1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #include <drm/display/drm_dsc_helper.h> 6 7 #include "reg_helper.h" 8 #include "dcn401_dsc.h" 9 #include "dsc/dscc_types.h" 10 #include "dsc/rc_calc.h" 11 12 #define MAX_THROUGHPUT_PER_DSC_100HZ 20000000 13 #define MAX_DSC_UNIT_COMBINE 4 14 15 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals); 16 17 /* Object I/F functions */ 18 //static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz); 19 //static bool dsc401_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps); 20 static void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc); 21 static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz); 22 23 static const struct dsc_funcs dcn401_dsc_funcs = { 24 .dsc_get_enc_caps = dsc401_get_enc_caps, 25 .dsc_read_state = dsc401_read_state, 26 .dsc_validate_stream = dsc401_validate_stream, 27 .dsc_set_config = dsc401_set_config, 28 .dsc_get_packed_pps = dsc2_get_packed_pps, 29 .dsc_enable = dsc401_enable, 30 .dsc_disable = dsc401_disable, 31 .dsc_disconnect = dsc401_disconnect, 32 .dsc_wait_disconnect_pending_clear = dsc401_wait_disconnect_pending_clear, 33 }; 34 35 /* Macro definitios for REG_SET macros*/ 36 #define CTX \ 37 dsc401->base.ctx 38 39 #define REG(reg)\ 40 dsc401->dsc_regs->reg 41 42 #undef FN 43 #define FN(reg_name, field_name) \ 44 dsc401->dsc_shift->field_name, dsc401->dsc_mask->field_name 45 #define DC_LOGGER \ 46 dsc->ctx->logger 47 48 49 /* API functions (external or via structure->function_pointer) */ 50 51 void dsc401_construct(struct dcn401_dsc *dsc, 52 struct dc_context *ctx, 53 int inst, 54 const struct dcn401_dsc_registers *dsc_regs, 55 const struct dcn401_dsc_shift *dsc_shift, 56 const struct dcn401_dsc_mask *dsc_mask) 57 { 58 dsc->base.ctx = ctx; 59 dsc->base.inst = inst; 60 dsc->base.funcs = &dcn401_dsc_funcs; 61 62 dsc->dsc_regs = dsc_regs; 63 dsc->dsc_shift = dsc_shift; 64 dsc->dsc_mask = dsc_mask; 65 66 dsc->max_image_width = 5184; 67 } 68 69 static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz) 70 { 71 int min_dsc_unit_required = (pixel_clock_100Hz + MAX_THROUGHPUT_PER_DSC_100HZ - 1) / MAX_THROUGHPUT_PER_DSC_100HZ; 72 73 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */ 74 75 /* 1 slice is only supported with 1 DSC unit */ 76 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = min_dsc_unit_required == 1 ? 1 : 0; 77 /* 2 slice is only supported with 1 or 2 DSC units */ 78 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = (min_dsc_unit_required == 1 || min_dsc_unit_required == 2) ? 1 : 0; 79 /* 3 slice is only supported with 1 DSC unit */ 80 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = min_dsc_unit_required == 1 ? 1 : 0; 81 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1; 82 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1; 83 dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 = 1; 84 dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 = 1; 85 86 dsc_enc_caps->lb_bit_depth = 13; 87 dsc_enc_caps->is_block_pred_supported = true; 88 89 dsc_enc_caps->color_formats.bits.RGB = 1; 90 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 91 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 92 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; 93 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 94 95 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; 96 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1; 97 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1; 98 dsc_enc_caps->max_total_throughput_mps = MAX_THROUGHPUT_PER_DSC_100HZ * MAX_DSC_UNIT_COMBINE; 99 100 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */ 101 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */ 102 } 103 104 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state 105 * into a dcn_dsc_state struct. 106 */ 107 void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s) 108 { 109 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 110 111 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); 112 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); 113 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel); 114 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height); 115 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size); 116 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width); 117 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height); 118 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset); 119 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en, 120 DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source); 121 } 122 123 124 bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) 125 { 126 struct dsc_optc_config dsc_optc_cfg; 127 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 128 129 if (dsc_cfg->pic_width > dsc401->max_image_width) 130 return false; 131 132 return dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, &dsc_optc_cfg); 133 } 134 135 void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 136 struct dsc_optc_config *dsc_optc_cfg) 137 { 138 bool is_config_ok; 139 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 140 141 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst); 142 dsc_config_log(dsc, dsc_cfg); 143 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc401->reg_vals, dsc_optc_cfg); 144 ASSERT(is_config_ok); 145 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):"); 146 dsc_log_pps(dsc, &dsc401->reg_vals.pps); 147 dsc_write_to_registers(dsc, &dsc401->reg_vals); 148 } 149 150 void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe) 151 { 152 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 153 int dsc_clock_en; 154 int dsc_fw_config; 155 int enabled_opp_pipe; 156 157 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe); 158 159 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 160 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 161 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { 162 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe); 163 ASSERT(0); 164 } 165 166 REG_UPDATE(DSC_TOP_CONTROL, 167 DSC_CLOCK_EN, 1); 168 169 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG, 170 DSCRM_DSC_FORWARD_EN, 1, 171 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe); 172 } 173 174 175 void dsc401_disable(struct display_stream_compressor *dsc) 176 { 177 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 178 int dsc_clock_en; 179 180 DC_LOG_DSC("disable DSC %d", dsc->inst); 181 182 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 183 if (!dsc_clock_en) { 184 DC_LOG_DSC("DSC %d already disabled!", dsc->inst); 185 } 186 187 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, 188 DSCRM_DSC_FORWARD_EN, 0); 189 190 REG_UPDATE(DSC_TOP_CONTROL, 191 DSC_CLOCK_EN, 0); 192 } 193 194 static void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc) 195 { 196 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 197 198 REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN_STATUS, 0, 2, 50000); 199 } 200 201 void dsc401_disconnect(struct display_stream_compressor *dsc) 202 { 203 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 204 205 DC_LOG_DSC("disconnect DSC %d", dsc->inst); 206 207 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, 208 DSCRM_DSC_FORWARD_EN, 0); 209 } 210 211 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals) 212 { 213 uint32_t temp_int; 214 struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); 215 216 REG_SET(DSC_DEBUG_CONTROL, 0, 217 DSC_DBG_EN, reg_vals->dsc_dbg_en); 218 219 // dsccif registers 220 REG_SET_2(DSCCIF_CONFIG0, 0, 221 //INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en, 222 //INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en, 223 //INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status, 224 INPUT_PIXEL_FORMAT, reg_vals->pixel_format, 225 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 226 227 /* REG_SET_2(DSCCIF_CONFIG1, 0, 228 PIC_WIDTH, reg_vals->pps.pic_width, 229 PIC_HEIGHT, reg_vals->pps.pic_height); 230 */ 231 // dscc registers 232 if (dsc401->dsc_mask->ICH_RESET_AT_END_OF_LINE == 0) { 233 REG_SET_3(DSCC_CONFIG0, 0, 234 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, 235 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en, 236 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1); 237 } else { 238 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE, 239 reg_vals->ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE, 240 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN, 241 reg_vals->alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, 242 reg_vals->num_slices_v - 1); 243 } 244 245 REG_SET(DSCC_CONFIG1, 0, 246 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size); 247 /*REG_SET_2(DSCC_CONFIG1, 0, 248 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size, 249 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/ 250 251 REG_SET_4(DSCC_INTERRUPT_CONTROL0, 0, 252 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0, reg_vals->rc_buffer_model_overflow_int_en[0], 253 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1, reg_vals->rc_buffer_model_overflow_int_en[1], 254 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2, reg_vals->rc_buffer_model_overflow_int_en[2], 255 DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3, reg_vals->rc_buffer_model_overflow_int_en[3]); 256 257 REG_SET_3(DSCC_PPS_CONFIG0, 0, 258 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor, 259 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth, 260 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 261 262 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 263 temp_int = reg_vals->bpp_x32; 264 else 265 temp_int = reg_vals->bpp_x32 >> 1; 266 267 REG_SET_7(DSCC_PPS_CONFIG1, 0, 268 BITS_PER_PIXEL, temp_int, 269 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422, 270 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB, 271 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable, 272 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422, 273 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420, 274 CHUNK_SIZE, reg_vals->pps.slice_chunk_size); 275 276 REG_SET_2(DSCC_PPS_CONFIG2, 0, 277 PIC_WIDTH, reg_vals->pps.pic_width, 278 PIC_HEIGHT, reg_vals->pps.pic_height); 279 280 REG_SET_2(DSCC_PPS_CONFIG3, 0, 281 SLICE_WIDTH, reg_vals->pps.slice_width, 282 SLICE_HEIGHT, reg_vals->pps.slice_height); 283 284 REG_SET(DSCC_PPS_CONFIG4, 0, 285 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay); 286 287 REG_SET_2(DSCC_PPS_CONFIG5, 0, 288 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value, 289 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval); 290 291 REG_SET_3(DSCC_PPS_CONFIG6, 0, 292 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval, 293 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset, 294 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset); 295 296 REG_SET_2(DSCC_PPS_CONFIG7, 0, 297 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset, 298 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset); 299 300 REG_SET_2(DSCC_PPS_CONFIG8, 0, 301 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset, 302 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj); 303 304 REG_SET_2(DSCC_PPS_CONFIG9, 0, 305 INITIAL_OFFSET, reg_vals->pps.initial_offset, 306 FINAL_OFFSET, reg_vals->pps.final_offset); 307 308 REG_SET_3(DSCC_PPS_CONFIG10, 0, 309 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp, 310 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp, 311 RC_MODEL_SIZE, reg_vals->pps.rc_model_size); 312 313 REG_SET_5(DSCC_PPS_CONFIG11, 0, 314 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor, 315 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0, 316 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1, 317 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low, 318 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high); 319 320 REG_SET_4(DSCC_PPS_CONFIG12, 0, 321 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0], 322 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1], 323 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2], 324 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]); 325 326 REG_SET_4(DSCC_PPS_CONFIG13, 0, 327 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4], 328 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5], 329 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6], 330 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]); 331 332 REG_SET_4(DSCC_PPS_CONFIG14, 0, 333 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8], 334 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9], 335 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10], 336 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]); 337 338 REG_SET_5(DSCC_PPS_CONFIG15, 0, 339 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12], 340 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13], 341 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, 342 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, 343 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); 344 345 REG_SET_6(DSCC_PPS_CONFIG16, 0, 346 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, 347 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, 348 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, 349 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, 350 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp, 351 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); 352 353 REG_SET_6(DSCC_PPS_CONFIG17, 0, 354 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp, 355 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp, 356 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, 357 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp, 358 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp, 359 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); 360 361 REG_SET_6(DSCC_PPS_CONFIG18, 0, 362 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp, 363 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp, 364 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, 365 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp, 366 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp, 367 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); 368 369 REG_SET_6(DSCC_PPS_CONFIG19, 0, 370 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp, 371 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp, 372 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, 373 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp, 374 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp, 375 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); 376 377 REG_SET_6(DSCC_PPS_CONFIG20, 0, 378 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp, 379 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp, 380 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, 381 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp, 382 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp, 383 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset); 384 385 REG_SET_6(DSCC_PPS_CONFIG21, 0, 386 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp, 387 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp, 388 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset, 389 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp, 390 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp, 391 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset); 392 393 REG_SET_6(DSCC_PPS_CONFIG22, 0, 394 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp, 395 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp, 396 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset, 397 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp, 398 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp, 399 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); 400 } 401 402 void dsc401_set_fgcg(struct dcn401_dsc *dsc401, bool enable) 403 { 404 REG_UPDATE(DSC_TOP_CONTROL, DSC_FGCG_REP_DIS, !enable); 405 } 406