1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 6 #include "dml2_internal_shared_types.h" 7 #include "dml21_translation_helper.h" 8 #include "dml2_internal_types.h" 9 #include "dml21_utils.h" 10 #include "dml2_dc_resource_mgmt.h" 11 12 #include "dml2_core_dcn4_calcs.h" 13 14 int dml21_helper_find_dml_pipe_idx_by_stream_id(struct dml2_context *ctx, unsigned int stream_id) 15 { 16 int i; 17 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { 18 if (ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] && ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[i] == stream_id) 19 return i; 20 } 21 22 return -1; 23 } 24 25 int dml21_find_dml_pipe_idx_by_plane_id(struct dml2_context *ctx, unsigned int plane_id) 26 { 27 int i; 28 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { 29 if (ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] && ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[i] == plane_id) 30 return i; 31 } 32 33 return -1; 34 } 35 36 bool dml21_get_plane_id(const struct dc_state *state, const struct dc_plane_state *plane, unsigned int *plane_id) 37 { 38 int i, j; 39 40 if (!plane_id) 41 return false; 42 43 for (i = 0; i < state->stream_count; i++) { 44 for (j = 0; j < state->stream_status[i].plane_count; j++) { 45 if (state->stream_status[i].plane_states[j] == plane) { 46 *plane_id = (i << 16) | j; 47 return true; 48 } 49 } 50 } 51 52 return false; 53 } 54 55 unsigned int dml21_get_dc_plane_idx_from_plane_id(unsigned int plane_id) 56 { 57 return 0xffff & plane_id; 58 } 59 60 void find_valid_pipe_idx_for_stream_index(const struct dml2_context *dml_ctx, unsigned int *dml_pipe_idx, unsigned int stream_index) 61 { 62 unsigned int i = 0; 63 64 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { 65 if (dml_ctx->v21.mode_programming.programming->plane_programming[i].plane_descriptor->stream_index == stream_index) { 66 *dml_pipe_idx = i; 67 return; 68 } 69 } 70 } 71 72 void find_pipe_regs_idx(const struct dml2_context *dml_ctx, 73 struct pipe_ctx *pipe, unsigned int *pipe_regs_idx) 74 { 75 struct pipe_ctx *opp_head = dml_ctx->config.callbacks.get_opp_head(pipe); 76 77 *pipe_regs_idx = dml_ctx->config.callbacks.get_odm_slice_index(opp_head); 78 79 if (pipe->plane_state) 80 *pipe_regs_idx += dml_ctx->config.callbacks.get_mpc_slice_index(pipe); 81 } 82 83 /* places pipe references into pipes arrays and returns number of pipes */ 84 int dml21_find_dc_pipes_for_plane(const struct dc *in_dc, 85 struct dc_state *context, 86 struct dml2_context *dml_ctx, 87 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__], 88 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__], 89 int dml_plane_idx) 90 { 91 unsigned int dml_stream_index; 92 unsigned int main_stream_id; 93 unsigned int dc_plane_index; 94 struct dc_stream_state *dc_main_stream; 95 struct dc_stream_status *dc_main_stream_status; 96 struct dc_plane_state *dc_main_plane; 97 struct dc_stream_state *dc_phantom_stream; 98 struct dc_stream_status *dc_phantom_stream_status; 99 struct dc_plane_state *dc_phantom_plane; 100 int num_pipes = 0; 101 102 memset(dc_main_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__); 103 memset(dc_phantom_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__); 104 105 dml_stream_index = dml_ctx->v21.mode_programming.programming->plane_programming[dml_plane_idx].plane_descriptor->stream_index; 106 main_stream_id = dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_stream_index]; 107 108 dc_main_stream = dml_ctx->config.callbacks.get_stream_from_id(context, main_stream_id); 109 dc_main_stream_status = dml_ctx->config.callbacks.get_stream_status(context, dc_main_stream); 110 if (!dc_main_stream_status) 111 return num_pipes; 112 113 /* find main plane based on id */ 114 dc_plane_index = dml21_get_dc_plane_idx_from_plane_id(dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[dml_plane_idx]); 115 dc_main_plane = dc_main_stream_status->plane_states[dc_plane_index]; 116 117 if (dc_main_plane) { 118 num_pipes = dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_main_plane, &context->res_ctx, dc_main_pipes); 119 } else { 120 /* stream was configured with dummy plane, so get pipes from opp head */ 121 struct pipe_ctx *otg_master_pipe = dml_ctx->config.callbacks.get_otg_master_for_stream(&context->res_ctx, dc_main_stream); 122 if (otg_master_pipe != NULL) 123 num_pipes = dml_ctx->config.callbacks.get_opp_heads_for_otg_master(otg_master_pipe, &context->res_ctx, dc_main_pipes); 124 } 125 126 /* if phantom exists, find associated pipes */ 127 dc_phantom_stream = dml_ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, dc_main_stream); 128 if (dc_phantom_stream && num_pipes > 0) { 129 dc_phantom_stream_status = dml_ctx->config.callbacks.get_stream_status(context, dc_phantom_stream); 130 131 if (dc_phantom_stream_status) { 132 /* phantom plane will have same index as main */ 133 dc_phantom_plane = dc_phantom_stream_status->plane_states[dc_plane_index]; 134 135 if (dc_phantom_plane) { 136 /* only care about phantom pipes if they contain the phantom plane */ 137 dml_ctx->config.callbacks.get_dpp_pipes_for_plane(dc_phantom_plane, &context->res_ctx, dc_phantom_pipes); 138 } 139 } 140 } 141 142 return num_pipes; 143 } 144 145 void dml21_pipe_populate_global_sync(struct dml2_context *dml_ctx, 146 struct dc_state *context, 147 struct pipe_ctx *pipe_ctx, 148 struct dml2_per_stream_programming *stream_programming) 149 { 150 union dml2_global_sync_programming *global_sync = &stream_programming->global_sync; 151 152 if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) { 153 /* phantom has its own global sync */ 154 global_sync = &stream_programming->phantom_stream.global_sync; 155 } 156 157 memcpy(&pipe_ctx->global_sync, 158 global_sync, 159 sizeof(union dml2_global_sync_programming)); 160 } 161 162 void dml21_populate_mall_allocation_size(struct dc_state *context, 163 struct dml2_context *in_ctx, 164 struct dml2_per_plane_programming *pln_prog, 165 struct pipe_ctx *dc_pipe) 166 { 167 168 /* Reuse MALL Allocation Sizes logic from dcn32_fpu.c */ 169 /* Count from active, top pipes per plane only. Only add mall_ss_size_bytes for each unique plane. */ 170 if (dc_pipe->stream && dc_pipe->plane_state && 171 (dc_pipe->top_pipe == NULL || 172 dc_pipe->plane_state != dc_pipe->top_pipe->plane_state) && 173 dc_pipe->prev_odm_pipe == NULL) { 174 /* SS: all active surfaces stored in MALL */ 175 if (in_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, dc_pipe) != SUBVP_PHANTOM) { 176 dc_pipe->surface_size_in_mall_bytes = pln_prog->surface_size_mall_bytes; 177 context->bw_ctx.bw.dcn.mall_ss_size_bytes += dc_pipe->surface_size_in_mall_bytes; 178 } else { 179 /* SUBVP: phantom surfaces only stored in MALL */ 180 dc_pipe->surface_size_in_mall_bytes = pln_prog->svp_size_mall_bytes; 181 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += dc_pipe->surface_size_in_mall_bytes; 182 } 183 } 184 } 185 186 bool check_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx) 187 { 188 /* If this assert is hit then we have a link encoder dynamic management issue */ 189 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true); 190 return (pipe_ctx->stream_res.hpo_dp_stream_enc && 191 pipe_ctx->link_res.hpo_dp_link_enc && 192 dc_is_dp_signal(pipe_ctx->stream->signal)); 193 } 194 195 196 static bool is_sub_vp_enabled(struct dc *dc, struct dc_state *context) 197 { 198 int i; 199 200 for (i = 0; i < dc->res_pool->pipe_count; i++) { 201 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 202 203 if (pipe_ctx->stream && dc_state_get_paired_subvp_stream(context, pipe_ctx->stream) && 204 dc_state_get_pipe_subvp_type(context, pipe_ctx) == SUBVP_MAIN) { 205 return true; 206 } 207 } 208 return false; 209 } 210 211 212 void dml21_program_dc_pipe(struct dml2_context *dml_ctx, struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, 213 struct dml2_per_stream_programming *stream_prog) 214 { 215 unsigned int pipe_reg_index = 0; 216 217 dml21_pipe_populate_global_sync(dml_ctx, context, pipe_ctx, stream_prog); 218 find_pipe_regs_idx(dml_ctx, pipe_ctx, &pipe_reg_index); 219 220 if (dml_ctx->config.svp_pstate.callbacks.get_pipe_subvp_type(context, pipe_ctx) == SUBVP_PHANTOM) { 221 memcpy(&pipe_ctx->hubp_regs, pln_prog->phantom_plane.pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set)); 222 pipe_ctx->unbounded_req = false; 223 pipe_ctx->det_buffer_size_kb = 0; 224 } else { 225 memcpy(&pipe_ctx->hubp_regs, pln_prog->pipe_regs[pipe_reg_index], sizeof(struct dml2_dchub_per_pipe_register_set)); 226 pipe_ctx->unbounded_req = pln_prog->pipe_regs[pipe_reg_index]->rq_regs.unbounded_request_enabled; 227 pipe_ctx->det_buffer_size_kb = pln_prog->pipe_regs[pipe_reg_index]->det_size * 64; 228 } 229 230 pipe_ctx->plane_res.bw.dppclk_khz = pln_prog->min_clocks.dcn4x.dppclk_khz; 231 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipe_ctx->plane_res.bw.dppclk_khz) 232 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipe_ctx->plane_res.bw.dppclk_khz; 233 234 dml21_populate_mall_allocation_size(context, dml_ctx, pln_prog, pipe_ctx); 235 memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[pipe_ctx->pipe_idx], &pln_prog->mcache_allocation, sizeof(struct dml2_mcache_surface_allocation)); 236 237 bool sub_vp_enabled = is_sub_vp_enabled(pipe_ctx->stream->ctx->dc, context); 238 239 dml21_set_dc_p_state_type(pipe_ctx, stream_prog, sub_vp_enabled); 240 } 241 242 static struct dc_stream_state *dml21_add_phantom_stream(struct dml2_context *dml_ctx, 243 const struct dc *dc, 244 struct dc_state *context, 245 struct dc_stream_state *main_stream, 246 struct dml2_per_stream_programming *stream_programming) 247 { 248 struct dc_stream_state *phantom_stream; 249 struct dml2_stream_parameters *phantom_stream_descriptor = &stream_programming->phantom_stream.descriptor; 250 251 phantom_stream = dml_ctx->config.svp_pstate.callbacks.create_phantom_stream(dc, context, main_stream); 252 if (!phantom_stream) 253 return NULL; 254 255 /* copy details of phantom stream from main */ 256 memcpy(&phantom_stream->timing, &main_stream->timing, sizeof(phantom_stream->timing)); 257 memcpy(&phantom_stream->src, &main_stream->src, sizeof(phantom_stream->src)); 258 memcpy(&phantom_stream->dst, &main_stream->dst, sizeof(phantom_stream->dst)); 259 260 /* modify timing for phantom */ 261 phantom_stream->timing.v_front_porch = phantom_stream_descriptor->timing.v_front_porch; 262 phantom_stream->timing.v_addressable = phantom_stream_descriptor->timing.v_active; 263 phantom_stream->timing.v_total = phantom_stream_descriptor->timing.v_total; 264 phantom_stream->timing.flags.DSC = 0; // phantom always has DSC disabled 265 266 phantom_stream->dst.y = 0; 267 phantom_stream->dst.height = stream_programming->phantom_stream.descriptor.timing.v_active; 268 269 phantom_stream->src.y = 0; 270 phantom_stream->src.height = (double)phantom_stream_descriptor->timing.v_active * (double)main_stream->src.height / (double)main_stream->dst.height; 271 272 phantom_stream->use_dynamic_meta = false; 273 274 dml_ctx->config.svp_pstate.callbacks.add_phantom_stream(dc, context, phantom_stream, main_stream); 275 276 return phantom_stream; 277 } 278 279 static struct dc_plane_state *dml21_add_phantom_plane(struct dml2_context *dml_ctx, 280 const struct dc *dc, 281 struct dc_state *context, 282 struct dc_stream_state *phantom_stream, 283 struct dc_plane_state *main_plane, 284 struct dml2_per_plane_programming *plane_programming) 285 { 286 struct dc_plane_state *phantom_plane; 287 288 phantom_plane = dml_ctx->config.svp_pstate.callbacks.create_phantom_plane(dc, context, main_plane); 289 if (!phantom_plane) 290 return NULL; 291 292 phantom_plane->format = main_plane->format; 293 phantom_plane->rotation = main_plane->rotation; 294 phantom_plane->visible = main_plane->visible; 295 296 memcpy(&phantom_plane->address, &main_plane->address, sizeof(phantom_plane->address)); 297 memcpy(&phantom_plane->scaling_quality, &main_plane->scaling_quality, 298 sizeof(phantom_plane->scaling_quality)); 299 memcpy(&phantom_plane->src_rect, &main_plane->src_rect, sizeof(phantom_plane->src_rect)); 300 memcpy(&phantom_plane->dst_rect, &main_plane->dst_rect, sizeof(phantom_plane->dst_rect)); 301 memcpy(&phantom_plane->clip_rect, &main_plane->clip_rect, sizeof(phantom_plane->clip_rect)); 302 memcpy(&phantom_plane->plane_size, &main_plane->plane_size, 303 sizeof(phantom_plane->plane_size)); 304 memcpy(&phantom_plane->tiling_info, &main_plane->tiling_info, 305 sizeof(phantom_plane->tiling_info)); 306 memcpy(&phantom_plane->dcc, &main_plane->dcc, sizeof(phantom_plane->dcc)); 307 308 phantom_plane->format = main_plane->format; 309 phantom_plane->rotation = main_plane->rotation; 310 phantom_plane->visible = main_plane->visible; 311 312 /* Shadow pipe has small viewport. */ 313 phantom_plane->clip_rect.y = 0; 314 phantom_plane->clip_rect.height = phantom_stream->src.height; 315 316 dml_ctx->config.svp_pstate.callbacks.add_phantom_plane(dc, phantom_stream, phantom_plane, context); 317 318 return phantom_plane; 319 } 320 321 void dml21_handle_phantom_streams_planes(const struct dc *dc, struct dc_state *context, struct dml2_context *dml_ctx) 322 { 323 unsigned int dml_stream_index, dml_plane_index, dc_plane_index; 324 struct dc_stream_state *main_stream; 325 struct dc_stream_status *main_stream_status; 326 struct dc_stream_state *phantom_stream; 327 struct dc_plane_state *main_plane; 328 bool phantoms_added = false; 329 330 /* create phantom streams and planes and add to context */ 331 for (dml_stream_index = 0; dml_stream_index < dml_ctx->v21.mode_programming.programming->display_config.num_streams; dml_stream_index++) { 332 /* iterate through DML streams looking for phantoms */ 333 if (dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_index].phantom_stream.enabled) { 334 /* find associated dc stream */ 335 main_stream = dml_ctx->config.callbacks.get_stream_from_id(context, 336 dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[dml_stream_index]); 337 338 main_stream_status = dml_ctx->config.callbacks.get_stream_status(context, main_stream); 339 340 if (!main_stream_status || main_stream_status->plane_count == 0) 341 continue; 342 343 /* create phantom stream for subvp enabled stream */ 344 phantom_stream = dml21_add_phantom_stream(dml_ctx, 345 dc, 346 context, 347 main_stream, 348 &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_index]); 349 350 if (!phantom_stream) 351 continue; 352 353 /* iterate through DML planes associated with this stream */ 354 for (dml_plane_index = 0; dml_plane_index < dml_ctx->v21.mode_programming.programming->display_config.num_planes; dml_plane_index++) { 355 if (dml_ctx->v21.mode_programming.programming->plane_programming[dml_plane_index].plane_descriptor->stream_index == dml_stream_index) { 356 /* find associated dc plane */ 357 dc_plane_index = dml21_get_dc_plane_idx_from_plane_id(dml_ctx->v21.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[dml_plane_index]); 358 main_plane = main_stream_status->plane_states[dc_plane_index]; 359 360 /* create phantom planes for subvp enabled plane */ 361 dml21_add_phantom_plane(dml_ctx, 362 dc, 363 context, 364 phantom_stream, 365 main_plane, 366 &dml_ctx->v21.mode_programming.programming->plane_programming[dml_plane_index]); 367 368 phantoms_added = true; 369 } 370 } 371 } 372 } 373 374 if (phantoms_added) 375 dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, dc->current_state); 376 } 377 378 void dml21_build_fams2_programming(const struct dc *dc, 379 struct dc_state *context, 380 struct dml2_context *dml_ctx) 381 { 382 int i, j, k; 383 unsigned int num_fams2_streams = 0; 384 385 /* reset fams2 data */ 386 memset(&context->bw_ctx.bw.dcn.fams2_stream_base_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES); 387 memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES); 388 memset(&context->bw_ctx.bw.dcn.fams2_global_config, 0, sizeof(struct dmub_cmd_fams2_global_config)); 389 390 if (dml_ctx->v21.mode_programming.programming->fams2_required) { 391 for (i = 0; i < context->stream_count; i++) { 392 int dml_stream_idx; 393 struct dc_stream_state *phantom_stream; 394 struct dc_stream_status *phantom_status; 395 enum fams2_stream_type type = 0; 396 397 union dmub_cmd_fams2_config *static_base_state = &context->bw_ctx.bw.dcn.fams2_stream_base_params[num_fams2_streams]; 398 union dmub_cmd_fams2_config *static_sub_state = &context->bw_ctx.bw.dcn.fams2_stream_sub_params[num_fams2_streams]; 399 400 struct dc_stream_state *stream = context->streams[i]; 401 402 if (context->stream_status[i].plane_count == 0 || 403 dml_ctx->config.svp_pstate.callbacks.get_stream_subvp_type(context, stream) == SUBVP_PHANTOM) { 404 /* can ignore blanked or phantom streams */ 405 continue; 406 } 407 408 dml_stream_idx = dml21_helper_find_dml_pipe_idx_by_stream_id(dml_ctx, stream->stream_id); 409 if (dml_stream_idx < 0) { 410 ASSERT(dml_stream_idx >= 0); 411 continue; 412 } 413 414 /* copy static state from PMO */ 415 memcpy(static_base_state, 416 &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_base_params, 417 sizeof(union dmub_cmd_fams2_config)); 418 memcpy(static_sub_state, 419 &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_sub_params, 420 sizeof(union dmub_cmd_fams2_config)); 421 422 switch (dc->debug.fams_version.minor) { 423 case 1: 424 default: 425 type = static_base_state->stream_v1.base.type; 426 427 /* get information from context */ 428 static_base_state->stream_v1.base.num_planes = context->stream_status[i].plane_count; 429 static_base_state->stream_v1.base.otg_inst = context->stream_status[i].primary_otg_inst; 430 431 /* populate pipe masks for planes */ 432 for (j = 0; j < context->stream_status[i].plane_count; j++) { 433 for (k = 0; k < dc->res_pool->pipe_count; k++) { 434 if (context->res_ctx.pipe_ctx[k].stream && 435 context->res_ctx.pipe_ctx[k].stream->stream_id == stream->stream_id && 436 context->res_ctx.pipe_ctx[k].plane_state == context->stream_status[i].plane_states[j]) { 437 static_base_state->stream_v1.base.pipe_mask |= (1 << k); 438 static_base_state->stream_v1.base.plane_pipe_masks[j] |= (1 << k); 439 } 440 } 441 } 442 } 443 444 445 /* get per method programming */ 446 switch (type) { 447 case FAMS2_STREAM_TYPE_VBLANK: 448 case FAMS2_STREAM_TYPE_VACTIVE: 449 case FAMS2_STREAM_TYPE_DRR: 450 break; 451 case FAMS2_STREAM_TYPE_SUBVP: 452 phantom_stream = dml_ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, stream); 453 if (!phantom_stream) 454 break; 455 456 phantom_status = dml_ctx->config.callbacks.get_stream_status(context, phantom_stream); 457 458 /* phantom status should always be present */ 459 ASSERT(phantom_status); 460 if (!phantom_status) 461 break; 462 463 switch (dc->debug.fams_version.minor) { 464 case 1: 465 default: 466 static_sub_state->stream_v1.sub_state.subvp.phantom_otg_inst = phantom_status->primary_otg_inst; 467 468 /* populate pipe masks for phantom planes */ 469 for (j = 0; j < phantom_status->plane_count; j++) { 470 for (k = 0; k < dc->res_pool->pipe_count; k++) { 471 if (context->res_ctx.pipe_ctx[k].stream && 472 context->res_ctx.pipe_ctx[k].stream->stream_id == phantom_stream->stream_id && 473 context->res_ctx.pipe_ctx[k].plane_state == phantom_status->plane_states[j]) { 474 switch (dc->debug.fams_version.minor) { 475 case 1: 476 default: 477 static_sub_state->stream_v1.sub_state.subvp.phantom_pipe_mask |= (1 << k); 478 static_sub_state->stream_v1.sub_state.subvp.phantom_plane_pipe_masks[j] |= (1 << k); 479 } 480 } 481 } 482 } 483 } 484 break; 485 default: 486 ASSERT(false); 487 break; 488 } 489 490 num_fams2_streams++; 491 } 492 } 493 494 if (num_fams2_streams > 0) { 495 /* copy FAMS2 configuration */ 496 memcpy(&context->bw_ctx.bw.dcn.fams2_global_config, 497 &dml_ctx->v21.mode_programming.programming->fams2_global_config, 498 sizeof(struct dmub_cmd_fams2_global_config)); 499 500 context->bw_ctx.bw.dcn.fams2_global_config.num_streams = num_fams2_streams; 501 } 502 503 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable; 504 } 505 506 bool dml21_is_plane1_enabled(enum dml2_source_format_class source_format) 507 { 508 return source_format >= dml2_420_8 && source_format <= dml2_rgbe_alpha; 509 } 510