xref: /linux/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h (revision 260f6f4fda93c8485c8037865c941b42b9cba5d2)
13df528beSRodrigo Siqueira // SPDX-License-Identifier: MIT
23df528beSRodrigo Siqueira //
33df528beSRodrigo Siqueira // Copyright 2024 Advanced Micro Devices, Inc.
4c7ddc0a8SBhawanpreet Lakha 
5c7ddc0a8SBhawanpreet Lakha #ifndef _DMUB_REPLAY_H_
6c7ddc0a8SBhawanpreet Lakha #define _DMUB_REPLAY_H_
7c7ddc0a8SBhawanpreet Lakha 
8c7ddc0a8SBhawanpreet Lakha #include "dc_types.h"
9c7ddc0a8SBhawanpreet Lakha #include "dmub_cmd.h"
10c7ddc0a8SBhawanpreet Lakha struct dc_link;
11c7ddc0a8SBhawanpreet Lakha struct dmub_replay_funcs;
12c7ddc0a8SBhawanpreet Lakha 
13c7ddc0a8SBhawanpreet Lakha struct dmub_replay {
14c7ddc0a8SBhawanpreet Lakha 	struct dc_context *ctx;
15c7ddc0a8SBhawanpreet Lakha 	const struct dmub_replay_funcs *funcs;
16c7ddc0a8SBhawanpreet Lakha };
17c7ddc0a8SBhawanpreet Lakha 
18c7ddc0a8SBhawanpreet Lakha struct dmub_replay_funcs {
19c7ddc0a8SBhawanpreet Lakha 	void (*replay_get_state)(struct dmub_replay *dmub, enum replay_state *state,
20c7ddc0a8SBhawanpreet Lakha 		uint8_t panel_inst);
21c7ddc0a8SBhawanpreet Lakha 	void (*replay_enable)(struct dmub_replay *dmub, bool enable, bool wait,
22*1f26214dSOvidiu Bunea 		uint8_t panel_inst, struct dc_link *link);
23c7ddc0a8SBhawanpreet Lakha 	bool (*replay_copy_settings)(struct dmub_replay *dmub, struct dc_link *link,
24c7ddc0a8SBhawanpreet Lakha 		struct replay_context *replay_context, uint8_t panel_inst);
25c7ddc0a8SBhawanpreet Lakha 	void (*replay_set_power_opt)(struct dmub_replay *dmub, unsigned int power_opt,
26c7ddc0a8SBhawanpreet Lakha 		uint8_t panel_inst);
27cee6de12SDennis Chan 	void (*replay_send_cmd)(struct dmub_replay *dmub,
2837f4382bSMax Tseng 		enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_element);
29a3324a67SChunTao Tso 	void (*replay_set_coasting_vtotal)(struct dmub_replay *dmub, uint32_t coasting_vtotal,
30c7ddc0a8SBhawanpreet Lakha 		uint8_t panel_inst);
31c7ddc0a8SBhawanpreet Lakha 	void (*replay_residency)(struct dmub_replay *dmub,
32a63e1c04SLeon Huang 		uint8_t panel_inst, uint32_t *residency, const bool is_start, const enum pr_residency_mode mode);
33e379787cSTom Chung 	void (*replay_set_power_opt_and_coasting_vtotal)(struct dmub_replay *dmub,
34a3324a67SChunTao Tso 		unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal);
35c7ddc0a8SBhawanpreet Lakha };
36c7ddc0a8SBhawanpreet Lakha 
37c7ddc0a8SBhawanpreet Lakha struct dmub_replay *dmub_replay_create(struct dc_context *ctx);
38c7ddc0a8SBhawanpreet Lakha void dmub_replay_destroy(struct dmub_replay **dmub);
39c7ddc0a8SBhawanpreet Lakha 
40c7ddc0a8SBhawanpreet Lakha 
41c7ddc0a8SBhawanpreet Lakha #endif /* _DMUB_REPLAY_H_ */
42