1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "amdgpu_dm_psr.h" 27 #include "dc_dmub_srv.h" 28 #include "dc.h" 29 #include "dm_helpers.h" 30 #include "amdgpu_dm.h" 31 #include "modules/power/power_helpers.h" 32 33 static bool link_supports_psrsu(struct dc_link *link) 34 { 35 struct dc *dc = link->ctx->dc; 36 37 if (!dc->caps.dmcub_support) 38 return false; 39 40 if (dc->ctx->dce_version < DCN_VERSION_3_1) 41 return false; 42 43 if (!is_psr_su_specific_panel(link)) 44 return false; 45 46 if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP || 47 !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) 48 return false; 49 50 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED && 51 !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap) 52 return false; 53 54 if (amdgpu_dc_debug_mask & DC_DISABLE_PSR_SU) 55 return false; 56 57 /* Temporarily disable PSR-SU to avoid glitches */ 58 return false; 59 } 60 61 /* 62 * amdgpu_dm_set_psr_caps() - set link psr capabilities 63 * @link: link 64 * 65 */ 66 void amdgpu_dm_set_psr_caps(struct dc_link *link) 67 { 68 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) { 69 link->psr_settings.psr_feature_enabled = false; 70 return; 71 } 72 73 if (link->type == dc_connection_none) { 74 link->psr_settings.psr_feature_enabled = false; 75 return; 76 } 77 78 if (link->dpcd_caps.psr_info.psr_version == 0) { 79 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 80 link->psr_settings.psr_feature_enabled = false; 81 82 } else { 83 if (link_supports_psrsu(link)) 84 link->psr_settings.psr_version = DC_PSR_VERSION_SU_1; 85 else 86 link->psr_settings.psr_version = DC_PSR_VERSION_1; 87 88 link->psr_settings.psr_feature_enabled = true; 89 } 90 } 91 92 /* 93 * amdgpu_dm_link_setup_psr() - configure psr link 94 * @stream: stream state 95 * 96 * Return: true if success 97 */ 98 bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) 99 { 100 struct dc_link *link = NULL; 101 struct psr_config psr_config = {0}; 102 struct psr_context psr_context = {0}; 103 struct dc *dc = NULL; 104 bool ret = false; 105 106 if (stream == NULL) 107 return false; 108 109 link = stream->link; 110 dc = link->ctx->dc; 111 112 if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) { 113 mod_power_calc_psr_configs(&psr_config, link, stream); 114 115 /* linux DM specific updating for psr config fields */ 116 psr_config.allow_smu_optimizations = 117 (amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) && 118 mod_power_only_edp(dc->current_state, stream); 119 psr_config.allow_multi_disp_optimizations = 120 (amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT); 121 122 if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) { 123 if (!psr_su_set_dsc_slice_height(dc, link, stream, &psr_config)) 124 return false; 125 } 126 127 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context); 128 129 } 130 DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled); 131 132 return ret; 133 } 134 135 /* 136 * amdgpu_dm_psr_enable() - enable psr f/w 137 * @stream: stream state 138 * 139 */ 140 void amdgpu_dm_psr_enable(struct dc_stream_state *stream) 141 { 142 struct dc_link *link = stream->link; 143 unsigned int vsync_rate_hz = 0; 144 struct dc_static_screen_params params = {0}; 145 /* Calculate number of static frames before generating interrupt to 146 * enter PSR. 147 */ 148 // Init fail safe of 2 frames static 149 unsigned int num_frames_static = 2; 150 unsigned int power_opt = 0; 151 bool psr_enable = true; 152 153 DRM_DEBUG_DRIVER("Enabling psr...\n"); 154 155 vsync_rate_hz = div64_u64(div64_u64(( 156 stream->timing.pix_clk_100hz * (uint64_t)100), 157 stream->timing.v_total), 158 stream->timing.h_total); 159 160 /* Round up 161 * Calculate number of frames such that at least 30 ms of time has 162 * passed. 163 */ 164 if (vsync_rate_hz != 0) { 165 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz; 166 167 num_frames_static = (30000 / frame_time_microsec) + 1; 168 } 169 170 params.triggers.cursor_update = true; 171 params.triggers.overlay_update = true; 172 params.triggers.surface_update = true; 173 params.num_frames = num_frames_static; 174 175 dc_stream_set_static_screen_params(link->ctx->dc, 176 &stream, 1, 177 ¶ms); 178 179 /* 180 * Only enable static-screen optimizations for PSR1. For PSR SU, this 181 * causes vstartup interrupt issues, used by amdgpu_dm to send vblank 182 * events. 183 */ 184 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) 185 power_opt |= psr_power_opt_z10_static_screen; 186 187 dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt); 188 189 if (link->ctx->dc->caps.ips_support) 190 dc_allow_idle_optimizations(link->ctx->dc, true); 191 } 192 193 /* 194 * amdgpu_dm_psr_disable() - disable psr f/w 195 * @stream: stream state 196 * 197 * Return: true if success 198 */ 199 bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait) 200 { 201 bool psr_enable = false; 202 203 DRM_DEBUG_DRIVER("Disabling psr...\n"); 204 205 return dc_link_set_psr_allow_active(stream->link, &psr_enable, wait, false, NULL); 206 } 207 208 /* 209 * amdgpu_dm_psr_disable_all() - disable psr f/w for all streams 210 * if psr is enabled on any stream 211 * 212 * Return: true if success 213 */ 214 bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm) 215 { 216 DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n"); 217 return dc_set_psr_allow_active(dm->dc, false); 218 } 219 220 /* 221 * amdgpu_dm_psr_is_active_allowed() - check if psr is allowed on any stream 222 * @dm: pointer to amdgpu_display_manager 223 * 224 * Return: true if allowed 225 */ 226 227 bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm) 228 { 229 unsigned int i; 230 bool allow_active = false; 231 232 for (i = 0; i < dm->dc->current_state->stream_count ; i++) { 233 struct dc_link *link; 234 struct dc_stream_state *stream = dm->dc->current_state->streams[i]; 235 236 link = stream->link; 237 if (!link) 238 continue; 239 if (link->psr_settings.psr_feature_enabled && 240 link->psr_settings.psr_allow_active) { 241 allow_active = true; 242 break; 243 } 244 } 245 246 return allow_active; 247 } 248 249 /** 250 * amdgpu_dm_psr_wait_disable() - Wait for eDP panel to exit PSR 251 * @stream: stream state attached to the eDP link 252 * 253 * Waits for a max of 500ms for the eDP panel to exit PSR. 254 * 255 * Return: true if panel exited PSR, false otherwise. 256 */ 257 bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream) 258 { 259 enum dc_psr_state psr_state = PSR_STATE0; 260 struct dc_link *link = stream->link; 261 int retry_count; 262 263 if (link == NULL) 264 return false; 265 266 for (retry_count = 0; retry_count <= 1000; retry_count++) { 267 dc_link_get_psr_state(link, &psr_state); 268 if (psr_state == PSR_STATE0) 269 break; 270 udelay(500); 271 } 272 273 if (retry_count == 1000) 274 return false; 275 276 return true; 277 } 278