1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2016-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v9_structs.h" 31 #include "gc/gc_9_0_offset.h" 32 #include "gc/gc_9_0_sh_mask.h" 33 #include "sdma0/sdma0_4_0_sh_mask.h" 34 #include "amdgpu_amdkfd.h" 35 #include "kfd_device_queue_manager.h" 36 37 static void update_mqd(struct mqd_manager *mm, void *mqd, 38 struct queue_properties *q, 39 struct mqd_update_info *minfo); 40 41 static uint64_t mqd_stride_v9(struct mqd_manager *mm, 42 struct queue_properties *q) 43 { 44 if (mm->dev->kfd->cwsr_enabled && 45 q->type == KFD_QUEUE_TYPE_COMPUTE) 46 return ALIGN(q->ctl_stack_size, PAGE_SIZE) + 47 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE); 48 49 return mm->mqd_size; 50 } 51 52 static inline struct v9_mqd *get_mqd(void *mqd) 53 { 54 return (struct v9_mqd *)mqd; 55 } 56 57 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 58 { 59 return (struct v9_sdma_mqd *)mqd; 60 } 61 62 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 63 struct mqd_update_info *minfo, uint32_t inst) 64 { 65 struct v9_mqd *m; 66 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; 67 68 if (!minfo || !minfo->cu_mask.ptr) 69 return; 70 71 mqd_symmetrically_map_cu_mask(mm, 72 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, inst); 73 74 m = get_mqd(mqd); 75 76 m->compute_static_thread_mgmt_se0 = se_mask[0]; 77 m->compute_static_thread_mgmt_se1 = se_mask[1]; 78 m->compute_static_thread_mgmt_se2 = se_mask[2]; 79 m->compute_static_thread_mgmt_se3 = se_mask[3]; 80 if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3) && 81 KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 4) && 82 KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 5, 0)) { 83 m->compute_static_thread_mgmt_se4 = se_mask[4]; 84 m->compute_static_thread_mgmt_se5 = se_mask[5]; 85 m->compute_static_thread_mgmt_se6 = se_mask[6]; 86 m->compute_static_thread_mgmt_se7 = se_mask[7]; 87 88 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", 89 m->compute_static_thread_mgmt_se0, 90 m->compute_static_thread_mgmt_se1, 91 m->compute_static_thread_mgmt_se2, 92 m->compute_static_thread_mgmt_se3, 93 m->compute_static_thread_mgmt_se4, 94 m->compute_static_thread_mgmt_se5, 95 m->compute_static_thread_mgmt_se6, 96 m->compute_static_thread_mgmt_se7); 97 } else { 98 pr_debug("inst: %u, update cu mask to %#x %#x %#x %#x\n", 99 inst, m->compute_static_thread_mgmt_se0, 100 m->compute_static_thread_mgmt_se1, 101 m->compute_static_thread_mgmt_se2, 102 m->compute_static_thread_mgmt_se3); 103 } 104 } 105 106 static void set_priority(struct v9_mqd *m, struct queue_properties *q) 107 { 108 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 109 m->cp_hqd_queue_priority = q->priority; 110 } 111 112 static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, 113 struct queue_properties *q) 114 { 115 int retval; 116 struct kfd_mem_obj *mqd_mem_obj = NULL; 117 118 /* For V9 only, due to a HW bug, the control stack of a user mode 119 * compute queue needs to be allocated just behind the page boundary 120 * of its regular MQD buffer. So we allocate an enlarged MQD buffer: 121 * the first page of the buffer serves as the regular MQD buffer 122 * purpose and the remaining is for control stack. Although the two 123 * parts are in the same buffer object, they need different memory 124 * types: MQD part needs UC (uncached) as usual, while control stack 125 * needs NC (non coherent), which is different from the UC type which 126 * is used when control stack is allocated in user space. 127 * 128 * Because of all those, we use the gtt allocation function instead 129 * of sub-allocation function for this enlarged MQD buffer. Moreover, 130 * in order to achieve two memory types in a single buffer object, we 131 * pass a special bo flag AMDGPU_GEM_CREATE_CP_MQD_GFX9 to instruct 132 * amdgpu memory functions to do so. 133 */ 134 if (node->kfd->cwsr_enabled && (q->type == KFD_QUEUE_TYPE_COMPUTE)) { 135 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 136 if (!mqd_mem_obj) 137 return NULL; 138 retval = amdgpu_amdkfd_alloc_gtt_mem(node->adev, 139 (ALIGN(q->ctl_stack_size, PAGE_SIZE) + 140 ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) * 141 NUM_XCC(node->xcc_mask), 142 &(mqd_mem_obj->gtt_mem), 143 &(mqd_mem_obj->gpu_addr), 144 (void *)&(mqd_mem_obj->cpu_ptr), true); 145 146 if (retval) { 147 kfree(mqd_mem_obj); 148 return NULL; 149 } 150 } else { 151 retval = kfd_gtt_sa_allocate(node, sizeof(struct v9_mqd), 152 &mqd_mem_obj); 153 if (retval) 154 return NULL; 155 } 156 157 return mqd_mem_obj; 158 } 159 160 static void init_mqd(struct mqd_manager *mm, void **mqd, 161 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 162 struct queue_properties *q) 163 { 164 uint64_t addr; 165 struct v9_mqd *m; 166 167 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 168 addr = mqd_mem_obj->gpu_addr; 169 170 memset(m, 0, sizeof(struct v9_mqd)); 171 172 m->header = 0xC0310800; 173 m->compute_pipelinestat_enable = 1; 174 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 175 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 176 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 177 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 178 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; 179 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; 180 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; 181 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; 182 183 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 184 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 185 186 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 187 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 188 189 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 190 191 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 192 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 193 194 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 195 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 196 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 197 198 /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the 199 * DISPATCH_PTR. This is required for the kfd debugger 200 */ 201 m->cp_hqd_hq_status0 = 1 << 14; 202 203 if (q->format == KFD_QUEUE_FORMAT_AQL) 204 m->cp_hqd_aql_control = 205 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 206 207 if (q->tba_addr) { 208 m->compute_pgm_rsrc2 |= 209 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); 210 } 211 212 if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) { 213 m->cp_hqd_persistent_state |= 214 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 215 m->cp_hqd_ctx_save_base_addr_lo = 216 lower_32_bits(q->ctx_save_restore_area_address); 217 m->cp_hqd_ctx_save_base_addr_hi = 218 upper_32_bits(q->ctx_save_restore_area_address); 219 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 220 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 221 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 222 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 223 } 224 225 *mqd = m; 226 if (gart_addr) 227 *gart_addr = addr; 228 update_mqd(mm, m, q, NULL); 229 } 230 231 static int load_mqd(struct mqd_manager *mm, void *mqd, 232 uint32_t pipe_id, uint32_t queue_id, 233 struct queue_properties *p, struct mm_struct *mms) 234 { 235 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 236 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 237 238 return mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 239 (uint32_t __user *)p->write_ptr, 240 wptr_shift, 0, mms, 0); 241 } 242 243 static void update_mqd(struct mqd_manager *mm, void *mqd, 244 struct queue_properties *q, 245 struct mqd_update_info *minfo) 246 { 247 struct v9_mqd *m; 248 249 m = get_mqd(mqd); 250 251 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; 252 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; 253 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 254 255 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 256 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 257 258 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 259 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 260 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 261 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 262 263 m->cp_hqd_pq_doorbell_control = 264 q->doorbell_off << 265 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 266 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 267 m->cp_hqd_pq_doorbell_control); 268 269 m->cp_hqd_ib_control = 270 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT | 271 1 << CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT; 272 273 /* 274 * HW does not clamp this field correctly. Maximum EOP queue size 275 * is constrained by per-SE EOP done signal count, which is 8-bit. 276 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 277 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 278 * is safe, giving a maximum field value of 0xA. 279 * 280 * Also, do calculation only if EOP is used (size > 0), otherwise 281 * the order_base_2 calculation provides incorrect result. 282 * 283 */ 284 m->cp_hqd_eop_control = q->eop_ring_buffer_size ? 285 min(0xA, order_base_2(q->eop_ring_buffer_size / 4) - 1) : 0; 286 287 m->cp_hqd_eop_base_addr_lo = 288 lower_32_bits(q->eop_ring_buffer_address >> 8); 289 m->cp_hqd_eop_base_addr_hi = 290 upper_32_bits(q->eop_ring_buffer_address >> 8); 291 292 m->cp_hqd_iq_timer = 0; 293 294 m->cp_hqd_vmid = q->vmid; 295 296 if (q->format == KFD_QUEUE_FORMAT_AQL) { 297 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 298 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 299 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT | 300 1 << CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT; 301 m->cp_hqd_pq_doorbell_control |= 1 << 302 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 303 } 304 if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) 305 m->cp_hqd_ctx_save_control = 0; 306 307 if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3) && 308 KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 4) && 309 KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 5, 0)) 310 update_cu_mask(mm, mqd, minfo, 0); 311 set_priority(m, q); 312 313 if (minfo && KFD_GC_VERSION(mm->dev) >= IP_VERSION(9, 4, 2)) { 314 if (minfo->update_flag & UPDATE_FLAG_IS_GWS) 315 m->compute_resource_limits |= 316 COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK; 317 else 318 m->compute_resource_limits &= 319 ~COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK; 320 } 321 322 q->is_active = QUEUE_IS_ACTIVE(*q); 323 } 324 325 326 static bool check_preemption_failed(struct mqd_manager *mm, void *mqd) 327 { 328 struct v9_mqd *m = (struct v9_mqd *)mqd; 329 uint32_t doorbell_id = m->queue_doorbell_id0; 330 331 m->queue_doorbell_id0 = 0; 332 333 return kfd_check_hiq_mqd_doorbell_id(mm->dev, doorbell_id, 0); 334 } 335 336 static int get_wave_state(struct mqd_manager *mm, void *mqd, 337 struct queue_properties *q, 338 void __user *ctl_stack, 339 u32 *ctl_stack_used_size, 340 u32 *save_area_used_size) 341 { 342 struct v9_mqd *m; 343 struct kfd_context_save_area_header header; 344 345 /* Control stack is located one page after MQD. */ 346 void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 347 348 m = get_mqd(mqd); 349 350 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 351 m->cp_hqd_cntl_stack_offset; 352 *save_area_used_size = m->cp_hqd_wg_state_offset - 353 m->cp_hqd_cntl_stack_size; 354 355 header.wave_state.control_stack_size = *ctl_stack_used_size; 356 header.wave_state.wave_state_size = *save_area_used_size; 357 358 header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset; 359 header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset; 360 361 if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state))) 362 return -EFAULT; 363 364 if (copy_to_user(ctl_stack + m->cp_hqd_cntl_stack_offset, 365 mqd_ctl_stack + m->cp_hqd_cntl_stack_offset, 366 *ctl_stack_used_size)) 367 return -EFAULT; 368 369 return 0; 370 } 371 372 static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) 373 { 374 struct v9_mqd *m = get_mqd(mqd); 375 376 *ctl_stack_size = m->cp_hqd_cntl_stack_size; 377 } 378 379 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 380 { 381 struct v9_mqd *m; 382 /* Control stack is located one page after MQD. */ 383 void *ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); 384 385 m = get_mqd(mqd); 386 387 memcpy(mqd_dst, m, sizeof(struct v9_mqd)); 388 memcpy(ctl_stack_dst, ctl_stack, m->cp_hqd_cntl_stack_size); 389 } 390 391 static void restore_mqd(struct mqd_manager *mm, void **mqd, 392 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 393 struct queue_properties *qp, 394 const void *mqd_src, 395 const void *ctl_stack_src, u32 ctl_stack_size) 396 { 397 uint64_t addr; 398 struct v9_mqd *m; 399 void *ctl_stack; 400 401 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 402 addr = mqd_mem_obj->gpu_addr; 403 404 memcpy(m, mqd_src, sizeof(*m)); 405 406 *mqd = m; 407 if (gart_addr) 408 *gart_addr = addr; 409 410 /* Control stack is located one page after MQD. */ 411 ctl_stack = (void *)((uintptr_t)*mqd + PAGE_SIZE); 412 memcpy(ctl_stack, ctl_stack_src, ctl_stack_size); 413 414 m->cp_hqd_pq_doorbell_control = 415 qp->doorbell_off << 416 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 417 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 418 m->cp_hqd_pq_doorbell_control); 419 420 qp->is_active = 0; 421 } 422 423 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 424 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 425 struct queue_properties *q) 426 { 427 struct v9_mqd *m; 428 429 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 430 431 m = get_mqd(*mqd); 432 433 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 434 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 435 } 436 437 static int destroy_hiq_mqd(struct mqd_manager *mm, void *mqd, 438 enum kfd_preempt_type type, unsigned int timeout, 439 uint32_t pipe_id, uint32_t queue_id) 440 { 441 int err; 442 struct v9_mqd *m; 443 u32 doorbell_off; 444 445 m = get_mqd(mqd); 446 447 doorbell_off = m->cp_hqd_pq_doorbell_control >> 448 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 449 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, 0); 450 if (err) 451 pr_debug("Destroy HIQ MQD failed: %d\n", err); 452 453 return err; 454 } 455 456 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 457 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 458 struct queue_properties *q) 459 { 460 struct v9_sdma_mqd *m; 461 462 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 463 464 memset(m, 0, sizeof(struct v9_sdma_mqd)); 465 466 *mqd = m; 467 if (gart_addr) 468 *gart_addr = mqd_mem_obj->gpu_addr; 469 470 mm->update_mqd(mm, m, q, NULL); 471 } 472 473 #define SDMA_RLC_DUMMY_DEFAULT 0xf 474 475 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 476 struct queue_properties *q, 477 struct mqd_update_info *minfo) 478 { 479 struct v9_sdma_mqd *m; 480 481 m = get_sdma_mqd(mqd); 482 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) 483 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 484 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 485 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 486 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 487 488 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 489 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 490 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 491 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 492 m->sdmax_rlcx_doorbell_offset = 493 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 494 495 m->sdma_engine_id = q->sdma_engine_id; 496 m->sdma_queue_id = q->sdma_queue_id; 497 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 498 499 q->is_active = QUEUE_IS_ACTIVE(*q); 500 } 501 502 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 503 void *mqd, 504 void *mqd_dst, 505 void *ctl_stack_dst) 506 { 507 struct v9_sdma_mqd *m; 508 509 m = get_sdma_mqd(mqd); 510 511 memcpy(mqd_dst, m, sizeof(struct v9_sdma_mqd)); 512 } 513 514 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 515 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 516 struct queue_properties *qp, 517 const void *mqd_src, 518 const void *ctl_stack_src, const u32 ctl_stack_size) 519 { 520 uint64_t addr; 521 struct v9_sdma_mqd *m; 522 523 m = (struct v9_sdma_mqd *) mqd_mem_obj->cpu_ptr; 524 addr = mqd_mem_obj->gpu_addr; 525 526 memcpy(m, mqd_src, sizeof(*m)); 527 528 m->sdmax_rlcx_doorbell_offset = 529 qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 530 531 *mqd = m; 532 if (gart_addr) 533 *gart_addr = addr; 534 535 qp->is_active = 0; 536 } 537 538 static void init_mqd_hiq_v9_4_3(struct mqd_manager *mm, void **mqd, 539 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 540 struct queue_properties *q) 541 { 542 struct v9_mqd *m; 543 int xcc = 0; 544 struct kfd_mem_obj xcc_mqd_mem_obj; 545 uint64_t xcc_gart_addr = 0; 546 547 memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj)); 548 549 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 550 kfd_get_hiq_xcc_mqd(mm->dev, &xcc_mqd_mem_obj, xcc); 551 552 init_mqd(mm, (void **)&m, &xcc_mqd_mem_obj, &xcc_gart_addr, q); 553 554 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 555 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 556 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 557 if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) 558 m->cp_hqd_pq_doorbell_control |= 1 << 559 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; 560 m->cp_mqd_stride_size = kfd_hiq_mqd_stride(mm->dev); 561 if (xcc == 0) { 562 /* Set no_update_rptr = 0 in Master XCC */ 563 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 564 565 /* Set the MQD pointer and gart address to XCC0 MQD */ 566 *mqd = m; 567 *gart_addr = xcc_gart_addr; 568 } 569 } 570 } 571 572 static int hiq_load_mqd_kiq_v9_4_3(struct mqd_manager *mm, void *mqd, 573 uint32_t pipe_id, uint32_t queue_id, 574 struct queue_properties *p, struct mm_struct *mms) 575 { 576 uint32_t xcc_mask = mm->dev->xcc_mask; 577 int xcc_id, err, inst = 0; 578 void *xcc_mqd; 579 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 580 581 for_each_inst(xcc_id, xcc_mask) { 582 xcc_mqd = mqd + hiq_mqd_size * inst; 583 err = mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->adev, xcc_mqd, 584 pipe_id, queue_id, 585 p->doorbell_off, xcc_id); 586 if (err) { 587 pr_debug("Failed to load HIQ MQD for XCC: %d\n", inst); 588 break; 589 } 590 ++inst; 591 } 592 593 return err; 594 } 595 596 static int destroy_hiq_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 597 enum kfd_preempt_type type, unsigned int timeout, 598 uint32_t pipe_id, uint32_t queue_id) 599 { 600 uint32_t xcc_mask = mm->dev->xcc_mask; 601 int xcc_id, err, inst = 0; 602 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 603 struct v9_mqd *m; 604 u32 doorbell_off; 605 606 for_each_inst(xcc_id, xcc_mask) { 607 m = get_mqd(mqd + hiq_mqd_size * inst); 608 609 doorbell_off = m->cp_hqd_pq_doorbell_control >> 610 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 611 612 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, xcc_id); 613 if (err) { 614 pr_debug("Destroy HIQ MQD failed for xcc: %d\n", inst); 615 break; 616 } 617 ++inst; 618 } 619 620 return err; 621 } 622 623 static bool check_preemption_failed_v9_4_3(struct mqd_manager *mm, void *mqd) 624 { 625 uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); 626 uint32_t xcc_mask = mm->dev->xcc_mask; 627 int inst = 0, xcc_id; 628 struct v9_mqd *m; 629 bool ret = false; 630 631 for_each_inst(xcc_id, xcc_mask) { 632 m = get_mqd(mqd + hiq_mqd_size * inst); 633 ret |= kfd_check_hiq_mqd_doorbell_id(mm->dev, 634 m->queue_doorbell_id0, inst); 635 m->queue_doorbell_id0 = 0; 636 ++inst; 637 } 638 639 return ret; 640 } 641 642 static void get_xcc_mqd(struct kfd_mem_obj *mqd_mem_obj, 643 struct kfd_mem_obj *xcc_mqd_mem_obj, 644 uint64_t offset) 645 { 646 xcc_mqd_mem_obj->gtt_mem = (offset == 0) ? 647 mqd_mem_obj->gtt_mem : NULL; 648 xcc_mqd_mem_obj->gpu_addr = mqd_mem_obj->gpu_addr + offset; 649 xcc_mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)mqd_mem_obj->cpu_ptr 650 + offset); 651 } 652 653 static void init_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, 654 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 655 struct queue_properties *q) 656 { 657 struct v9_mqd *m; 658 int xcc = 0; 659 struct kfd_mem_obj xcc_mqd_mem_obj; 660 uint64_t xcc_gart_addr = 0; 661 uint64_t xcc_ctx_save_restore_area_address; 662 uint64_t offset = mm->mqd_stride(mm, q); 663 uint32_t local_xcc_start = mm->dev->dqm->current_logical_xcc_start++; 664 665 memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj)); 666 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 667 get_xcc_mqd(mqd_mem_obj, &xcc_mqd_mem_obj, offset*xcc); 668 669 init_mqd(mm, (void **)&m, &xcc_mqd_mem_obj, &xcc_gart_addr, q); 670 if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) 671 m->cp_hqd_pq_doorbell_control |= 1 << 672 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; 673 m->cp_mqd_stride_size = offset; 674 675 /* 676 * Update the CWSR address for each XCC if CWSR is enabled 677 * and CWSR area is allocated in thunk 678 */ 679 if (mm->dev->kfd->cwsr_enabled && 680 q->ctx_save_restore_area_address) { 681 xcc_ctx_save_restore_area_address = 682 q->ctx_save_restore_area_address + 683 (xcc * q->ctx_save_restore_area_size); 684 685 m->cp_hqd_ctx_save_base_addr_lo = 686 lower_32_bits(xcc_ctx_save_restore_area_address); 687 m->cp_hqd_ctx_save_base_addr_hi = 688 upper_32_bits(xcc_ctx_save_restore_area_address); 689 } 690 691 if (q->format == KFD_QUEUE_FORMAT_AQL) { 692 m->compute_tg_chunk_size = 1; 693 m->compute_current_logic_xcc_id = 694 (local_xcc_start + xcc) % 695 NUM_XCC(mm->dev->xcc_mask); 696 697 switch (xcc) { 698 case 0: 699 /* Master XCC */ 700 m->cp_hqd_pq_control &= 701 ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 702 break; 703 default: 704 break; 705 } 706 } else { 707 /* PM4 Queue */ 708 m->compute_current_logic_xcc_id = 0; 709 m->compute_tg_chunk_size = 0; 710 m->pm4_target_xcc_in_xcp = q->pm4_target_xcc; 711 } 712 713 if (xcc == 0) { 714 /* Set the MQD pointer and gart address to XCC0 MQD */ 715 *mqd = m; 716 *gart_addr = xcc_gart_addr; 717 } 718 } 719 } 720 721 static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 722 struct queue_properties *q, struct mqd_update_info *minfo) 723 { 724 struct v9_mqd *m; 725 int xcc = 0; 726 uint64_t size = mm->mqd_stride(mm, q); 727 728 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 729 m = get_mqd(mqd + size * xcc); 730 update_mqd(mm, m, q, minfo); 731 732 if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) 733 m->cp_hqd_pq_doorbell_control |= 1 << 734 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; 735 update_cu_mask(mm, m, minfo, xcc); 736 737 if (q->format == KFD_QUEUE_FORMAT_AQL) { 738 switch (xcc) { 739 case 0: 740 /* Master XCC */ 741 m->cp_hqd_pq_control &= 742 ~CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK; 743 break; 744 default: 745 break; 746 } 747 m->compute_tg_chunk_size = 1; 748 } else { 749 /* PM4 Queue */ 750 m->compute_current_logic_xcc_id = 0; 751 m->compute_tg_chunk_size = 0; 752 m->pm4_target_xcc_in_xcp = q->pm4_target_xcc; 753 } 754 } 755 } 756 757 static void restore_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, 758 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 759 struct queue_properties *qp, 760 const void *mqd_src, 761 const void *ctl_stack_src, u32 ctl_stack_size) 762 { 763 restore_mqd(mm, mqd, mqd_mem_obj, gart_addr, qp, mqd_src, ctl_stack_src, ctl_stack_size); 764 if (amdgpu_sriov_multi_vf_mode(mm->dev->adev)) { 765 struct v9_mqd *m; 766 767 m = (struct v9_mqd *) mqd_mem_obj->cpu_ptr; 768 m->cp_hqd_pq_doorbell_control |= 1 << 769 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT; 770 } 771 } 772 static int destroy_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 773 enum kfd_preempt_type type, unsigned int timeout, 774 uint32_t pipe_id, uint32_t queue_id) 775 { 776 uint32_t xcc_mask = mm->dev->xcc_mask; 777 int xcc_id, err, inst = 0; 778 void *xcc_mqd; 779 struct v9_mqd *m; 780 uint64_t mqd_offset; 781 782 m = get_mqd(mqd); 783 mqd_offset = m->cp_mqd_stride_size; 784 785 for_each_inst(xcc_id, xcc_mask) { 786 xcc_mqd = mqd + mqd_offset * inst; 787 err = mm->dev->kfd2kgd->hqd_destroy(mm->dev->adev, xcc_mqd, 788 type, timeout, pipe_id, 789 queue_id, xcc_id); 790 if (err) { 791 pr_debug("Destroy MQD failed for xcc: %d\n", inst); 792 break; 793 } 794 ++inst; 795 } 796 797 return err; 798 } 799 800 static int load_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, 801 uint32_t pipe_id, uint32_t queue_id, 802 struct queue_properties *p, struct mm_struct *mms) 803 { 804 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 805 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 806 uint32_t xcc_mask = mm->dev->xcc_mask; 807 int xcc_id, err, inst = 0; 808 void *xcc_mqd; 809 uint64_t mqd_stride_size = mm->mqd_stride(mm, p); 810 811 for_each_inst(xcc_id, xcc_mask) { 812 xcc_mqd = mqd + mqd_stride_size * inst; 813 err = mm->dev->kfd2kgd->hqd_load( 814 mm->dev->adev, xcc_mqd, pipe_id, queue_id, 815 (uint32_t __user *)p->write_ptr, wptr_shift, 0, mms, 816 xcc_id); 817 if (err) { 818 pr_debug("Load MQD failed for xcc: %d\n", inst); 819 break; 820 } 821 ++inst; 822 } 823 824 return err; 825 } 826 827 static int get_wave_state_v9_4_3(struct mqd_manager *mm, void *mqd, 828 struct queue_properties *q, 829 void __user *ctl_stack, 830 u32 *ctl_stack_used_size, 831 u32 *save_area_used_size) 832 { 833 int xcc, err = 0; 834 void *xcc_mqd; 835 void __user *xcc_ctl_stack; 836 uint64_t mqd_stride_size = mm->mqd_stride(mm, q); 837 u32 tmp_ctl_stack_used_size = 0, tmp_save_area_used_size = 0; 838 839 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { 840 xcc_mqd = mqd + mqd_stride_size * xcc; 841 xcc_ctl_stack = (void __user *)((uintptr_t)ctl_stack + 842 q->ctx_save_restore_area_size * xcc); 843 844 err = get_wave_state(mm, xcc_mqd, q, xcc_ctl_stack, 845 &tmp_ctl_stack_used_size, 846 &tmp_save_area_used_size); 847 if (err) 848 break; 849 850 /* 851 * Set the ctl_stack_used_size and save_area_used_size to 852 * ctl_stack_used_size and save_area_used_size of XCC 0 when 853 * passing the info the user-space. 854 * For multi XCC, user-space would have to look at the header 855 * info of each Control stack area to determine the control 856 * stack size and save area used. 857 */ 858 if (xcc == 0) { 859 *ctl_stack_used_size = tmp_ctl_stack_used_size; 860 *save_area_used_size = tmp_save_area_used_size; 861 } 862 } 863 864 return err; 865 } 866 867 #if defined(CONFIG_DEBUG_FS) 868 869 static int debugfs_show_mqd(struct seq_file *m, void *data) 870 { 871 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 872 data, sizeof(struct v9_mqd), false); 873 return 0; 874 } 875 876 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 877 { 878 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 879 data, sizeof(struct v9_sdma_mqd), false); 880 return 0; 881 } 882 883 #endif 884 885 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, 886 struct kfd_node *dev) 887 { 888 struct mqd_manager *mqd; 889 890 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 891 return NULL; 892 893 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 894 if (!mqd) 895 return NULL; 896 897 mqd->dev = dev; 898 899 switch (type) { 900 case KFD_MQD_TYPE_CP: 901 mqd->allocate_mqd = allocate_mqd; 902 mqd->free_mqd = kfd_free_mqd_cp; 903 mqd->is_occupied = kfd_is_occupied_cp; 904 mqd->get_checkpoint_info = get_checkpoint_info; 905 mqd->checkpoint_mqd = checkpoint_mqd; 906 mqd->mqd_size = sizeof(struct v9_mqd); 907 mqd->mqd_stride = mqd_stride_v9; 908 #if defined(CONFIG_DEBUG_FS) 909 mqd->debugfs_show_mqd = debugfs_show_mqd; 910 #endif 911 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 912 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) || 913 KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) { 914 mqd->init_mqd = init_mqd_v9_4_3; 915 mqd->load_mqd = load_mqd_v9_4_3; 916 mqd->update_mqd = update_mqd_v9_4_3; 917 mqd->restore_mqd = restore_mqd_v9_4_3; 918 mqd->destroy_mqd = destroy_mqd_v9_4_3; 919 mqd->get_wave_state = get_wave_state_v9_4_3; 920 } else { 921 mqd->init_mqd = init_mqd; 922 mqd->load_mqd = load_mqd; 923 mqd->update_mqd = update_mqd; 924 mqd->restore_mqd = restore_mqd; 925 mqd->destroy_mqd = kfd_destroy_mqd_cp; 926 mqd->get_wave_state = get_wave_state; 927 } 928 break; 929 case KFD_MQD_TYPE_HIQ: 930 mqd->allocate_mqd = allocate_hiq_mqd; 931 mqd->free_mqd = free_mqd_hiq_sdma; 932 mqd->update_mqd = update_mqd; 933 mqd->is_occupied = kfd_is_occupied_cp; 934 mqd->mqd_size = sizeof(struct v9_mqd); 935 mqd->mqd_stride = kfd_mqd_stride; 936 #if defined(CONFIG_DEBUG_FS) 937 mqd->debugfs_show_mqd = debugfs_show_mqd; 938 #endif 939 mqd->check_preemption_failed = check_preemption_failed; 940 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || 941 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4) || 942 KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) { 943 mqd->init_mqd = init_mqd_hiq_v9_4_3; 944 mqd->load_mqd = hiq_load_mqd_kiq_v9_4_3; 945 mqd->destroy_mqd = destroy_hiq_mqd_v9_4_3; 946 mqd->check_preemption_failed = check_preemption_failed_v9_4_3; 947 } else { 948 mqd->init_mqd = init_mqd_hiq; 949 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 950 mqd->destroy_mqd = destroy_hiq_mqd; 951 mqd->check_preemption_failed = check_preemption_failed; 952 } 953 break; 954 case KFD_MQD_TYPE_DIQ: 955 mqd->allocate_mqd = allocate_mqd; 956 mqd->init_mqd = init_mqd_hiq; 957 mqd->free_mqd = kfd_free_mqd_cp; 958 mqd->load_mqd = load_mqd; 959 mqd->update_mqd = update_mqd; 960 mqd->destroy_mqd = kfd_destroy_mqd_cp; 961 mqd->is_occupied = kfd_is_occupied_cp; 962 mqd->mqd_size = sizeof(struct v9_mqd); 963 #if defined(CONFIG_DEBUG_FS) 964 mqd->debugfs_show_mqd = debugfs_show_mqd; 965 #endif 966 break; 967 case KFD_MQD_TYPE_SDMA: 968 mqd->allocate_mqd = allocate_sdma_mqd; 969 mqd->init_mqd = init_mqd_sdma; 970 mqd->free_mqd = free_mqd_hiq_sdma; 971 mqd->load_mqd = kfd_load_mqd_sdma; 972 mqd->update_mqd = update_mqd_sdma; 973 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 974 mqd->is_occupied = kfd_is_occupied_sdma; 975 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 976 mqd->restore_mqd = restore_mqd_sdma; 977 mqd->mqd_size = sizeof(struct v9_sdma_mqd); 978 mqd->mqd_stride = kfd_mqd_stride; 979 #if defined(CONFIG_DEBUG_FS) 980 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 981 #endif 982 break; 983 default: 984 kfree(mqd); 985 return NULL; 986 } 987 988 return mqd; 989 } 990