1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2018-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/printk.h> 26 #include <linux/slab.h> 27 #include <linux/uaccess.h> 28 #include "kfd_priv.h" 29 #include "kfd_mqd_manager.h" 30 #include "v10_structs.h" 31 #include "gc/gc_10_1_0_offset.h" 32 #include "gc/gc_10_1_0_sh_mask.h" 33 #include "amdgpu_amdkfd.h" 34 35 static inline struct v10_compute_mqd *get_mqd(void *mqd) 36 { 37 return (struct v10_compute_mqd *)mqd; 38 } 39 40 static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd) 41 { 42 return (struct v10_sdma_mqd *)mqd; 43 } 44 45 static void update_cu_mask(struct mqd_manager *mm, void *mqd, 46 struct mqd_update_info *minfo) 47 { 48 struct v10_compute_mqd *m; 49 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ 50 51 if (!minfo || !minfo->cu_mask.ptr) 52 return; 53 54 mqd_symmetrically_map_cu_mask(mm, 55 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); 56 57 m = get_mqd(mqd); 58 m->compute_static_thread_mgmt_se0 = se_mask[0]; 59 m->compute_static_thread_mgmt_se1 = se_mask[1]; 60 m->compute_static_thread_mgmt_se2 = se_mask[2]; 61 m->compute_static_thread_mgmt_se3 = se_mask[3]; 62 63 pr_debug("update cu mask to %#x %#x %#x %#x\n", 64 m->compute_static_thread_mgmt_se0, 65 m->compute_static_thread_mgmt_se1, 66 m->compute_static_thread_mgmt_se2, 67 m->compute_static_thread_mgmt_se3); 68 } 69 70 static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q) 71 { 72 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; 73 m->cp_hqd_queue_priority = q->priority; 74 } 75 76 static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd, 77 struct queue_properties *q) 78 { 79 struct kfd_mem_obj *mqd_mem_obj; 80 81 if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd), 82 &mqd_mem_obj)) 83 return NULL; 84 85 return mqd_mem_obj; 86 } 87 88 static void init_mqd(struct mqd_manager *mm, void **mqd, 89 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 90 struct queue_properties *q) 91 { 92 uint64_t addr; 93 struct v10_compute_mqd *m; 94 95 m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr; 96 addr = mqd_mem_obj->gpu_addr; 97 98 memset(m, 0, sizeof(struct v10_compute_mqd)); 99 100 m->header = 0xC0310800; 101 m->compute_pipelinestat_enable = 1; 102 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; 103 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; 104 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; 105 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; 106 107 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | 108 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; 109 110 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; 111 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; 112 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; 113 114 m->cp_mqd_base_addr_lo = lower_32_bits(addr); 115 m->cp_mqd_base_addr_hi = upper_32_bits(addr); 116 117 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | 118 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | 119 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; 120 121 /* Set cp_hqd_hq_scheduler0 bit 14 to 1 to have the CP set up the 122 * DISPATCH_PTR. This is required for the kfd debugger 123 */ 124 m->cp_hqd_hq_scheduler0 = 1 << 14; 125 126 if (q->format == KFD_QUEUE_FORMAT_AQL) { 127 m->cp_hqd_aql_control = 128 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; 129 } 130 131 if (mm->dev->kfd->cwsr_enabled) { 132 m->cp_hqd_persistent_state |= 133 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); 134 m->cp_hqd_ctx_save_base_addr_lo = 135 lower_32_bits(q->ctx_save_restore_area_address); 136 m->cp_hqd_ctx_save_base_addr_hi = 137 upper_32_bits(q->ctx_save_restore_area_address); 138 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; 139 m->cp_hqd_cntl_stack_size = q->ctl_stack_size; 140 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; 141 m->cp_hqd_wg_state_offset = q->ctl_stack_size; 142 } 143 144 *mqd = m; 145 if (gart_addr) 146 *gart_addr = addr; 147 mm->update_mqd(mm, m, q, NULL); 148 } 149 150 static int load_mqd(struct mqd_manager *mm, void *mqd, 151 uint32_t pipe_id, uint32_t queue_id, 152 struct queue_properties *p, struct mm_struct *mms) 153 { 154 int r = 0; 155 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ 156 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); 157 158 r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, 159 (uint32_t __user *)p->write_ptr, 160 wptr_shift, 0, mms, 0); 161 return r; 162 } 163 164 static void update_mqd(struct mqd_manager *mm, void *mqd, 165 struct queue_properties *q, 166 struct mqd_update_info *minfo) 167 { 168 struct v10_compute_mqd *m; 169 170 m = get_mqd(mqd); 171 172 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; 173 m->cp_hqd_pq_control |= 174 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; 175 176 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); 177 178 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); 179 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); 180 181 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 182 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 183 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); 184 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); 185 186 m->cp_hqd_pq_doorbell_control = 187 q->doorbell_off << 188 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 189 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 190 m->cp_hqd_pq_doorbell_control); 191 192 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; 193 194 /* 195 * HW does not clamp this field correctly. Maximum EOP queue size 196 * is constrained by per-SE EOP done signal count, which is 8-bit. 197 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit 198 * more than (EOP entry count - 1) so a queue size of 0x800 dwords 199 * is safe, giving a maximum field value of 0xA. 200 */ 201 m->cp_hqd_eop_control = min(0xA, 202 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); 203 m->cp_hqd_eop_base_addr_lo = 204 lower_32_bits(q->eop_ring_buffer_address >> 8); 205 m->cp_hqd_eop_base_addr_hi = 206 upper_32_bits(q->eop_ring_buffer_address >> 8); 207 208 m->cp_hqd_iq_timer = 0; 209 210 m->cp_hqd_vmid = q->vmid; 211 212 if (q->format == KFD_QUEUE_FORMAT_AQL) { 213 /* GC 10 removed WPP_CLAMP from PQ Control */ 214 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 215 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | 216 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT; 217 m->cp_hqd_pq_doorbell_control |= 218 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; 219 } 220 if (mm->dev->kfd->cwsr_enabled) 221 m->cp_hqd_ctx_save_control = 0; 222 223 update_cu_mask(mm, mqd, minfo); 224 set_priority(m, q); 225 226 q->is_active = QUEUE_IS_ACTIVE(*q); 227 } 228 229 static bool check_preemption_failed(struct mqd_manager *mm, void *mqd) 230 { 231 struct v10_compute_mqd *m = (struct v10_compute_mqd *)mqd; 232 233 return kfd_check_hiq_mqd_doorbell_id(mm->dev, m->queue_doorbell_id0, 0); 234 } 235 236 static int get_wave_state(struct mqd_manager *mm, void *mqd, 237 struct queue_properties *q, 238 void __user *ctl_stack, 239 u32 *ctl_stack_used_size, 240 u32 *save_area_used_size) 241 { 242 struct v10_compute_mqd *m; 243 struct kfd_context_save_area_header header; 244 245 m = get_mqd(mqd); 246 247 /* Control stack is written backwards, while workgroup context data 248 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. 249 * Current position is at m->cp_hqd_cntl_stack_offset and 250 * m->cp_hqd_wg_state_offset, respectively. 251 */ 252 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - 253 m->cp_hqd_cntl_stack_offset; 254 *save_area_used_size = m->cp_hqd_wg_state_offset - 255 m->cp_hqd_cntl_stack_size; 256 257 /* Control stack is not copied to user mode for GFXv10 because 258 * it's part of the context save area that is already 259 * accessible to user mode 260 */ 261 262 header.wave_state.control_stack_size = *ctl_stack_used_size; 263 header.wave_state.wave_state_size = *save_area_used_size; 264 265 header.wave_state.wave_state_offset = m->cp_hqd_wg_state_offset; 266 header.wave_state.control_stack_offset = m->cp_hqd_cntl_stack_offset; 267 268 if (copy_to_user(ctl_stack, &header, sizeof(header.wave_state))) 269 return -EFAULT; 270 271 return 0; 272 } 273 274 static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) 275 { 276 struct v10_compute_mqd *m; 277 278 m = get_mqd(mqd); 279 280 memcpy(mqd_dst, m, sizeof(struct v10_compute_mqd)); 281 } 282 283 static void restore_mqd(struct mqd_manager *mm, void **mqd, 284 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 285 struct queue_properties *qp, 286 const void *mqd_src, 287 const void *ctl_stack_src, const u32 ctl_stack_size) 288 { 289 uint64_t addr; 290 struct v10_compute_mqd *m; 291 292 m = (struct v10_compute_mqd *) mqd_mem_obj->cpu_ptr; 293 addr = mqd_mem_obj->gpu_addr; 294 295 memcpy(m, mqd_src, sizeof(*m)); 296 297 *mqd = m; 298 if (gart_addr) 299 *gart_addr = addr; 300 301 m->cp_hqd_pq_doorbell_control = 302 qp->doorbell_off << 303 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 304 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", 305 m->cp_hqd_pq_doorbell_control); 306 307 qp->is_active = 0; 308 } 309 310 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, 311 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 312 struct queue_properties *q) 313 { 314 struct v10_compute_mqd *m; 315 316 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); 317 318 m = get_mqd(*mqd); 319 320 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | 321 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; 322 } 323 324 static int destroy_hiq_mqd(struct mqd_manager *mm, void *mqd, 325 enum kfd_preempt_type type, unsigned int timeout, 326 uint32_t pipe_id, uint32_t queue_id) 327 { 328 int err; 329 struct v10_compute_mqd *m; 330 u32 doorbell_off; 331 332 m = get_mqd(mqd); 333 334 doorbell_off = m->cp_hqd_pq_doorbell_control >> 335 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 336 337 err = amdgpu_amdkfd_unmap_hiq(mm->dev->adev, doorbell_off, 0); 338 if (err) 339 pr_debug("Destroy HIQ MQD failed: %d\n", err); 340 341 return err; 342 } 343 344 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, 345 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 346 struct queue_properties *q) 347 { 348 struct v10_sdma_mqd *m; 349 350 m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr; 351 352 memset(m, 0, sizeof(struct v10_sdma_mqd)); 353 354 *mqd = m; 355 if (gart_addr) 356 *gart_addr = mqd_mem_obj->gpu_addr; 357 358 mm->update_mqd(mm, m, q, NULL); 359 } 360 361 #define SDMA_RLC_DUMMY_DEFAULT 0xf 362 363 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, 364 struct queue_properties *q, 365 struct mqd_update_info *minfo) 366 { 367 struct v10_sdma_mqd *m; 368 369 m = get_sdma_mqd(mqd); 370 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) 371 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 372 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | 373 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 374 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 375 376 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); 377 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); 378 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); 379 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); 380 m->sdmax_rlcx_doorbell_offset = 381 q->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 382 383 m->sdma_engine_id = q->sdma_engine_id; 384 m->sdma_queue_id = q->sdma_queue_id; 385 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; 386 387 q->is_active = QUEUE_IS_ACTIVE(*q); 388 } 389 390 static void checkpoint_mqd_sdma(struct mqd_manager *mm, 391 void *mqd, 392 void *mqd_dst, 393 void *ctl_stack_dst) 394 { 395 struct v10_sdma_mqd *m; 396 397 m = get_sdma_mqd(mqd); 398 399 memcpy(mqd_dst, m, sizeof(struct v10_sdma_mqd)); 400 } 401 402 static void restore_mqd_sdma(struct mqd_manager *mm, void **mqd, 403 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, 404 struct queue_properties *qp, 405 const void *mqd_src, 406 const void *ctl_stack_src, 407 const u32 ctl_stack_size) 408 { 409 uint64_t addr; 410 struct v10_sdma_mqd *m; 411 412 m = (struct v10_sdma_mqd *) mqd_mem_obj->cpu_ptr; 413 addr = mqd_mem_obj->gpu_addr; 414 415 memcpy(m, mqd_src, sizeof(*m)); 416 417 m->sdmax_rlcx_doorbell_offset = 418 qp->doorbell_off << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 419 420 *mqd = m; 421 if (gart_addr) 422 *gart_addr = addr; 423 424 qp->is_active = 0; 425 } 426 427 #if defined(CONFIG_DEBUG_FS) 428 429 static int debugfs_show_mqd(struct seq_file *m, void *data) 430 { 431 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 432 data, sizeof(struct v10_compute_mqd), false); 433 return 0; 434 } 435 436 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) 437 { 438 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, 439 data, sizeof(struct v10_sdma_mqd), false); 440 return 0; 441 } 442 443 #endif 444 445 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, 446 struct kfd_node *dev) 447 { 448 struct mqd_manager *mqd; 449 450 if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) 451 return NULL; 452 453 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); 454 if (!mqd) 455 return NULL; 456 457 mqd->dev = dev; 458 459 switch (type) { 460 case KFD_MQD_TYPE_CP: 461 pr_debug("%s@%i\n", __func__, __LINE__); 462 mqd->allocate_mqd = allocate_mqd; 463 mqd->init_mqd = init_mqd; 464 mqd->free_mqd = kfd_free_mqd_cp; 465 mqd->load_mqd = load_mqd; 466 mqd->update_mqd = update_mqd; 467 mqd->destroy_mqd = kfd_destroy_mqd_cp; 468 mqd->is_occupied = kfd_is_occupied_cp; 469 mqd->mqd_size = sizeof(struct v10_compute_mqd); 470 mqd->get_wave_state = get_wave_state; 471 mqd->checkpoint_mqd = checkpoint_mqd; 472 mqd->restore_mqd = restore_mqd; 473 mqd->mqd_stride = kfd_mqd_stride; 474 #if defined(CONFIG_DEBUG_FS) 475 mqd->debugfs_show_mqd = debugfs_show_mqd; 476 #endif 477 pr_debug("%s@%i\n", __func__, __LINE__); 478 break; 479 case KFD_MQD_TYPE_HIQ: 480 pr_debug("%s@%i\n", __func__, __LINE__); 481 mqd->allocate_mqd = allocate_hiq_mqd; 482 mqd->init_mqd = init_mqd_hiq; 483 mqd->free_mqd = free_mqd_hiq_sdma; 484 mqd->load_mqd = kfd_hiq_load_mqd_kiq; 485 mqd->update_mqd = update_mqd; 486 mqd->destroy_mqd = destroy_hiq_mqd; 487 mqd->is_occupied = kfd_is_occupied_cp; 488 mqd->mqd_size = sizeof(struct v10_compute_mqd); 489 mqd->mqd_stride = kfd_mqd_stride; 490 #if defined(CONFIG_DEBUG_FS) 491 mqd->debugfs_show_mqd = debugfs_show_mqd; 492 #endif 493 mqd->check_preemption_failed = check_preemption_failed; 494 pr_debug("%s@%i\n", __func__, __LINE__); 495 break; 496 case KFD_MQD_TYPE_DIQ: 497 mqd->allocate_mqd = allocate_mqd; 498 mqd->init_mqd = init_mqd_hiq; 499 mqd->free_mqd = kfd_free_mqd_cp; 500 mqd->load_mqd = load_mqd; 501 mqd->update_mqd = update_mqd; 502 mqd->destroy_mqd = kfd_destroy_mqd_cp; 503 mqd->is_occupied = kfd_is_occupied_cp; 504 mqd->mqd_size = sizeof(struct v10_compute_mqd); 505 #if defined(CONFIG_DEBUG_FS) 506 mqd->debugfs_show_mqd = debugfs_show_mqd; 507 #endif 508 break; 509 case KFD_MQD_TYPE_SDMA: 510 pr_debug("%s@%i\n", __func__, __LINE__); 511 mqd->allocate_mqd = allocate_sdma_mqd; 512 mqd->init_mqd = init_mqd_sdma; 513 mqd->free_mqd = free_mqd_hiq_sdma; 514 mqd->load_mqd = kfd_load_mqd_sdma; 515 mqd->update_mqd = update_mqd_sdma; 516 mqd->destroy_mqd = kfd_destroy_mqd_sdma; 517 mqd->is_occupied = kfd_is_occupied_sdma; 518 mqd->checkpoint_mqd = checkpoint_mqd_sdma; 519 mqd->restore_mqd = restore_mqd_sdma; 520 mqd->mqd_size = sizeof(struct v10_sdma_mqd); 521 mqd->mqd_stride = kfd_mqd_stride; 522 #if defined(CONFIG_DEBUG_FS) 523 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; 524 #endif 525 pr_debug("%s@%i\n", __func__, __LINE__); 526 break; 527 default: 528 kfree(mqd); 529 return NULL; 530 } 531 532 return mqd; 533 } 534