1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include "kfd_device_queue_manager.h" 26 #include "gca/gfx_8_0_enum.h" 27 #include "gca/gfx_8_0_sh_mask.h" 28 #include "oss/oss_3_0_sh_mask.h" 29 30 /* 31 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to 32 * stay in user mode. 33 */ 34 #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL 35 /* APE1 limit is inclusive and 64K aligned. */ 36 #define APE1_LIMIT_ALIGNMENT 0xFFFF 37 38 static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm, 39 struct qcm_process_device *qpd, 40 enum cache_policy default_policy, 41 enum cache_policy alternate_policy, 42 void __user *alternate_aperture_base, 43 uint64_t alternate_aperture_size, 44 u32 misc_process_properties); 45 static int update_qpd_vi(struct device_queue_manager *dqm, 46 struct qcm_process_device *qpd); 47 static void init_sdma_vm(struct device_queue_manager *dqm, 48 struct queue *q, 49 struct qcm_process_device *qpd); 50 51 void device_queue_manager_init_vi( 52 struct device_queue_manager_asic_ops *asic_ops) 53 { 54 asic_ops->set_cache_memory_policy = set_cache_memory_policy_vi; 55 asic_ops->update_qpd = update_qpd_vi; 56 asic_ops->init_sdma_vm = init_sdma_vm; 57 asic_ops->mqd_manager_init = mqd_manager_init_vi; 58 } 59 60 static uint32_t compute_sh_mem_bases_64bit(unsigned int top_address_nybble) 61 { 62 /* In 64-bit mode, we can only control the top 3 bits of the LDS, 63 * scratch and GPUVM apertures. 64 * The hardware fills in the remaining 59 bits according to the 65 * following pattern: 66 * LDS: X0000000'00000000 - X0000001'00000000 (4GB) 67 * Scratch: X0000001'00000000 - X0000002'00000000 (4GB) 68 * GPUVM: Y0010000'00000000 - Y0020000'00000000 (1TB) 69 * 70 * (where X/Y is the configurable nybble with the low-bit 0) 71 * 72 * LDS and scratch will have the same top nybble programmed in the 73 * top 3 bits of SH_MEM_BASES.PRIVATE_BASE. 74 * GPUVM can have a different top nybble programmed in the 75 * top 3 bits of SH_MEM_BASES.SHARED_BASE. 76 * We don't bother to support different top nybbles 77 * for LDS/Scratch and GPUVM. 78 */ 79 80 WARN_ON((top_address_nybble & 1) || top_address_nybble > 0xE || 81 top_address_nybble == 0); 82 83 return top_address_nybble << 12 | 84 (top_address_nybble << 12) << 85 SH_MEM_BASES__SHARED_BASE__SHIFT; 86 } 87 88 static bool set_cache_memory_policy_vi(struct device_queue_manager *dqm, 89 struct qcm_process_device *qpd, 90 enum cache_policy default_policy, 91 enum cache_policy alternate_policy, 92 void __user *alternate_aperture_base, 93 uint64_t alternate_aperture_size, 94 u32 misc_process_properties) 95 { 96 uint32_t default_mtype; 97 uint32_t ape1_mtype; 98 unsigned int temp; 99 bool retval = true; 100 101 if (alternate_aperture_size == 0) { 102 /* base > limit disables APE1 */ 103 qpd->sh_mem_ape1_base = 1; 104 qpd->sh_mem_ape1_limit = 0; 105 } else { 106 /* 107 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]}, 108 * SH_MEM_APE1_BASE[31:0], 0x0000 } 109 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]}, 110 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF } 111 * Verify that the base and size parameters can be 112 * represented in this format and convert them. 113 * Additionally restrict APE1 to user-mode addresses. 114 */ 115 116 uint64_t base = (uintptr_t)alternate_aperture_base; 117 uint64_t limit = base + alternate_aperture_size - 1; 118 119 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 || 120 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) { 121 retval = false; 122 goto out; 123 } 124 125 qpd->sh_mem_ape1_base = base >> 16; 126 qpd->sh_mem_ape1_limit = limit >> 16; 127 } 128 129 default_mtype = (default_policy == cache_policy_coherent) ? 130 MTYPE_UC : 131 MTYPE_NC; 132 133 ape1_mtype = (alternate_policy == cache_policy_coherent) ? 134 MTYPE_UC : 135 MTYPE_NC; 136 137 qpd->sh_mem_config = 138 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 139 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT | 140 default_mtype << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT | 141 ape1_mtype << SH_MEM_CONFIG__APE1_MTYPE__SHIFT; 142 143 /* On dGPU we're always in GPUVM64 addressing mode with 64-bit 144 * aperture addresses. 145 */ 146 temp = get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd)); 147 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); 148 149 pr_debug("sh_mem_bases nybble: 0x%X and register 0x%X\n", 150 temp, qpd->sh_mem_bases); 151 out: 152 return retval; 153 } 154 155 static int update_qpd_vi(struct device_queue_manager *dqm, 156 struct qcm_process_device *qpd) 157 { 158 return 0; 159 } 160 161 static void init_sdma_vm(struct device_queue_manager *dqm, 162 struct queue *q, 163 struct qcm_process_device *qpd) 164 { 165 /* On dGPU we're always in GPUVM64 addressing mode with 64-bit 166 * aperture addresses. 167 */ 168 q->properties.sdma_vm_addr = 169 ((get_sh_mem_bases_nybble_64(qpd_to_pdd(qpd))) << 170 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE__SHIFT) & 171 SDMA0_RLC0_VIRTUAL_ADDR__SHARED_BASE_MASK; 172 } 173