1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/device.h> 25 #include <linux/export.h> 26 #include <linux/err.h> 27 #include <linux/fs.h> 28 #include <linux/file.h> 29 #include <linux/sched.h> 30 #include <linux/slab.h> 31 #include <linux/uaccess.h> 32 #include <linux/compat.h> 33 #include <uapi/linux/kfd_ioctl.h> 34 #include <linux/time.h> 35 #include <linux/mm.h> 36 #include <linux/mman.h> 37 #include <linux/ptrace.h> 38 #include <linux/dma-buf.h> 39 #include <linux/processor.h> 40 #include "kfd_priv.h" 41 #include "kfd_device_queue_manager.h" 42 #include "kfd_svm.h" 43 #include "amdgpu_amdkfd.h" 44 #include "kfd_smi_events.h" 45 #include "amdgpu_dma_buf.h" 46 #include "kfd_debug.h" 47 48 static long kfd_ioctl(struct file *, unsigned int, unsigned long); 49 static int kfd_open(struct inode *, struct file *); 50 static int kfd_release(struct inode *, struct file *); 51 static int kfd_mmap(struct file *, struct vm_area_struct *); 52 53 static const char kfd_dev_name[] = "kfd"; 54 55 static const struct file_operations kfd_fops = { 56 .owner = THIS_MODULE, 57 .unlocked_ioctl = kfd_ioctl, 58 .compat_ioctl = compat_ptr_ioctl, 59 .open = kfd_open, 60 .release = kfd_release, 61 .mmap = kfd_mmap, 62 }; 63 64 static int kfd_char_dev_major = -1; 65 struct device *kfd_device; 66 static const struct class kfd_class = { 67 .name = kfd_dev_name, 68 }; 69 70 static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id) 71 { 72 struct kfd_process_device *pdd; 73 74 mutex_lock(&p->mutex); 75 pdd = kfd_process_device_data_by_id(p, gpu_id); 76 77 if (pdd) 78 return pdd; 79 80 mutex_unlock(&p->mutex); 81 return NULL; 82 } 83 84 static inline void kfd_unlock_pdd(struct kfd_process_device *pdd) 85 { 86 mutex_unlock(&pdd->process->mutex); 87 } 88 89 int kfd_chardev_init(void) 90 { 91 int err = 0; 92 93 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops); 94 err = kfd_char_dev_major; 95 if (err < 0) 96 goto err_register_chrdev; 97 98 err = class_register(&kfd_class); 99 if (err) 100 goto err_class_create; 101 102 kfd_device = device_create(&kfd_class, NULL, 103 MKDEV(kfd_char_dev_major, 0), 104 NULL, kfd_dev_name); 105 err = PTR_ERR(kfd_device); 106 if (IS_ERR(kfd_device)) 107 goto err_device_create; 108 109 return 0; 110 111 err_device_create: 112 class_unregister(&kfd_class); 113 err_class_create: 114 unregister_chrdev(kfd_char_dev_major, kfd_dev_name); 115 err_register_chrdev: 116 return err; 117 } 118 119 void kfd_chardev_exit(void) 120 { 121 device_destroy(&kfd_class, MKDEV(kfd_char_dev_major, 0)); 122 class_unregister(&kfd_class); 123 unregister_chrdev(kfd_char_dev_major, kfd_dev_name); 124 kfd_device = NULL; 125 } 126 127 128 static int kfd_open(struct inode *inode, struct file *filep) 129 { 130 struct kfd_process *process; 131 bool is_32bit_user_mode; 132 133 if (iminor(inode) != 0) 134 return -ENODEV; 135 136 is_32bit_user_mode = in_compat_syscall(); 137 138 if (is_32bit_user_mode) { 139 dev_warn(kfd_device, 140 "Process %d (32-bit) failed to open /dev/kfd\n" 141 "32-bit processes are not supported by amdkfd\n", 142 current->pid); 143 return -EPERM; 144 } 145 146 process = kfd_create_process(current); 147 if (IS_ERR(process)) 148 return PTR_ERR(process); 149 150 if (kfd_process_init_cwsr_apu(process, filep)) { 151 kfd_unref_process(process); 152 return -EFAULT; 153 } 154 155 /* filep now owns the reference returned by kfd_create_process */ 156 filep->private_data = process; 157 158 dev_dbg(kfd_device, "process pid %d opened kfd node, compat mode (32 bit) - %d\n", 159 process->lead_thread->pid, process->is_32bit_user_mode); 160 161 return 0; 162 } 163 164 static int kfd_release(struct inode *inode, struct file *filep) 165 { 166 struct kfd_process *process = filep->private_data; 167 168 if (process) 169 kfd_unref_process(process); 170 171 return 0; 172 } 173 174 static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p, 175 void *data) 176 { 177 struct kfd_ioctl_get_version_args *args = data; 178 179 args->major_version = KFD_IOCTL_MAJOR_VERSION; 180 args->minor_version = KFD_IOCTL_MINOR_VERSION; 181 182 return 0; 183 } 184 185 static int set_queue_properties_from_user(struct queue_properties *q_properties, 186 struct kfd_ioctl_create_queue_args *args) 187 { 188 /* 189 * Repurpose queue percentage to accommodate new features: 190 * bit 0-7: queue percentage 191 * bit 8-15: pm4_target_xcc 192 */ 193 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) { 194 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); 195 return -EINVAL; 196 } 197 198 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { 199 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); 200 return -EINVAL; 201 } 202 203 if ((args->ring_base_address) && 204 (!access_ok((const void __user *) args->ring_base_address, 205 sizeof(uint64_t)))) { 206 pr_err("Can't access ring base address\n"); 207 return -EFAULT; 208 } 209 210 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { 211 pr_err("Ring size must be a power of 2 or 0\n"); 212 return -EINVAL; 213 } 214 215 if (args->ring_size < KFD_MIN_QUEUE_RING_SIZE) { 216 args->ring_size = KFD_MIN_QUEUE_RING_SIZE; 217 pr_debug("Size lower. clamped to KFD_MIN_QUEUE_RING_SIZE"); 218 } 219 220 if (!access_ok((const void __user *) args->read_pointer_address, 221 sizeof(uint32_t))) { 222 pr_err("Can't access read pointer\n"); 223 return -EFAULT; 224 } 225 226 if (!access_ok((const void __user *) args->write_pointer_address, 227 sizeof(uint32_t))) { 228 pr_err("Can't access write pointer\n"); 229 return -EFAULT; 230 } 231 232 if (args->eop_buffer_address && 233 !access_ok((const void __user *) args->eop_buffer_address, 234 sizeof(uint32_t))) { 235 pr_debug("Can't access eop buffer"); 236 return -EFAULT; 237 } 238 239 if (args->ctx_save_restore_address && 240 !access_ok((const void __user *) args->ctx_save_restore_address, 241 sizeof(uint32_t))) { 242 pr_debug("Can't access ctx save restore buffer"); 243 return -EFAULT; 244 } 245 246 q_properties->is_interop = false; 247 q_properties->is_gws = false; 248 q_properties->queue_percent = args->queue_percentage & 0xFF; 249 /* bit 8-15 are repurposed to be PM4 target XCC */ 250 q_properties->pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF; 251 q_properties->priority = args->queue_priority; 252 q_properties->queue_address = args->ring_base_address; 253 q_properties->queue_size = args->ring_size; 254 q_properties->read_ptr = (void __user *)args->read_pointer_address; 255 q_properties->write_ptr = (void __user *)args->write_pointer_address; 256 q_properties->eop_ring_buffer_address = args->eop_buffer_address; 257 q_properties->eop_ring_buffer_size = args->eop_buffer_size; 258 q_properties->ctx_save_restore_area_address = 259 args->ctx_save_restore_address; 260 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size; 261 q_properties->ctl_stack_size = args->ctl_stack_size; 262 q_properties->sdma_engine_id = args->sdma_engine_id; 263 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE || 264 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) 265 q_properties->type = KFD_QUEUE_TYPE_COMPUTE; 266 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA) 267 q_properties->type = KFD_QUEUE_TYPE_SDMA; 268 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI) 269 q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI; 270 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_BY_ENG_ID) 271 q_properties->type = KFD_QUEUE_TYPE_SDMA_BY_ENG_ID; 272 else 273 return -ENOTSUPP; 274 275 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) 276 q_properties->format = KFD_QUEUE_FORMAT_AQL; 277 else 278 q_properties->format = KFD_QUEUE_FORMAT_PM4; 279 280 pr_debug("Queue Percentage: %d, %d\n", 281 q_properties->queue_percent, args->queue_percentage); 282 283 pr_debug("Queue Priority: %d, %d\n", 284 q_properties->priority, args->queue_priority); 285 286 pr_debug("Queue Address: 0x%llX, 0x%llX\n", 287 q_properties->queue_address, args->ring_base_address); 288 289 pr_debug("Queue Size: 0x%llX, %u\n", 290 q_properties->queue_size, args->ring_size); 291 292 pr_debug("Queue r/w Pointers: %px, %px\n", 293 q_properties->read_ptr, 294 q_properties->write_ptr); 295 296 pr_debug("Queue Format: %d\n", q_properties->format); 297 298 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address); 299 300 pr_debug("Queue CTX save area: 0x%llX\n", 301 q_properties->ctx_save_restore_area_address); 302 303 return 0; 304 } 305 306 static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, 307 void *data) 308 { 309 struct kfd_ioctl_create_queue_args *args = data; 310 struct kfd_node *dev; 311 int err = 0; 312 unsigned int queue_id; 313 struct kfd_process_device *pdd; 314 struct queue_properties q_properties; 315 uint32_t doorbell_offset_in_process = 0; 316 317 memset(&q_properties, 0, sizeof(struct queue_properties)); 318 319 pr_debug("Creating queue ioctl\n"); 320 321 err = set_queue_properties_from_user(&q_properties, args); 322 if (err) 323 return err; 324 325 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id); 326 327 mutex_lock(&p->mutex); 328 329 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 330 if (!pdd) { 331 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); 332 err = -EINVAL; 333 goto err_pdd; 334 } 335 dev = pdd->dev; 336 337 pdd = kfd_bind_process_to_device(dev, p); 338 if (IS_ERR(pdd)) { 339 err = -ESRCH; 340 goto err_bind_process; 341 } 342 343 if (q_properties.type == KFD_QUEUE_TYPE_SDMA_BY_ENG_ID) { 344 int max_sdma_eng_id = kfd_get_num_sdma_engines(dev) + 345 kfd_get_num_xgmi_sdma_engines(dev) - 1; 346 347 if (q_properties.sdma_engine_id > max_sdma_eng_id) { 348 err = -EINVAL; 349 pr_err("sdma_engine_id %i exceeds maximum id of %i\n", 350 q_properties.sdma_engine_id, max_sdma_eng_id); 351 goto err_sdma_engine_id; 352 } 353 } 354 355 if (!pdd->qpd.proc_doorbells) { 356 err = kfd_alloc_process_doorbells(dev->kfd, pdd); 357 if (err) { 358 pr_debug("failed to allocate process doorbells\n"); 359 goto err_bind_process; 360 } 361 } 362 363 err = kfd_queue_acquire_buffers(pdd, &q_properties); 364 if (err) { 365 pr_debug("failed to acquire user queue buffers\n"); 366 goto err_acquire_queue_buf; 367 } 368 369 pr_debug("Creating queue for process pid %d on gpu 0x%x\n", 370 p->lead_thread->pid, 371 dev->id); 372 373 err = pqm_create_queue(&p->pqm, dev, &q_properties, &queue_id, 374 NULL, NULL, NULL, &doorbell_offset_in_process); 375 if (err != 0) 376 goto err_create_queue; 377 378 args->queue_id = queue_id; 379 380 381 /* Return gpu_id as doorbell offset for mmap usage */ 382 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL; 383 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id); 384 if (KFD_IS_SOC15(dev)) 385 /* On SOC15 ASICs, include the doorbell offset within the 386 * process doorbell frame, which is 2 pages. 387 */ 388 args->doorbell_offset |= doorbell_offset_in_process; 389 390 mutex_unlock(&p->mutex); 391 392 pr_debug("Queue id %d was created successfully\n", args->queue_id); 393 394 pr_debug("Ring buffer address == 0x%016llX\n", 395 args->ring_base_address); 396 397 pr_debug("Read ptr address == 0x%016llX\n", 398 args->read_pointer_address); 399 400 pr_debug("Write ptr address == 0x%016llX\n", 401 args->write_pointer_address); 402 403 kfd_dbg_ev_raise(KFD_EC_MASK(EC_QUEUE_NEW), p, dev, queue_id, false, NULL, 0); 404 return 0; 405 406 err_create_queue: 407 kfd_queue_unref_bo_vas(pdd, &q_properties); 408 kfd_queue_release_buffers(pdd, &q_properties); 409 err_acquire_queue_buf: 410 err_sdma_engine_id: 411 err_bind_process: 412 err_pdd: 413 mutex_unlock(&p->mutex); 414 return err; 415 } 416 417 static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p, 418 void *data) 419 { 420 int retval; 421 struct kfd_ioctl_destroy_queue_args *args = data; 422 423 pr_debug("Destroying queue id %d for process pid %d\n", 424 args->queue_id, 425 p->lead_thread->pid); 426 427 mutex_lock(&p->mutex); 428 429 retval = pqm_destroy_queue(&p->pqm, args->queue_id); 430 431 mutex_unlock(&p->mutex); 432 return retval; 433 } 434 435 static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, 436 void *data) 437 { 438 int retval; 439 struct kfd_ioctl_update_queue_args *args = data; 440 struct queue_properties properties; 441 442 /* 443 * Repurpose queue percentage to accommodate new features: 444 * bit 0-7: queue percentage 445 * bit 8-15: pm4_target_xcc 446 */ 447 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) { 448 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n"); 449 return -EINVAL; 450 } 451 452 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) { 453 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n"); 454 return -EINVAL; 455 } 456 457 if ((args->ring_base_address) && 458 (!access_ok((const void __user *) args->ring_base_address, 459 sizeof(uint64_t)))) { 460 pr_err("Can't access ring base address\n"); 461 return -EFAULT; 462 } 463 464 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) { 465 pr_err("Ring size must be a power of 2 or 0\n"); 466 return -EINVAL; 467 } 468 469 if (args->ring_size < KFD_MIN_QUEUE_RING_SIZE) { 470 args->ring_size = KFD_MIN_QUEUE_RING_SIZE; 471 pr_debug("Size lower. clamped to KFD_MIN_QUEUE_RING_SIZE"); 472 } 473 474 properties.queue_address = args->ring_base_address; 475 properties.queue_size = args->ring_size; 476 properties.queue_percent = args->queue_percentage & 0xFF; 477 /* bit 8-15 are repurposed to be PM4 target XCC */ 478 properties.pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF; 479 properties.priority = args->queue_priority; 480 481 pr_debug("Updating queue id %d for process pid %d\n", 482 args->queue_id, p->lead_thread->pid); 483 484 mutex_lock(&p->mutex); 485 486 retval = pqm_update_queue_properties(&p->pqm, args->queue_id, &properties); 487 488 mutex_unlock(&p->mutex); 489 490 return retval; 491 } 492 493 static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p, 494 void *data) 495 { 496 int retval; 497 const int max_num_cus = 1024; 498 struct kfd_ioctl_set_cu_mask_args *args = data; 499 struct mqd_update_info minfo = {0}; 500 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr; 501 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32); 502 503 if ((args->num_cu_mask % 32) != 0) { 504 pr_debug("num_cu_mask 0x%x must be a multiple of 32", 505 args->num_cu_mask); 506 return -EINVAL; 507 } 508 509 minfo.cu_mask.count = args->num_cu_mask; 510 if (minfo.cu_mask.count == 0) { 511 pr_debug("CU mask cannot be 0"); 512 return -EINVAL; 513 } 514 515 /* To prevent an unreasonably large CU mask size, set an arbitrary 516 * limit of max_num_cus bits. We can then just drop any CU mask bits 517 * past max_num_cus bits and just use the first max_num_cus bits. 518 */ 519 if (minfo.cu_mask.count > max_num_cus) { 520 pr_debug("CU mask cannot be greater than 1024 bits"); 521 minfo.cu_mask.count = max_num_cus; 522 cu_mask_size = sizeof(uint32_t) * (max_num_cus/32); 523 } 524 525 minfo.cu_mask.ptr = kzalloc(cu_mask_size, GFP_KERNEL); 526 if (!minfo.cu_mask.ptr) 527 return -ENOMEM; 528 529 retval = copy_from_user(minfo.cu_mask.ptr, cu_mask_ptr, cu_mask_size); 530 if (retval) { 531 pr_debug("Could not copy CU mask from userspace"); 532 retval = -EFAULT; 533 goto out; 534 } 535 536 mutex_lock(&p->mutex); 537 538 retval = pqm_update_mqd(&p->pqm, args->queue_id, &minfo); 539 540 mutex_unlock(&p->mutex); 541 542 out: 543 kfree(minfo.cu_mask.ptr); 544 return retval; 545 } 546 547 static int kfd_ioctl_get_queue_wave_state(struct file *filep, 548 struct kfd_process *p, void *data) 549 { 550 struct kfd_ioctl_get_queue_wave_state_args *args = data; 551 int r; 552 553 mutex_lock(&p->mutex); 554 555 r = pqm_get_wave_state(&p->pqm, args->queue_id, 556 (void __user *)args->ctl_stack_address, 557 &args->ctl_stack_used_size, 558 &args->save_area_used_size); 559 560 mutex_unlock(&p->mutex); 561 562 return r; 563 } 564 565 static int kfd_ioctl_set_memory_policy(struct file *filep, 566 struct kfd_process *p, void *data) 567 { 568 struct kfd_ioctl_set_memory_policy_args *args = data; 569 int err = 0; 570 struct kfd_process_device *pdd; 571 enum cache_policy default_policy, alternate_policy; 572 573 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT 574 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { 575 return -EINVAL; 576 } 577 578 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT 579 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) { 580 return -EINVAL; 581 } 582 583 mutex_lock(&p->mutex); 584 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 585 if (!pdd) { 586 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); 587 err = -EINVAL; 588 goto err_pdd; 589 } 590 591 pdd = kfd_bind_process_to_device(pdd->dev, p); 592 if (IS_ERR(pdd)) { 593 err = -ESRCH; 594 goto out; 595 } 596 597 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT) 598 ? cache_policy_coherent : cache_policy_noncoherent; 599 600 alternate_policy = 601 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT) 602 ? cache_policy_coherent : cache_policy_noncoherent; 603 604 if (!pdd->dev->dqm->ops.set_cache_memory_policy(pdd->dev->dqm, 605 &pdd->qpd, 606 default_policy, 607 alternate_policy, 608 (void __user *)args->alternate_aperture_base, 609 args->alternate_aperture_size, 610 args->misc_process_flag)) 611 err = -EINVAL; 612 613 out: 614 err_pdd: 615 mutex_unlock(&p->mutex); 616 617 return err; 618 } 619 620 static int kfd_ioctl_set_trap_handler(struct file *filep, 621 struct kfd_process *p, void *data) 622 { 623 struct kfd_ioctl_set_trap_handler_args *args = data; 624 int err = 0; 625 struct kfd_process_device *pdd; 626 627 mutex_lock(&p->mutex); 628 629 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 630 if (!pdd) { 631 err = -EINVAL; 632 goto err_pdd; 633 } 634 635 pdd = kfd_bind_process_to_device(pdd->dev, p); 636 if (IS_ERR(pdd)) { 637 err = -ESRCH; 638 goto out; 639 } 640 641 kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr); 642 643 out: 644 err_pdd: 645 mutex_unlock(&p->mutex); 646 647 return err; 648 } 649 650 static int kfd_ioctl_dbg_register(struct file *filep, 651 struct kfd_process *p, void *data) 652 { 653 return -EPERM; 654 } 655 656 static int kfd_ioctl_dbg_unregister(struct file *filep, 657 struct kfd_process *p, void *data) 658 { 659 return -EPERM; 660 } 661 662 static int kfd_ioctl_dbg_address_watch(struct file *filep, 663 struct kfd_process *p, void *data) 664 { 665 return -EPERM; 666 } 667 668 /* Parse and generate fixed size data structure for wave control */ 669 static int kfd_ioctl_dbg_wave_control(struct file *filep, 670 struct kfd_process *p, void *data) 671 { 672 return -EPERM; 673 } 674 675 static int kfd_ioctl_get_clock_counters(struct file *filep, 676 struct kfd_process *p, void *data) 677 { 678 struct kfd_ioctl_get_clock_counters_args *args = data; 679 struct kfd_process_device *pdd; 680 681 mutex_lock(&p->mutex); 682 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 683 mutex_unlock(&p->mutex); 684 if (pdd) 685 /* Reading GPU clock counter from KGD */ 686 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(pdd->dev->adev); 687 else 688 /* Node without GPU resource */ 689 args->gpu_clock_counter = 0; 690 691 /* No access to rdtsc. Using raw monotonic time */ 692 args->cpu_clock_counter = ktime_get_raw_ns(); 693 args->system_clock_counter = ktime_get_boottime_ns(); 694 695 /* Since the counter is in nano-seconds we use 1GHz frequency */ 696 args->system_clock_freq = 1000000000; 697 698 return 0; 699 } 700 701 702 static int kfd_ioctl_get_process_apertures(struct file *filp, 703 struct kfd_process *p, void *data) 704 { 705 struct kfd_ioctl_get_process_apertures_args *args = data; 706 struct kfd_process_device_apertures *pAperture; 707 int i; 708 709 dev_dbg(kfd_device, "get apertures for process pid %d", p->lead_thread->pid); 710 711 args->num_of_nodes = 0; 712 713 mutex_lock(&p->mutex); 714 /* Run over all pdd of the process */ 715 for (i = 0; i < p->n_pdds; i++) { 716 struct kfd_process_device *pdd = p->pdds[i]; 717 718 pAperture = 719 &args->process_apertures[args->num_of_nodes]; 720 pAperture->gpu_id = pdd->dev->id; 721 pAperture->lds_base = pdd->lds_base; 722 pAperture->lds_limit = pdd->lds_limit; 723 pAperture->gpuvm_base = pdd->gpuvm_base; 724 pAperture->gpuvm_limit = pdd->gpuvm_limit; 725 pAperture->scratch_base = pdd->scratch_base; 726 pAperture->scratch_limit = pdd->scratch_limit; 727 728 dev_dbg(kfd_device, 729 "node id %u\n", args->num_of_nodes); 730 dev_dbg(kfd_device, 731 "gpu id %u\n", pdd->dev->id); 732 dev_dbg(kfd_device, 733 "lds_base %llX\n", pdd->lds_base); 734 dev_dbg(kfd_device, 735 "lds_limit %llX\n", pdd->lds_limit); 736 dev_dbg(kfd_device, 737 "gpuvm_base %llX\n", pdd->gpuvm_base); 738 dev_dbg(kfd_device, 739 "gpuvm_limit %llX\n", pdd->gpuvm_limit); 740 dev_dbg(kfd_device, 741 "scratch_base %llX\n", pdd->scratch_base); 742 dev_dbg(kfd_device, 743 "scratch_limit %llX\n", pdd->scratch_limit); 744 745 if (++args->num_of_nodes >= NUM_OF_SUPPORTED_GPUS) 746 break; 747 } 748 mutex_unlock(&p->mutex); 749 750 return 0; 751 } 752 753 static int kfd_ioctl_get_process_apertures_new(struct file *filp, 754 struct kfd_process *p, void *data) 755 { 756 struct kfd_ioctl_get_process_apertures_new_args *args = data; 757 struct kfd_process_device_apertures *pa; 758 int ret; 759 int i; 760 761 dev_dbg(kfd_device, "get apertures for process pid %d", 762 p->lead_thread->pid); 763 764 if (args->num_of_nodes == 0) { 765 /* Return number of nodes, so that user space can alloacate 766 * sufficient memory 767 */ 768 mutex_lock(&p->mutex); 769 args->num_of_nodes = p->n_pdds; 770 goto out_unlock; 771 } 772 773 /* Fill in process-aperture information for all available 774 * nodes, but not more than args->num_of_nodes as that is 775 * the amount of memory allocated by user 776 */ 777 pa = kcalloc(args->num_of_nodes, sizeof(struct kfd_process_device_apertures), 778 GFP_KERNEL); 779 if (!pa) 780 return -ENOMEM; 781 782 mutex_lock(&p->mutex); 783 784 if (!p->n_pdds) { 785 args->num_of_nodes = 0; 786 kfree(pa); 787 goto out_unlock; 788 } 789 790 /* Run over all pdd of the process */ 791 for (i = 0; i < min(p->n_pdds, args->num_of_nodes); i++) { 792 struct kfd_process_device *pdd = p->pdds[i]; 793 794 pa[i].gpu_id = pdd->dev->id; 795 pa[i].lds_base = pdd->lds_base; 796 pa[i].lds_limit = pdd->lds_limit; 797 pa[i].gpuvm_base = pdd->gpuvm_base; 798 pa[i].gpuvm_limit = pdd->gpuvm_limit; 799 pa[i].scratch_base = pdd->scratch_base; 800 pa[i].scratch_limit = pdd->scratch_limit; 801 802 dev_dbg(kfd_device, 803 "gpu id %u\n", pdd->dev->id); 804 dev_dbg(kfd_device, 805 "lds_base %llX\n", pdd->lds_base); 806 dev_dbg(kfd_device, 807 "lds_limit %llX\n", pdd->lds_limit); 808 dev_dbg(kfd_device, 809 "gpuvm_base %llX\n", pdd->gpuvm_base); 810 dev_dbg(kfd_device, 811 "gpuvm_limit %llX\n", pdd->gpuvm_limit); 812 dev_dbg(kfd_device, 813 "scratch_base %llX\n", pdd->scratch_base); 814 dev_dbg(kfd_device, 815 "scratch_limit %llX\n", pdd->scratch_limit); 816 } 817 mutex_unlock(&p->mutex); 818 819 args->num_of_nodes = i; 820 ret = copy_to_user( 821 (void __user *)args->kfd_process_device_apertures_ptr, 822 pa, 823 (i * sizeof(struct kfd_process_device_apertures))); 824 kfree(pa); 825 return ret ? -EFAULT : 0; 826 827 out_unlock: 828 mutex_unlock(&p->mutex); 829 return 0; 830 } 831 832 static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p, 833 void *data) 834 { 835 struct kfd_ioctl_create_event_args *args = data; 836 int err; 837 838 /* For dGPUs the event page is allocated in user mode. The 839 * handle is passed to KFD with the first call to this IOCTL 840 * through the event_page_offset field. 841 */ 842 if (args->event_page_offset) { 843 mutex_lock(&p->mutex); 844 err = kfd_kmap_event_page(p, args->event_page_offset); 845 mutex_unlock(&p->mutex); 846 if (err) 847 return err; 848 } 849 850 err = kfd_event_create(filp, p, args->event_type, 851 args->auto_reset != 0, args->node_id, 852 &args->event_id, &args->event_trigger_data, 853 &args->event_page_offset, 854 &args->event_slot_index); 855 856 pr_debug("Created event (id:0x%08x) (%s)\n", args->event_id, __func__); 857 return err; 858 } 859 860 static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p, 861 void *data) 862 { 863 struct kfd_ioctl_destroy_event_args *args = data; 864 865 return kfd_event_destroy(p, args->event_id); 866 } 867 868 static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p, 869 void *data) 870 { 871 struct kfd_ioctl_set_event_args *args = data; 872 873 return kfd_set_event(p, args->event_id); 874 } 875 876 static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p, 877 void *data) 878 { 879 struct kfd_ioctl_reset_event_args *args = data; 880 881 return kfd_reset_event(p, args->event_id); 882 } 883 884 static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p, 885 void *data) 886 { 887 struct kfd_ioctl_wait_events_args *args = data; 888 889 return kfd_wait_on_events(p, args->num_events, 890 (void __user *)args->events_ptr, 891 (args->wait_for_all != 0), 892 &args->timeout, &args->wait_result); 893 } 894 static int kfd_ioctl_set_scratch_backing_va(struct file *filep, 895 struct kfd_process *p, void *data) 896 { 897 struct kfd_ioctl_set_scratch_backing_va_args *args = data; 898 struct kfd_process_device *pdd; 899 struct kfd_node *dev; 900 long err; 901 902 mutex_lock(&p->mutex); 903 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 904 if (!pdd) { 905 err = -EINVAL; 906 goto err_pdd; 907 } 908 dev = pdd->dev; 909 910 pdd = kfd_bind_process_to_device(dev, p); 911 if (IS_ERR(pdd)) { 912 err = PTR_ERR(pdd); 913 goto bind_process_to_device_fail; 914 } 915 916 pdd->qpd.sh_hidden_private_base = args->va_addr; 917 918 mutex_unlock(&p->mutex); 919 920 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS && 921 pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va) 922 dev->kfd2kgd->set_scratch_backing_va( 923 dev->adev, args->va_addr, pdd->qpd.vmid); 924 925 return 0; 926 927 bind_process_to_device_fail: 928 err_pdd: 929 mutex_unlock(&p->mutex); 930 return err; 931 } 932 933 static int kfd_ioctl_get_tile_config(struct file *filep, 934 struct kfd_process *p, void *data) 935 { 936 struct kfd_ioctl_get_tile_config_args *args = data; 937 struct kfd_process_device *pdd; 938 struct tile_config config; 939 int err = 0; 940 941 mutex_lock(&p->mutex); 942 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 943 mutex_unlock(&p->mutex); 944 if (!pdd) 945 return -EINVAL; 946 947 amdgpu_amdkfd_get_tile_config(pdd->dev->adev, &config); 948 949 args->gb_addr_config = config.gb_addr_config; 950 args->num_banks = config.num_banks; 951 args->num_ranks = config.num_ranks; 952 953 if (args->num_tile_configs > config.num_tile_configs) 954 args->num_tile_configs = config.num_tile_configs; 955 err = copy_to_user((void __user *)args->tile_config_ptr, 956 config.tile_config_ptr, 957 args->num_tile_configs * sizeof(uint32_t)); 958 if (err) { 959 args->num_tile_configs = 0; 960 return -EFAULT; 961 } 962 963 if (args->num_macro_tile_configs > config.num_macro_tile_configs) 964 args->num_macro_tile_configs = 965 config.num_macro_tile_configs; 966 err = copy_to_user((void __user *)args->macro_tile_config_ptr, 967 config.macro_tile_config_ptr, 968 args->num_macro_tile_configs * sizeof(uint32_t)); 969 if (err) { 970 args->num_macro_tile_configs = 0; 971 return -EFAULT; 972 } 973 974 return 0; 975 } 976 977 static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p, 978 void *data) 979 { 980 struct kfd_ioctl_acquire_vm_args *args = data; 981 struct kfd_process_device *pdd; 982 struct file *drm_file; 983 int ret; 984 985 drm_file = fget(args->drm_fd); 986 if (!drm_file) 987 return -EINVAL; 988 989 mutex_lock(&p->mutex); 990 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 991 if (!pdd) { 992 ret = -EINVAL; 993 goto err_pdd; 994 } 995 996 if (pdd->drm_file) { 997 ret = pdd->drm_file == drm_file ? 0 : -EBUSY; 998 goto err_drm_file; 999 } 1000 1001 ret = kfd_process_device_init_vm(pdd, drm_file); 1002 if (ret) 1003 goto err_unlock; 1004 1005 /* On success, the PDD keeps the drm_file reference */ 1006 mutex_unlock(&p->mutex); 1007 1008 return 0; 1009 1010 err_unlock: 1011 err_pdd: 1012 err_drm_file: 1013 mutex_unlock(&p->mutex); 1014 fput(drm_file); 1015 return ret; 1016 } 1017 1018 bool kfd_dev_is_large_bar(struct kfd_node *dev) 1019 { 1020 if (dev->kfd->adev->debug_largebar) { 1021 pr_debug("Simulate large-bar allocation on non large-bar machine\n"); 1022 return true; 1023 } 1024 1025 if (dev->local_mem_info.local_mem_size_private == 0 && 1026 dev->local_mem_info.local_mem_size_public > 0) 1027 return true; 1028 1029 if (dev->local_mem_info.local_mem_size_public == 0 && 1030 dev->kfd->adev->gmc.is_app_apu) { 1031 pr_debug("APP APU, Consider like a large bar system\n"); 1032 return true; 1033 } 1034 1035 return false; 1036 } 1037 1038 static int kfd_ioctl_get_available_memory(struct file *filep, 1039 struct kfd_process *p, void *data) 1040 { 1041 struct kfd_ioctl_get_available_memory_args *args = data; 1042 struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id); 1043 1044 if (!pdd) 1045 return -EINVAL; 1046 args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev, 1047 pdd->dev->node_id); 1048 kfd_unlock_pdd(pdd); 1049 return 0; 1050 } 1051 1052 static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, 1053 struct kfd_process *p, void *data) 1054 { 1055 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data; 1056 struct kfd_process_device *pdd; 1057 void *mem; 1058 struct kfd_node *dev; 1059 int idr_handle; 1060 long err; 1061 uint64_t offset = args->mmap_offset; 1062 uint32_t flags = args->flags; 1063 1064 if (args->size == 0) 1065 return -EINVAL; 1066 1067 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 1068 /* Flush pending deferred work to avoid racing with deferred actions 1069 * from previous memory map changes (e.g. munmap). 1070 */ 1071 svm_range_list_lock_and_flush_work(&p->svms, current->mm); 1072 mutex_lock(&p->svms.lock); 1073 mmap_write_unlock(current->mm); 1074 if (interval_tree_iter_first(&p->svms.objects, 1075 args->va_addr >> PAGE_SHIFT, 1076 (args->va_addr + args->size - 1) >> PAGE_SHIFT)) { 1077 pr_err("Address: 0x%llx already allocated by SVM\n", 1078 args->va_addr); 1079 mutex_unlock(&p->svms.lock); 1080 return -EADDRINUSE; 1081 } 1082 1083 /* When register user buffer check if it has been registered by svm by 1084 * buffer cpu virtual address. 1085 */ 1086 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) && 1087 interval_tree_iter_first(&p->svms.objects, 1088 args->mmap_offset >> PAGE_SHIFT, 1089 (args->mmap_offset + args->size - 1) >> PAGE_SHIFT)) { 1090 pr_err("User Buffer Address: 0x%llx already allocated by SVM\n", 1091 args->mmap_offset); 1092 mutex_unlock(&p->svms.lock); 1093 return -EADDRINUSE; 1094 } 1095 1096 mutex_unlock(&p->svms.lock); 1097 #endif 1098 mutex_lock(&p->mutex); 1099 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 1100 if (!pdd) { 1101 err = -EINVAL; 1102 goto err_pdd; 1103 } 1104 1105 dev = pdd->dev; 1106 1107 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) && 1108 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) && 1109 !kfd_dev_is_large_bar(dev)) { 1110 pr_err("Alloc host visible vram on small bar is not allowed\n"); 1111 err = -EINVAL; 1112 goto err_large_bar; 1113 } 1114 1115 pdd = kfd_bind_process_to_device(dev, p); 1116 if (IS_ERR(pdd)) { 1117 err = PTR_ERR(pdd); 1118 goto err_unlock; 1119 } 1120 1121 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { 1122 if (args->size != kfd_doorbell_process_slice(dev->kfd)) { 1123 err = -EINVAL; 1124 goto err_unlock; 1125 } 1126 offset = kfd_get_process_doorbells(pdd); 1127 if (!offset) { 1128 err = -ENOMEM; 1129 goto err_unlock; 1130 } 1131 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 1132 if (args->size != PAGE_SIZE) { 1133 err = -EINVAL; 1134 goto err_unlock; 1135 } 1136 offset = dev->adev->rmmio_remap.bus_addr; 1137 if (!offset || (PAGE_SIZE > 4096)) { 1138 err = -ENOMEM; 1139 goto err_unlock; 1140 } 1141 } 1142 1143 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 1144 dev->adev, args->va_addr, args->size, 1145 pdd->drm_priv, (struct kgd_mem **) &mem, &offset, 1146 flags, false); 1147 1148 if (err) 1149 goto err_unlock; 1150 1151 idr_handle = kfd_process_device_create_obj_handle(pdd, mem); 1152 if (idr_handle < 0) { 1153 err = -EFAULT; 1154 goto err_free; 1155 } 1156 1157 /* Update the VRAM usage count */ 1158 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 1159 uint64_t size = args->size; 1160 1161 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM) 1162 size >>= 1; 1163 atomic64_add(PAGE_ALIGN(size), &pdd->vram_usage); 1164 } 1165 1166 mutex_unlock(&p->mutex); 1167 1168 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle); 1169 args->mmap_offset = offset; 1170 1171 /* MMIO is mapped through kfd device 1172 * Generate a kfd mmap offset 1173 */ 1174 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) 1175 args->mmap_offset = KFD_MMAP_TYPE_MMIO 1176 | KFD_MMAP_GPU_ID(args->gpu_id); 1177 1178 return 0; 1179 1180 err_free: 1181 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, 1182 pdd->drm_priv, NULL); 1183 err_unlock: 1184 err_pdd: 1185 err_large_bar: 1186 mutex_unlock(&p->mutex); 1187 return err; 1188 } 1189 1190 static int kfd_ioctl_free_memory_of_gpu(struct file *filep, 1191 struct kfd_process *p, void *data) 1192 { 1193 struct kfd_ioctl_free_memory_of_gpu_args *args = data; 1194 struct kfd_process_device *pdd; 1195 void *mem; 1196 int ret; 1197 uint64_t size = 0; 1198 1199 mutex_lock(&p->mutex); 1200 /* 1201 * Safeguard to prevent user space from freeing signal BO. 1202 * It will be freed at process termination. 1203 */ 1204 if (p->signal_handle && (p->signal_handle == args->handle)) { 1205 pr_err("Free signal BO is not allowed\n"); 1206 ret = -EPERM; 1207 goto err_unlock; 1208 } 1209 1210 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1211 if (!pdd) { 1212 pr_err("Process device data doesn't exist\n"); 1213 ret = -EINVAL; 1214 goto err_pdd; 1215 } 1216 1217 mem = kfd_process_device_translate_handle( 1218 pdd, GET_IDR_HANDLE(args->handle)); 1219 if (!mem) { 1220 ret = -EINVAL; 1221 goto err_unlock; 1222 } 1223 1224 ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, 1225 (struct kgd_mem *)mem, pdd->drm_priv, &size); 1226 1227 /* If freeing the buffer failed, leave the handle in place for 1228 * clean-up during process tear-down. 1229 */ 1230 if (!ret) 1231 kfd_process_device_remove_obj_handle( 1232 pdd, GET_IDR_HANDLE(args->handle)); 1233 1234 atomic64_sub(size, &pdd->vram_usage); 1235 1236 err_unlock: 1237 err_pdd: 1238 mutex_unlock(&p->mutex); 1239 return ret; 1240 } 1241 1242 static int kfd_ioctl_map_memory_to_gpu(struct file *filep, 1243 struct kfd_process *p, void *data) 1244 { 1245 struct kfd_ioctl_map_memory_to_gpu_args *args = data; 1246 struct kfd_process_device *pdd, *peer_pdd; 1247 void *mem; 1248 struct kfd_node *dev; 1249 long err = 0; 1250 int i; 1251 uint32_t *devices_arr = NULL; 1252 1253 if (!args->n_devices) { 1254 pr_debug("Device IDs array empty\n"); 1255 return -EINVAL; 1256 } 1257 if (args->n_success > args->n_devices) { 1258 pr_debug("n_success exceeds n_devices\n"); 1259 return -EINVAL; 1260 } 1261 1262 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr), 1263 GFP_KERNEL); 1264 if (!devices_arr) 1265 return -ENOMEM; 1266 1267 err = copy_from_user(devices_arr, 1268 (void __user *)args->device_ids_array_ptr, 1269 args->n_devices * sizeof(*devices_arr)); 1270 if (err != 0) { 1271 err = -EFAULT; 1272 goto copy_from_user_failed; 1273 } 1274 1275 mutex_lock(&p->mutex); 1276 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1277 if (!pdd) { 1278 err = -EINVAL; 1279 goto get_process_device_data_failed; 1280 } 1281 dev = pdd->dev; 1282 1283 pdd = kfd_bind_process_to_device(dev, p); 1284 if (IS_ERR(pdd)) { 1285 err = PTR_ERR(pdd); 1286 goto bind_process_to_device_failed; 1287 } 1288 1289 mem = kfd_process_device_translate_handle(pdd, 1290 GET_IDR_HANDLE(args->handle)); 1291 if (!mem) { 1292 err = -ENOMEM; 1293 goto get_mem_obj_from_handle_failed; 1294 } 1295 1296 for (i = args->n_success; i < args->n_devices; i++) { 1297 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1298 if (!peer_pdd) { 1299 pr_debug("Getting device by id failed for 0x%x\n", 1300 devices_arr[i]); 1301 err = -EINVAL; 1302 goto get_mem_obj_from_handle_failed; 1303 } 1304 1305 peer_pdd = kfd_bind_process_to_device(peer_pdd->dev, p); 1306 if (IS_ERR(peer_pdd)) { 1307 err = PTR_ERR(peer_pdd); 1308 goto get_mem_obj_from_handle_failed; 1309 } 1310 1311 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu( 1312 peer_pdd->dev->adev, (struct kgd_mem *)mem, 1313 peer_pdd->drm_priv); 1314 if (err) { 1315 struct pci_dev *pdev = peer_pdd->dev->adev->pdev; 1316 1317 dev_err(dev->adev->dev, 1318 "Failed to map peer:%04x:%02x:%02x.%d mem_domain:%d\n", 1319 pci_domain_nr(pdev->bus), 1320 pdev->bus->number, 1321 PCI_SLOT(pdev->devfn), 1322 PCI_FUNC(pdev->devfn), 1323 ((struct kgd_mem *)mem)->domain); 1324 goto map_memory_to_gpu_failed; 1325 } 1326 args->n_success = i+1; 1327 } 1328 1329 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev, (struct kgd_mem *) mem, true); 1330 if (err) { 1331 pr_debug("Sync memory failed, wait interrupted by user signal\n"); 1332 goto sync_memory_failed; 1333 } 1334 1335 mutex_unlock(&p->mutex); 1336 1337 /* Flush TLBs after waiting for the page table updates to complete */ 1338 for (i = 0; i < args->n_devices; i++) { 1339 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1340 if (WARN_ON_ONCE(!peer_pdd)) 1341 continue; 1342 kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY); 1343 } 1344 kfree(devices_arr); 1345 1346 return err; 1347 1348 get_process_device_data_failed: 1349 bind_process_to_device_failed: 1350 get_mem_obj_from_handle_failed: 1351 map_memory_to_gpu_failed: 1352 sync_memory_failed: 1353 mutex_unlock(&p->mutex); 1354 copy_from_user_failed: 1355 kfree(devices_arr); 1356 1357 return err; 1358 } 1359 1360 static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, 1361 struct kfd_process *p, void *data) 1362 { 1363 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data; 1364 struct kfd_process_device *pdd, *peer_pdd; 1365 void *mem; 1366 long err = 0; 1367 uint32_t *devices_arr = NULL, i; 1368 bool flush_tlb; 1369 1370 if (!args->n_devices) { 1371 pr_debug("Device IDs array empty\n"); 1372 return -EINVAL; 1373 } 1374 if (args->n_success > args->n_devices) { 1375 pr_debug("n_success exceeds n_devices\n"); 1376 return -EINVAL; 1377 } 1378 1379 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr), 1380 GFP_KERNEL); 1381 if (!devices_arr) 1382 return -ENOMEM; 1383 1384 err = copy_from_user(devices_arr, 1385 (void __user *)args->device_ids_array_ptr, 1386 args->n_devices * sizeof(*devices_arr)); 1387 if (err != 0) { 1388 err = -EFAULT; 1389 goto copy_from_user_failed; 1390 } 1391 1392 mutex_lock(&p->mutex); 1393 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle)); 1394 if (!pdd) { 1395 err = -EINVAL; 1396 goto bind_process_to_device_failed; 1397 } 1398 1399 mem = kfd_process_device_translate_handle(pdd, 1400 GET_IDR_HANDLE(args->handle)); 1401 if (!mem) { 1402 err = -ENOMEM; 1403 goto get_mem_obj_from_handle_failed; 1404 } 1405 1406 for (i = args->n_success; i < args->n_devices; i++) { 1407 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1408 if (!peer_pdd) { 1409 err = -EINVAL; 1410 goto get_mem_obj_from_handle_failed; 1411 } 1412 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 1413 peer_pdd->dev->adev, (struct kgd_mem *)mem, peer_pdd->drm_priv); 1414 if (err) { 1415 pr_debug("Failed to unmap from gpu %d/%d\n", i, args->n_devices); 1416 goto unmap_memory_from_gpu_failed; 1417 } 1418 args->n_success = i+1; 1419 } 1420 1421 flush_tlb = kfd_flush_tlb_after_unmap(pdd->dev->kfd); 1422 if (flush_tlb) { 1423 err = amdgpu_amdkfd_gpuvm_sync_memory(pdd->dev->adev, 1424 (struct kgd_mem *) mem, true); 1425 if (err) { 1426 pr_debug("Sync memory failed, wait interrupted by user signal\n"); 1427 goto sync_memory_failed; 1428 } 1429 } 1430 1431 /* Flush TLBs after waiting for the page table updates to complete */ 1432 for (i = 0; i < args->n_devices; i++) { 1433 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]); 1434 if (WARN_ON_ONCE(!peer_pdd)) 1435 continue; 1436 if (flush_tlb) 1437 kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT); 1438 1439 /* Remove dma mapping after tlb flush to avoid IO_PAGE_FAULT */ 1440 err = amdgpu_amdkfd_gpuvm_dmaunmap_mem(mem, peer_pdd->drm_priv); 1441 if (err) 1442 goto sync_memory_failed; 1443 } 1444 1445 mutex_unlock(&p->mutex); 1446 1447 kfree(devices_arr); 1448 1449 return 0; 1450 1451 bind_process_to_device_failed: 1452 get_mem_obj_from_handle_failed: 1453 unmap_memory_from_gpu_failed: 1454 sync_memory_failed: 1455 mutex_unlock(&p->mutex); 1456 copy_from_user_failed: 1457 kfree(devices_arr); 1458 return err; 1459 } 1460 1461 static int kfd_ioctl_alloc_queue_gws(struct file *filep, 1462 struct kfd_process *p, void *data) 1463 { 1464 int retval; 1465 struct kfd_ioctl_alloc_queue_gws_args *args = data; 1466 struct queue *q; 1467 struct kfd_node *dev; 1468 1469 mutex_lock(&p->mutex); 1470 q = pqm_get_user_queue(&p->pqm, args->queue_id); 1471 1472 if (q) { 1473 dev = q->device; 1474 } else { 1475 retval = -EINVAL; 1476 goto out_unlock; 1477 } 1478 1479 if (!dev->gws) { 1480 retval = -ENODEV; 1481 goto out_unlock; 1482 } 1483 1484 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) { 1485 retval = -ENODEV; 1486 goto out_unlock; 1487 } 1488 1489 if (p->debug_trap_enabled && (!kfd_dbg_has_gws_support(dev) || 1490 kfd_dbg_has_cwsr_workaround(dev))) { 1491 retval = -EBUSY; 1492 goto out_unlock; 1493 } 1494 1495 retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL); 1496 mutex_unlock(&p->mutex); 1497 1498 args->first_gws = 0; 1499 return retval; 1500 1501 out_unlock: 1502 mutex_unlock(&p->mutex); 1503 return retval; 1504 } 1505 1506 static int kfd_ioctl_get_dmabuf_info(struct file *filep, 1507 struct kfd_process *p, void *data) 1508 { 1509 struct kfd_ioctl_get_dmabuf_info_args *args = data; 1510 struct kfd_node *dev = NULL; 1511 struct amdgpu_device *dmabuf_adev; 1512 void *metadata_buffer = NULL; 1513 uint32_t flags; 1514 int8_t xcp_id; 1515 unsigned int i; 1516 int r; 1517 1518 /* Find a KFD GPU device that supports the get_dmabuf_info query */ 1519 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++) 1520 if (dev && !kfd_devcgroup_check_permission(dev)) 1521 break; 1522 if (!dev) 1523 return -EINVAL; 1524 1525 if (args->metadata_ptr) { 1526 metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL); 1527 if (!metadata_buffer) 1528 return -ENOMEM; 1529 } 1530 1531 /* Get dmabuf info from KGD */ 1532 r = amdgpu_amdkfd_get_dmabuf_info(dev->adev, args->dmabuf_fd, 1533 &dmabuf_adev, &args->size, 1534 metadata_buffer, args->metadata_size, 1535 &args->metadata_size, &flags, &xcp_id); 1536 if (r) 1537 goto exit; 1538 1539 if (xcp_id >= 0) 1540 args->gpu_id = dmabuf_adev->kfd.dev->nodes[xcp_id]->id; 1541 else 1542 args->gpu_id = dev->id; 1543 args->flags = flags; 1544 1545 /* Copy metadata buffer to user mode */ 1546 if (metadata_buffer) { 1547 r = copy_to_user((void __user *)args->metadata_ptr, 1548 metadata_buffer, args->metadata_size); 1549 if (r != 0) 1550 r = -EFAULT; 1551 } 1552 1553 exit: 1554 kfree(metadata_buffer); 1555 1556 return r; 1557 } 1558 1559 static int kfd_ioctl_import_dmabuf(struct file *filep, 1560 struct kfd_process *p, void *data) 1561 { 1562 struct kfd_ioctl_import_dmabuf_args *args = data; 1563 struct kfd_process_device *pdd; 1564 int idr_handle; 1565 uint64_t size; 1566 void *mem; 1567 int r; 1568 1569 mutex_lock(&p->mutex); 1570 pdd = kfd_process_device_data_by_id(p, args->gpu_id); 1571 if (!pdd) { 1572 r = -EINVAL; 1573 goto err_unlock; 1574 } 1575 1576 pdd = kfd_bind_process_to_device(pdd->dev, p); 1577 if (IS_ERR(pdd)) { 1578 r = PTR_ERR(pdd); 1579 goto err_unlock; 1580 } 1581 1582 r = amdgpu_amdkfd_gpuvm_import_dmabuf_fd(pdd->dev->adev, args->dmabuf_fd, 1583 args->va_addr, pdd->drm_priv, 1584 (struct kgd_mem **)&mem, &size, 1585 NULL); 1586 if (r) 1587 goto err_unlock; 1588 1589 idr_handle = kfd_process_device_create_obj_handle(pdd, mem); 1590 if (idr_handle < 0) { 1591 r = -EFAULT; 1592 goto err_free; 1593 } 1594 1595 mutex_unlock(&p->mutex); 1596 1597 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle); 1598 1599 return 0; 1600 1601 err_free: 1602 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem, 1603 pdd->drm_priv, NULL); 1604 err_unlock: 1605 mutex_unlock(&p->mutex); 1606 return r; 1607 } 1608 1609 static int kfd_ioctl_export_dmabuf(struct file *filep, 1610 struct kfd_process *p, void *data) 1611 { 1612 struct kfd_ioctl_export_dmabuf_args *args = data; 1613 struct kfd_process_device *pdd; 1614 struct dma_buf *dmabuf; 1615 struct kfd_node *dev; 1616 void *mem; 1617 int ret = 0; 1618 1619 dev = kfd_device_by_id(GET_GPU_ID(args->handle)); 1620 if (!dev) 1621 return -EINVAL; 1622 1623 mutex_lock(&p->mutex); 1624 1625 pdd = kfd_get_process_device_data(dev, p); 1626 if (!pdd) { 1627 ret = -EINVAL; 1628 goto err_unlock; 1629 } 1630 1631 mem = kfd_process_device_translate_handle(pdd, 1632 GET_IDR_HANDLE(args->handle)); 1633 if (!mem) { 1634 ret = -EINVAL; 1635 goto err_unlock; 1636 } 1637 1638 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf); 1639 mutex_unlock(&p->mutex); 1640 if (ret) 1641 goto err_out; 1642 1643 ret = dma_buf_fd(dmabuf, args->flags); 1644 if (ret < 0) { 1645 dma_buf_put(dmabuf); 1646 goto err_out; 1647 } 1648 /* dma_buf_fd assigns the reference count to the fd, no need to 1649 * put the reference here. 1650 */ 1651 args->dmabuf_fd = ret; 1652 1653 return 0; 1654 1655 err_unlock: 1656 mutex_unlock(&p->mutex); 1657 err_out: 1658 return ret; 1659 } 1660 1661 /* Handle requests for watching SMI events */ 1662 static int kfd_ioctl_smi_events(struct file *filep, 1663 struct kfd_process *p, void *data) 1664 { 1665 struct kfd_ioctl_smi_events_args *args = data; 1666 struct kfd_process_device *pdd; 1667 1668 mutex_lock(&p->mutex); 1669 1670 pdd = kfd_process_device_data_by_id(p, args->gpuid); 1671 mutex_unlock(&p->mutex); 1672 if (!pdd) 1673 return -EINVAL; 1674 1675 return kfd_smi_event_open(pdd->dev, &args->anon_fd); 1676 } 1677 1678 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 1679 1680 static int kfd_ioctl_set_xnack_mode(struct file *filep, 1681 struct kfd_process *p, void *data) 1682 { 1683 struct kfd_ioctl_set_xnack_mode_args *args = data; 1684 int r = 0; 1685 1686 mutex_lock(&p->mutex); 1687 if (args->xnack_enabled >= 0) { 1688 if (!list_empty(&p->pqm.queues)) { 1689 pr_debug("Process has user queues running\n"); 1690 r = -EBUSY; 1691 goto out_unlock; 1692 } 1693 1694 if (p->xnack_enabled == args->xnack_enabled) 1695 goto out_unlock; 1696 1697 if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) { 1698 r = -EPERM; 1699 goto out_unlock; 1700 } 1701 1702 r = svm_range_switch_xnack_reserve_mem(p, args->xnack_enabled); 1703 } else { 1704 args->xnack_enabled = p->xnack_enabled; 1705 } 1706 1707 out_unlock: 1708 mutex_unlock(&p->mutex); 1709 1710 return r; 1711 } 1712 1713 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) 1714 { 1715 struct kfd_ioctl_svm_args *args = data; 1716 int r = 0; 1717 1718 pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n", 1719 args->start_addr, args->size, args->op, args->nattr); 1720 1721 if ((args->start_addr & ~PAGE_MASK) || (args->size & ~PAGE_MASK)) 1722 return -EINVAL; 1723 if (!args->start_addr || !args->size) 1724 return -EINVAL; 1725 1726 r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr, 1727 args->attrs); 1728 1729 return r; 1730 } 1731 #else 1732 static int kfd_ioctl_set_xnack_mode(struct file *filep, 1733 struct kfd_process *p, void *data) 1734 { 1735 return -EPERM; 1736 } 1737 static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) 1738 { 1739 return -EPERM; 1740 } 1741 #endif 1742 1743 static int criu_checkpoint_process(struct kfd_process *p, 1744 uint8_t __user *user_priv_data, 1745 uint64_t *priv_offset) 1746 { 1747 struct kfd_criu_process_priv_data process_priv; 1748 int ret; 1749 1750 memset(&process_priv, 0, sizeof(process_priv)); 1751 1752 process_priv.version = KFD_CRIU_PRIV_VERSION; 1753 /* For CR, we don't consider negative xnack mode which is used for 1754 * querying without changing it, here 0 simply means disabled and 1 1755 * means enabled so retry for finding a valid PTE. 1756 */ 1757 process_priv.xnack_mode = p->xnack_enabled ? 1 : 0; 1758 1759 ret = copy_to_user(user_priv_data + *priv_offset, 1760 &process_priv, sizeof(process_priv)); 1761 1762 if (ret) { 1763 pr_err("Failed to copy process information to user\n"); 1764 ret = -EFAULT; 1765 } 1766 1767 *priv_offset += sizeof(process_priv); 1768 return ret; 1769 } 1770 1771 static int criu_checkpoint_devices(struct kfd_process *p, 1772 uint32_t num_devices, 1773 uint8_t __user *user_addr, 1774 uint8_t __user *user_priv_data, 1775 uint64_t *priv_offset) 1776 { 1777 struct kfd_criu_device_priv_data *device_priv = NULL; 1778 struct kfd_criu_device_bucket *device_buckets = NULL; 1779 int ret = 0, i; 1780 1781 device_buckets = kvzalloc(num_devices * sizeof(*device_buckets), GFP_KERNEL); 1782 if (!device_buckets) { 1783 ret = -ENOMEM; 1784 goto exit; 1785 } 1786 1787 device_priv = kvzalloc(num_devices * sizeof(*device_priv), GFP_KERNEL); 1788 if (!device_priv) { 1789 ret = -ENOMEM; 1790 goto exit; 1791 } 1792 1793 for (i = 0; i < num_devices; i++) { 1794 struct kfd_process_device *pdd = p->pdds[i]; 1795 1796 device_buckets[i].user_gpu_id = pdd->user_gpu_id; 1797 device_buckets[i].actual_gpu_id = pdd->dev->id; 1798 1799 /* 1800 * priv_data does not contain useful information for now and is reserved for 1801 * future use, so we do not set its contents. 1802 */ 1803 } 1804 1805 ret = copy_to_user(user_addr, device_buckets, num_devices * sizeof(*device_buckets)); 1806 if (ret) { 1807 pr_err("Failed to copy device information to user\n"); 1808 ret = -EFAULT; 1809 goto exit; 1810 } 1811 1812 ret = copy_to_user(user_priv_data + *priv_offset, 1813 device_priv, 1814 num_devices * sizeof(*device_priv)); 1815 if (ret) { 1816 pr_err("Failed to copy device information to user\n"); 1817 ret = -EFAULT; 1818 } 1819 *priv_offset += num_devices * sizeof(*device_priv); 1820 1821 exit: 1822 kvfree(device_buckets); 1823 kvfree(device_priv); 1824 return ret; 1825 } 1826 1827 static uint32_t get_process_num_bos(struct kfd_process *p) 1828 { 1829 uint32_t num_of_bos = 0; 1830 int i; 1831 1832 /* Run over all PDDs of the process */ 1833 for (i = 0; i < p->n_pdds; i++) { 1834 struct kfd_process_device *pdd = p->pdds[i]; 1835 void *mem; 1836 int id; 1837 1838 idr_for_each_entry(&pdd->alloc_idr, mem, id) { 1839 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem; 1840 1841 if (!kgd_mem->va || kgd_mem->va > pdd->gpuvm_base) 1842 num_of_bos++; 1843 } 1844 } 1845 return num_of_bos; 1846 } 1847 1848 static int criu_get_prime_handle(struct kgd_mem *mem, 1849 int flags, u32 *shared_fd, 1850 struct file **file) 1851 { 1852 struct dma_buf *dmabuf; 1853 int ret; 1854 1855 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf); 1856 if (ret) { 1857 pr_err("dmabuf export failed for the BO\n"); 1858 return ret; 1859 } 1860 1861 ret = get_unused_fd_flags(flags); 1862 if (ret < 0) { 1863 pr_err("dmabuf create fd failed, ret:%d\n", ret); 1864 goto out_free_dmabuf; 1865 } 1866 1867 *shared_fd = ret; 1868 *file = dmabuf->file; 1869 return 0; 1870 1871 out_free_dmabuf: 1872 dma_buf_put(dmabuf); 1873 return ret; 1874 } 1875 1876 static void commit_files(struct file **files, 1877 struct kfd_criu_bo_bucket *bo_buckets, 1878 unsigned int count, 1879 int err) 1880 { 1881 while (count--) { 1882 struct file *file = files[count]; 1883 1884 if (!file) 1885 continue; 1886 if (err) { 1887 fput(file); 1888 put_unused_fd(bo_buckets[count].dmabuf_fd); 1889 } else { 1890 fd_install(bo_buckets[count].dmabuf_fd, file); 1891 } 1892 } 1893 } 1894 1895 static int criu_checkpoint_bos(struct kfd_process *p, 1896 uint32_t num_bos, 1897 uint8_t __user *user_bos, 1898 uint8_t __user *user_priv_data, 1899 uint64_t *priv_offset) 1900 { 1901 struct kfd_criu_bo_bucket *bo_buckets; 1902 struct kfd_criu_bo_priv_data *bo_privs; 1903 struct file **files = NULL; 1904 int ret = 0, pdd_index, bo_index = 0, id; 1905 void *mem; 1906 1907 bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL); 1908 if (!bo_buckets) 1909 return -ENOMEM; 1910 1911 bo_privs = kvzalloc(num_bos * sizeof(*bo_privs), GFP_KERNEL); 1912 if (!bo_privs) { 1913 ret = -ENOMEM; 1914 goto exit; 1915 } 1916 1917 files = kvzalloc(num_bos * sizeof(struct file *), GFP_KERNEL); 1918 if (!files) { 1919 ret = -ENOMEM; 1920 goto exit; 1921 } 1922 1923 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) { 1924 struct kfd_process_device *pdd = p->pdds[pdd_index]; 1925 struct amdgpu_bo *dumper_bo; 1926 struct kgd_mem *kgd_mem; 1927 1928 idr_for_each_entry(&pdd->alloc_idr, mem, id) { 1929 struct kfd_criu_bo_bucket *bo_bucket; 1930 struct kfd_criu_bo_priv_data *bo_priv; 1931 int i, dev_idx = 0; 1932 1933 kgd_mem = (struct kgd_mem *)mem; 1934 dumper_bo = kgd_mem->bo; 1935 1936 /* Skip checkpointing BOs that are used for Trap handler 1937 * code and state. Currently, these BOs have a VA that 1938 * is less GPUVM Base 1939 */ 1940 if (kgd_mem->va && kgd_mem->va <= pdd->gpuvm_base) 1941 continue; 1942 1943 bo_bucket = &bo_buckets[bo_index]; 1944 bo_priv = &bo_privs[bo_index]; 1945 1946 bo_bucket->gpu_id = pdd->user_gpu_id; 1947 bo_bucket->addr = (uint64_t)kgd_mem->va; 1948 bo_bucket->size = amdgpu_bo_size(dumper_bo); 1949 bo_bucket->alloc_flags = (uint32_t)kgd_mem->alloc_flags; 1950 bo_priv->idr_handle = id; 1951 1952 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 1953 ret = amdgpu_ttm_tt_get_userptr(&dumper_bo->tbo, 1954 &bo_priv->user_addr); 1955 if (ret) { 1956 pr_err("Failed to obtain user address for user-pointer bo\n"); 1957 goto exit; 1958 } 1959 } 1960 if (bo_bucket->alloc_flags 1961 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) { 1962 ret = criu_get_prime_handle(kgd_mem, 1963 bo_bucket->alloc_flags & 1964 KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0, 1965 &bo_bucket->dmabuf_fd, &files[bo_index]); 1966 if (ret) 1967 goto exit; 1968 } else { 1969 bo_bucket->dmabuf_fd = KFD_INVALID_FD; 1970 } 1971 1972 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) 1973 bo_bucket->offset = KFD_MMAP_TYPE_DOORBELL | 1974 KFD_MMAP_GPU_ID(pdd->dev->id); 1975 else if (bo_bucket->alloc_flags & 1976 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) 1977 bo_bucket->offset = KFD_MMAP_TYPE_MMIO | 1978 KFD_MMAP_GPU_ID(pdd->dev->id); 1979 else 1980 bo_bucket->offset = amdgpu_bo_mmap_offset(dumper_bo); 1981 1982 for (i = 0; i < p->n_pdds; i++) { 1983 if (amdgpu_amdkfd_bo_mapped_to_dev(p->pdds[i]->drm_priv, kgd_mem)) 1984 bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id; 1985 } 1986 1987 pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n" 1988 "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x", 1989 bo_bucket->size, 1990 bo_bucket->addr, 1991 bo_bucket->offset, 1992 bo_bucket->gpu_id, 1993 bo_bucket->alloc_flags, 1994 bo_priv->idr_handle); 1995 bo_index++; 1996 } 1997 } 1998 1999 ret = copy_to_user(user_bos, bo_buckets, num_bos * sizeof(*bo_buckets)); 2000 if (ret) { 2001 pr_err("Failed to copy BO information to user\n"); 2002 ret = -EFAULT; 2003 goto exit; 2004 } 2005 2006 ret = copy_to_user(user_priv_data + *priv_offset, bo_privs, num_bos * sizeof(*bo_privs)); 2007 if (ret) { 2008 pr_err("Failed to copy BO priv information to user\n"); 2009 ret = -EFAULT; 2010 goto exit; 2011 } 2012 2013 *priv_offset += num_bos * sizeof(*bo_privs); 2014 2015 exit: 2016 commit_files(files, bo_buckets, bo_index, ret); 2017 kvfree(files); 2018 kvfree(bo_buckets); 2019 kvfree(bo_privs); 2020 return ret; 2021 } 2022 2023 static int criu_get_process_object_info(struct kfd_process *p, 2024 uint32_t *num_devices, 2025 uint32_t *num_bos, 2026 uint32_t *num_objects, 2027 uint64_t *objs_priv_size) 2028 { 2029 uint64_t queues_priv_data_size, svm_priv_data_size, priv_size; 2030 uint32_t num_queues, num_events, num_svm_ranges; 2031 int ret; 2032 2033 *num_devices = p->n_pdds; 2034 *num_bos = get_process_num_bos(p); 2035 2036 ret = kfd_process_get_queue_info(p, &num_queues, &queues_priv_data_size); 2037 if (ret) 2038 return ret; 2039 2040 num_events = kfd_get_num_events(p); 2041 2042 svm_range_get_info(p, &num_svm_ranges, &svm_priv_data_size); 2043 2044 *num_objects = num_queues + num_events + num_svm_ranges; 2045 2046 if (objs_priv_size) { 2047 priv_size = sizeof(struct kfd_criu_process_priv_data); 2048 priv_size += *num_devices * sizeof(struct kfd_criu_device_priv_data); 2049 priv_size += *num_bos * sizeof(struct kfd_criu_bo_priv_data); 2050 priv_size += queues_priv_data_size; 2051 priv_size += num_events * sizeof(struct kfd_criu_event_priv_data); 2052 priv_size += svm_priv_data_size; 2053 *objs_priv_size = priv_size; 2054 } 2055 return 0; 2056 } 2057 2058 static int criu_checkpoint(struct file *filep, 2059 struct kfd_process *p, 2060 struct kfd_ioctl_criu_args *args) 2061 { 2062 int ret; 2063 uint32_t num_devices, num_bos, num_objects; 2064 uint64_t priv_size, priv_offset = 0, bo_priv_offset; 2065 2066 if (!args->devices || !args->bos || !args->priv_data) 2067 return -EINVAL; 2068 2069 mutex_lock(&p->mutex); 2070 2071 if (!p->n_pdds) { 2072 pr_err("No pdd for given process\n"); 2073 ret = -ENODEV; 2074 goto exit_unlock; 2075 } 2076 2077 /* Confirm all process queues are evicted */ 2078 if (!p->queues_paused) { 2079 pr_err("Cannot dump process when queues are not in evicted state\n"); 2080 /* CRIU plugin did not call op PROCESS_INFO before checkpointing */ 2081 ret = -EINVAL; 2082 goto exit_unlock; 2083 } 2084 2085 ret = criu_get_process_object_info(p, &num_devices, &num_bos, &num_objects, &priv_size); 2086 if (ret) 2087 goto exit_unlock; 2088 2089 if (num_devices != args->num_devices || 2090 num_bos != args->num_bos || 2091 num_objects != args->num_objects || 2092 priv_size != args->priv_data_size) { 2093 2094 ret = -EINVAL; 2095 goto exit_unlock; 2096 } 2097 2098 /* each function will store private data inside priv_data and adjust priv_offset */ 2099 ret = criu_checkpoint_process(p, (uint8_t __user *)args->priv_data, &priv_offset); 2100 if (ret) 2101 goto exit_unlock; 2102 2103 ret = criu_checkpoint_devices(p, num_devices, (uint8_t __user *)args->devices, 2104 (uint8_t __user *)args->priv_data, &priv_offset); 2105 if (ret) 2106 goto exit_unlock; 2107 2108 /* Leave room for BOs in the private data. They need to be restored 2109 * before events, but we checkpoint them last to simplify the error 2110 * handling. 2111 */ 2112 bo_priv_offset = priv_offset; 2113 priv_offset += num_bos * sizeof(struct kfd_criu_bo_priv_data); 2114 2115 if (num_objects) { 2116 ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data, 2117 &priv_offset); 2118 if (ret) 2119 goto exit_unlock; 2120 2121 ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data, 2122 &priv_offset); 2123 if (ret) 2124 goto exit_unlock; 2125 2126 ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset); 2127 if (ret) 2128 goto exit_unlock; 2129 } 2130 2131 /* This must be the last thing in this function that can fail. 2132 * Otherwise we leak dmabuf file descriptors. 2133 */ 2134 ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos, 2135 (uint8_t __user *)args->priv_data, &bo_priv_offset); 2136 2137 exit_unlock: 2138 mutex_unlock(&p->mutex); 2139 if (ret) 2140 pr_err("Failed to dump CRIU ret:%d\n", ret); 2141 else 2142 pr_debug("CRIU dump ret:%d\n", ret); 2143 2144 return ret; 2145 } 2146 2147 static int criu_restore_process(struct kfd_process *p, 2148 struct kfd_ioctl_criu_args *args, 2149 uint64_t *priv_offset, 2150 uint64_t max_priv_data_size) 2151 { 2152 int ret = 0; 2153 struct kfd_criu_process_priv_data process_priv; 2154 2155 if (*priv_offset + sizeof(process_priv) > max_priv_data_size) 2156 return -EINVAL; 2157 2158 ret = copy_from_user(&process_priv, 2159 (void __user *)(args->priv_data + *priv_offset), 2160 sizeof(process_priv)); 2161 if (ret) { 2162 pr_err("Failed to copy process private information from user\n"); 2163 ret = -EFAULT; 2164 goto exit; 2165 } 2166 *priv_offset += sizeof(process_priv); 2167 2168 if (process_priv.version != KFD_CRIU_PRIV_VERSION) { 2169 pr_err("Invalid CRIU API version (checkpointed:%d current:%d)\n", 2170 process_priv.version, KFD_CRIU_PRIV_VERSION); 2171 return -EINVAL; 2172 } 2173 2174 pr_debug("Setting XNACK mode\n"); 2175 if (process_priv.xnack_mode && !kfd_process_xnack_mode(p, true)) { 2176 pr_err("xnack mode cannot be set\n"); 2177 ret = -EPERM; 2178 goto exit; 2179 } else { 2180 pr_debug("set xnack mode: %d\n", process_priv.xnack_mode); 2181 p->xnack_enabled = process_priv.xnack_mode; 2182 } 2183 2184 exit: 2185 return ret; 2186 } 2187 2188 static int criu_restore_devices(struct kfd_process *p, 2189 struct kfd_ioctl_criu_args *args, 2190 uint64_t *priv_offset, 2191 uint64_t max_priv_data_size) 2192 { 2193 struct kfd_criu_device_bucket *device_buckets; 2194 struct kfd_criu_device_priv_data *device_privs; 2195 int ret = 0; 2196 uint32_t i; 2197 2198 if (args->num_devices != p->n_pdds) 2199 return -EINVAL; 2200 2201 if (*priv_offset + (args->num_devices * sizeof(*device_privs)) > max_priv_data_size) 2202 return -EINVAL; 2203 2204 device_buckets = kmalloc_array(args->num_devices, sizeof(*device_buckets), GFP_KERNEL); 2205 if (!device_buckets) 2206 return -ENOMEM; 2207 2208 ret = copy_from_user(device_buckets, (void __user *)args->devices, 2209 args->num_devices * sizeof(*device_buckets)); 2210 if (ret) { 2211 pr_err("Failed to copy devices buckets from user\n"); 2212 ret = -EFAULT; 2213 goto exit; 2214 } 2215 2216 for (i = 0; i < args->num_devices; i++) { 2217 struct kfd_node *dev; 2218 struct kfd_process_device *pdd; 2219 struct file *drm_file; 2220 2221 /* device private data is not currently used */ 2222 2223 if (!device_buckets[i].user_gpu_id) { 2224 pr_err("Invalid user gpu_id\n"); 2225 ret = -EINVAL; 2226 goto exit; 2227 } 2228 2229 dev = kfd_device_by_id(device_buckets[i].actual_gpu_id); 2230 if (!dev) { 2231 pr_err("Failed to find device with gpu_id = %x\n", 2232 device_buckets[i].actual_gpu_id); 2233 ret = -EINVAL; 2234 goto exit; 2235 } 2236 2237 pdd = kfd_get_process_device_data(dev, p); 2238 if (!pdd) { 2239 pr_err("Failed to get pdd for gpu_id = %x\n", 2240 device_buckets[i].actual_gpu_id); 2241 ret = -EINVAL; 2242 goto exit; 2243 } 2244 pdd->user_gpu_id = device_buckets[i].user_gpu_id; 2245 2246 drm_file = fget(device_buckets[i].drm_fd); 2247 if (!drm_file) { 2248 pr_err("Invalid render node file descriptor sent from plugin (%d)\n", 2249 device_buckets[i].drm_fd); 2250 ret = -EINVAL; 2251 goto exit; 2252 } 2253 2254 if (pdd->drm_file) { 2255 ret = -EINVAL; 2256 goto exit; 2257 } 2258 2259 /* create the vm using render nodes for kfd pdd */ 2260 if (kfd_process_device_init_vm(pdd, drm_file)) { 2261 pr_err("could not init vm for given pdd\n"); 2262 /* On success, the PDD keeps the drm_file reference */ 2263 fput(drm_file); 2264 ret = -EINVAL; 2265 goto exit; 2266 } 2267 /* 2268 * pdd now already has the vm bound to render node so below api won't create a new 2269 * exclusive kfd mapping but use existing one with renderDXXX but is still needed 2270 * for iommu v2 binding and runtime pm. 2271 */ 2272 pdd = kfd_bind_process_to_device(dev, p); 2273 if (IS_ERR(pdd)) { 2274 ret = PTR_ERR(pdd); 2275 goto exit; 2276 } 2277 2278 if (!pdd->qpd.proc_doorbells) { 2279 ret = kfd_alloc_process_doorbells(dev->kfd, pdd); 2280 if (ret) 2281 goto exit; 2282 } 2283 } 2284 2285 /* 2286 * We are not copying device private data from user as we are not using the data for now, 2287 * but we still adjust for its private data. 2288 */ 2289 *priv_offset += args->num_devices * sizeof(*device_privs); 2290 2291 exit: 2292 kfree(device_buckets); 2293 return ret; 2294 } 2295 2296 static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, 2297 struct kfd_criu_bo_bucket *bo_bucket, 2298 struct kfd_criu_bo_priv_data *bo_priv, 2299 struct kgd_mem **kgd_mem) 2300 { 2301 int idr_handle; 2302 int ret; 2303 const bool criu_resume = true; 2304 u64 offset; 2305 2306 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { 2307 if (bo_bucket->size != 2308 kfd_doorbell_process_slice(pdd->dev->kfd)) 2309 return -EINVAL; 2310 2311 offset = kfd_get_process_doorbells(pdd); 2312 if (!offset) 2313 return -ENOMEM; 2314 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 2315 /* MMIO BOs need remapped bus address */ 2316 if (bo_bucket->size != PAGE_SIZE) { 2317 pr_err("Invalid page size\n"); 2318 return -EINVAL; 2319 } 2320 offset = pdd->dev->adev->rmmio_remap.bus_addr; 2321 if (!offset || (PAGE_SIZE > 4096)) { 2322 pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n"); 2323 return -ENOMEM; 2324 } 2325 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 2326 offset = bo_priv->user_addr; 2327 } 2328 /* Create the BO */ 2329 ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr, 2330 bo_bucket->size, pdd->drm_priv, kgd_mem, 2331 &offset, bo_bucket->alloc_flags, criu_resume); 2332 if (ret) { 2333 pr_err("Could not create the BO\n"); 2334 return ret; 2335 } 2336 pr_debug("New BO created: size:0x%llx addr:0x%llx offset:0x%llx\n", 2337 bo_bucket->size, bo_bucket->addr, offset); 2338 2339 /* Restore previous IDR handle */ 2340 pr_debug("Restoring old IDR handle for the BO"); 2341 idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle, 2342 bo_priv->idr_handle + 1, GFP_KERNEL); 2343 2344 if (idr_handle < 0) { 2345 pr_err("Could not allocate idr\n"); 2346 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv, 2347 NULL); 2348 return -ENOMEM; 2349 } 2350 2351 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) 2352 bo_bucket->restored_offset = KFD_MMAP_TYPE_DOORBELL | KFD_MMAP_GPU_ID(pdd->dev->id); 2353 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) { 2354 bo_bucket->restored_offset = KFD_MMAP_TYPE_MMIO | KFD_MMAP_GPU_ID(pdd->dev->id); 2355 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 2356 bo_bucket->restored_offset = offset; 2357 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 2358 bo_bucket->restored_offset = offset; 2359 /* Update the VRAM usage count */ 2360 atomic64_add(bo_bucket->size, &pdd->vram_usage); 2361 } 2362 return 0; 2363 } 2364 2365 static int criu_restore_bo(struct kfd_process *p, 2366 struct kfd_criu_bo_bucket *bo_bucket, 2367 struct kfd_criu_bo_priv_data *bo_priv, 2368 struct file **file) 2369 { 2370 struct kfd_process_device *pdd; 2371 struct kgd_mem *kgd_mem; 2372 int ret; 2373 int j; 2374 2375 pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n", 2376 bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags, 2377 bo_priv->idr_handle); 2378 2379 pdd = kfd_process_device_data_by_id(p, bo_bucket->gpu_id); 2380 if (!pdd) { 2381 pr_err("Failed to get pdd\n"); 2382 return -ENODEV; 2383 } 2384 2385 ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem); 2386 if (ret) 2387 return ret; 2388 2389 /* now map these BOs to GPU/s */ 2390 for (j = 0; j < p->n_pdds; j++) { 2391 struct kfd_node *peer; 2392 struct kfd_process_device *peer_pdd; 2393 2394 if (!bo_priv->mapped_gpuids[j]) 2395 break; 2396 2397 peer_pdd = kfd_process_device_data_by_id(p, bo_priv->mapped_gpuids[j]); 2398 if (!peer_pdd) 2399 return -EINVAL; 2400 2401 peer = peer_pdd->dev; 2402 2403 peer_pdd = kfd_bind_process_to_device(peer, p); 2404 if (IS_ERR(peer_pdd)) 2405 return PTR_ERR(peer_pdd); 2406 2407 ret = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(peer->adev, kgd_mem, 2408 peer_pdd->drm_priv); 2409 if (ret) { 2410 pr_err("Failed to map to gpu %d/%d\n", j, p->n_pdds); 2411 return ret; 2412 } 2413 } 2414 2415 pr_debug("map memory was successful for the BO\n"); 2416 /* create the dmabuf object and export the bo */ 2417 if (bo_bucket->alloc_flags 2418 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) { 2419 ret = criu_get_prime_handle(kgd_mem, DRM_RDWR, 2420 &bo_bucket->dmabuf_fd, file); 2421 if (ret) 2422 return ret; 2423 } else { 2424 bo_bucket->dmabuf_fd = KFD_INVALID_FD; 2425 } 2426 2427 return 0; 2428 } 2429 2430 static int criu_restore_bos(struct kfd_process *p, 2431 struct kfd_ioctl_criu_args *args, 2432 uint64_t *priv_offset, 2433 uint64_t max_priv_data_size) 2434 { 2435 struct kfd_criu_bo_bucket *bo_buckets = NULL; 2436 struct kfd_criu_bo_priv_data *bo_privs = NULL; 2437 struct file **files = NULL; 2438 int ret = 0; 2439 uint32_t i = 0; 2440 2441 if (*priv_offset + (args->num_bos * sizeof(*bo_privs)) > max_priv_data_size) 2442 return -EINVAL; 2443 2444 /* Prevent MMU notifications until stage-4 IOCTL (CRIU_RESUME) is received */ 2445 amdgpu_amdkfd_block_mmu_notifications(p->kgd_process_info); 2446 2447 bo_buckets = kvmalloc_array(args->num_bos, sizeof(*bo_buckets), GFP_KERNEL); 2448 if (!bo_buckets) 2449 return -ENOMEM; 2450 2451 files = kvzalloc(args->num_bos * sizeof(struct file *), GFP_KERNEL); 2452 if (!files) { 2453 ret = -ENOMEM; 2454 goto exit; 2455 } 2456 2457 ret = copy_from_user(bo_buckets, (void __user *)args->bos, 2458 args->num_bos * sizeof(*bo_buckets)); 2459 if (ret) { 2460 pr_err("Failed to copy BOs information from user\n"); 2461 ret = -EFAULT; 2462 goto exit; 2463 } 2464 2465 bo_privs = kvmalloc_array(args->num_bos, sizeof(*bo_privs), GFP_KERNEL); 2466 if (!bo_privs) { 2467 ret = -ENOMEM; 2468 goto exit; 2469 } 2470 2471 ret = copy_from_user(bo_privs, (void __user *)args->priv_data + *priv_offset, 2472 args->num_bos * sizeof(*bo_privs)); 2473 if (ret) { 2474 pr_err("Failed to copy BOs information from user\n"); 2475 ret = -EFAULT; 2476 goto exit; 2477 } 2478 *priv_offset += args->num_bos * sizeof(*bo_privs); 2479 2480 /* Create and map new BOs */ 2481 for (; i < args->num_bos; i++) { 2482 ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i], &files[i]); 2483 if (ret) { 2484 pr_debug("Failed to restore BO[%d] ret%d\n", i, ret); 2485 goto exit; 2486 } 2487 } /* done */ 2488 2489 /* Copy only the buckets back so user can read bo_buckets[N].restored_offset */ 2490 ret = copy_to_user((void __user *)args->bos, 2491 bo_buckets, 2492 (args->num_bos * sizeof(*bo_buckets))); 2493 if (ret) 2494 ret = -EFAULT; 2495 2496 exit: 2497 commit_files(files, bo_buckets, i, ret); 2498 kvfree(files); 2499 kvfree(bo_buckets); 2500 kvfree(bo_privs); 2501 return ret; 2502 } 2503 2504 static int criu_restore_objects(struct file *filep, 2505 struct kfd_process *p, 2506 struct kfd_ioctl_criu_args *args, 2507 uint64_t *priv_offset, 2508 uint64_t max_priv_data_size) 2509 { 2510 int ret = 0; 2511 uint32_t i; 2512 2513 BUILD_BUG_ON(offsetof(struct kfd_criu_queue_priv_data, object_type)); 2514 BUILD_BUG_ON(offsetof(struct kfd_criu_event_priv_data, object_type)); 2515 BUILD_BUG_ON(offsetof(struct kfd_criu_svm_range_priv_data, object_type)); 2516 2517 for (i = 0; i < args->num_objects; i++) { 2518 uint32_t object_type; 2519 2520 if (*priv_offset + sizeof(object_type) > max_priv_data_size) { 2521 pr_err("Invalid private data size\n"); 2522 return -EINVAL; 2523 } 2524 2525 ret = get_user(object_type, (uint32_t __user *)(args->priv_data + *priv_offset)); 2526 if (ret) { 2527 pr_err("Failed to copy private information from user\n"); 2528 goto exit; 2529 } 2530 2531 switch (object_type) { 2532 case KFD_CRIU_OBJECT_TYPE_QUEUE: 2533 ret = kfd_criu_restore_queue(p, (uint8_t __user *)args->priv_data, 2534 priv_offset, max_priv_data_size); 2535 if (ret) 2536 goto exit; 2537 break; 2538 case KFD_CRIU_OBJECT_TYPE_EVENT: 2539 ret = kfd_criu_restore_event(filep, p, (uint8_t __user *)args->priv_data, 2540 priv_offset, max_priv_data_size); 2541 if (ret) 2542 goto exit; 2543 break; 2544 case KFD_CRIU_OBJECT_TYPE_SVM_RANGE: 2545 ret = kfd_criu_restore_svm(p, (uint8_t __user *)args->priv_data, 2546 priv_offset, max_priv_data_size); 2547 if (ret) 2548 goto exit; 2549 break; 2550 default: 2551 pr_err("Invalid object type:%u at index:%d\n", object_type, i); 2552 ret = -EINVAL; 2553 goto exit; 2554 } 2555 } 2556 exit: 2557 return ret; 2558 } 2559 2560 static int criu_restore(struct file *filep, 2561 struct kfd_process *p, 2562 struct kfd_ioctl_criu_args *args) 2563 { 2564 uint64_t priv_offset = 0; 2565 int ret = 0; 2566 2567 pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n", 2568 args->num_devices, args->num_bos, args->num_objects, args->priv_data_size); 2569 2570 if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size || 2571 !args->num_devices || !args->num_bos) 2572 return -EINVAL; 2573 2574 mutex_lock(&p->mutex); 2575 2576 /* 2577 * Set the process to evicted state to avoid running any new queues before all the memory 2578 * mappings are ready. 2579 */ 2580 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE); 2581 if (ret) 2582 goto exit_unlock; 2583 2584 /* Each function will adjust priv_offset based on how many bytes they consumed */ 2585 ret = criu_restore_process(p, args, &priv_offset, args->priv_data_size); 2586 if (ret) 2587 goto exit_unlock; 2588 2589 ret = criu_restore_devices(p, args, &priv_offset, args->priv_data_size); 2590 if (ret) 2591 goto exit_unlock; 2592 2593 ret = criu_restore_bos(p, args, &priv_offset, args->priv_data_size); 2594 if (ret) 2595 goto exit_unlock; 2596 2597 ret = criu_restore_objects(filep, p, args, &priv_offset, args->priv_data_size); 2598 if (ret) 2599 goto exit_unlock; 2600 2601 if (priv_offset != args->priv_data_size) { 2602 pr_err("Invalid private data size\n"); 2603 ret = -EINVAL; 2604 } 2605 2606 exit_unlock: 2607 mutex_unlock(&p->mutex); 2608 if (ret) 2609 pr_err("Failed to restore CRIU ret:%d\n", ret); 2610 else 2611 pr_debug("CRIU restore successful\n"); 2612 2613 return ret; 2614 } 2615 2616 static int criu_unpause(struct file *filep, 2617 struct kfd_process *p, 2618 struct kfd_ioctl_criu_args *args) 2619 { 2620 int ret; 2621 2622 mutex_lock(&p->mutex); 2623 2624 if (!p->queues_paused) { 2625 mutex_unlock(&p->mutex); 2626 return -EINVAL; 2627 } 2628 2629 ret = kfd_process_restore_queues(p); 2630 if (ret) 2631 pr_err("Failed to unpause queues ret:%d\n", ret); 2632 else 2633 p->queues_paused = false; 2634 2635 mutex_unlock(&p->mutex); 2636 2637 return ret; 2638 } 2639 2640 static int criu_resume(struct file *filep, 2641 struct kfd_process *p, 2642 struct kfd_ioctl_criu_args *args) 2643 { 2644 struct kfd_process *target = NULL; 2645 struct pid *pid = NULL; 2646 int ret = 0; 2647 2648 pr_debug("Inside %s, target pid for criu restore: %d\n", __func__, 2649 args->pid); 2650 2651 pid = find_get_pid(args->pid); 2652 if (!pid) { 2653 pr_err("Cannot find pid info for %i\n", args->pid); 2654 return -ESRCH; 2655 } 2656 2657 pr_debug("calling kfd_lookup_process_by_pid\n"); 2658 target = kfd_lookup_process_by_pid(pid); 2659 2660 put_pid(pid); 2661 2662 if (!target) { 2663 pr_debug("Cannot find process info for %i\n", args->pid); 2664 return -ESRCH; 2665 } 2666 2667 mutex_lock(&target->mutex); 2668 ret = kfd_criu_resume_svm(target); 2669 if (ret) { 2670 pr_err("kfd_criu_resume_svm failed for %i\n", args->pid); 2671 goto exit; 2672 } 2673 2674 ret = amdgpu_amdkfd_criu_resume(target->kgd_process_info); 2675 if (ret) 2676 pr_err("amdgpu_amdkfd_criu_resume failed for %i\n", args->pid); 2677 2678 exit: 2679 mutex_unlock(&target->mutex); 2680 2681 kfd_unref_process(target); 2682 return ret; 2683 } 2684 2685 static int criu_process_info(struct file *filep, 2686 struct kfd_process *p, 2687 struct kfd_ioctl_criu_args *args) 2688 { 2689 int ret = 0; 2690 2691 mutex_lock(&p->mutex); 2692 2693 if (!p->n_pdds) { 2694 pr_err("No pdd for given process\n"); 2695 ret = -ENODEV; 2696 goto err_unlock; 2697 } 2698 2699 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT); 2700 if (ret) 2701 goto err_unlock; 2702 2703 p->queues_paused = true; 2704 2705 args->pid = task_pid_nr_ns(p->lead_thread, 2706 task_active_pid_ns(p->lead_thread)); 2707 2708 ret = criu_get_process_object_info(p, &args->num_devices, &args->num_bos, 2709 &args->num_objects, &args->priv_data_size); 2710 if (ret) 2711 goto err_unlock; 2712 2713 dev_dbg(kfd_device, "Num of devices:%u bos:%u objects:%u priv_data_size:%lld\n", 2714 args->num_devices, args->num_bos, args->num_objects, 2715 args->priv_data_size); 2716 2717 err_unlock: 2718 if (ret) { 2719 kfd_process_restore_queues(p); 2720 p->queues_paused = false; 2721 } 2722 mutex_unlock(&p->mutex); 2723 return ret; 2724 } 2725 2726 static int kfd_ioctl_criu(struct file *filep, struct kfd_process *p, void *data) 2727 { 2728 struct kfd_ioctl_criu_args *args = data; 2729 int ret; 2730 2731 dev_dbg(kfd_device, "CRIU operation: %d\n", args->op); 2732 switch (args->op) { 2733 case KFD_CRIU_OP_PROCESS_INFO: 2734 ret = criu_process_info(filep, p, args); 2735 break; 2736 case KFD_CRIU_OP_CHECKPOINT: 2737 ret = criu_checkpoint(filep, p, args); 2738 break; 2739 case KFD_CRIU_OP_UNPAUSE: 2740 ret = criu_unpause(filep, p, args); 2741 break; 2742 case KFD_CRIU_OP_RESTORE: 2743 ret = criu_restore(filep, p, args); 2744 break; 2745 case KFD_CRIU_OP_RESUME: 2746 ret = criu_resume(filep, p, args); 2747 break; 2748 default: 2749 dev_dbg(kfd_device, "Unsupported CRIU operation:%d\n", args->op); 2750 ret = -EINVAL; 2751 break; 2752 } 2753 2754 if (ret) 2755 dev_dbg(kfd_device, "CRIU operation:%d err:%d\n", args->op, ret); 2756 2757 return ret; 2758 } 2759 2760 static int runtime_enable(struct kfd_process *p, uint64_t r_debug, 2761 bool enable_ttmp_setup) 2762 { 2763 int i = 0, ret = 0; 2764 2765 if (p->is_runtime_retry) 2766 goto retry; 2767 2768 if (p->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_DISABLED) 2769 return -EBUSY; 2770 2771 for (i = 0; i < p->n_pdds; i++) { 2772 struct kfd_process_device *pdd = p->pdds[i]; 2773 2774 if (pdd->qpd.queue_count) 2775 return -EEXIST; 2776 2777 /* 2778 * Setup TTMPs by default. 2779 * Note that this call must remain here for MES ADD QUEUE to 2780 * skip_process_ctx_clear unconditionally as the first call to 2781 * SET_SHADER_DEBUGGER clears any stale process context data 2782 * saved in MES. 2783 */ 2784 if (pdd->dev->kfd->shared_resources.enable_mes) 2785 kfd_dbg_set_mes_debug_mode(pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev)); 2786 } 2787 2788 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED; 2789 p->runtime_info.r_debug = r_debug; 2790 p->runtime_info.ttmp_setup = enable_ttmp_setup; 2791 2792 if (p->runtime_info.ttmp_setup) { 2793 for (i = 0; i < p->n_pdds; i++) { 2794 struct kfd_process_device *pdd = p->pdds[i]; 2795 2796 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) { 2797 amdgpu_gfx_off_ctrl(pdd->dev->adev, false); 2798 pdd->dev->kfd2kgd->enable_debug_trap( 2799 pdd->dev->adev, 2800 true, 2801 pdd->dev->vm_info.last_vmid_kfd); 2802 } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { 2803 pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap( 2804 pdd->dev->adev, 2805 false, 2806 0); 2807 } 2808 } 2809 } 2810 2811 retry: 2812 if (p->debug_trap_enabled) { 2813 if (!p->is_runtime_retry) { 2814 kfd_dbg_trap_activate(p); 2815 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME), 2816 p, NULL, 0, false, NULL, 0); 2817 } 2818 2819 mutex_unlock(&p->mutex); 2820 ret = down_interruptible(&p->runtime_enable_sema); 2821 mutex_lock(&p->mutex); 2822 2823 p->is_runtime_retry = !!ret; 2824 } 2825 2826 return ret; 2827 } 2828 2829 static int runtime_disable(struct kfd_process *p) 2830 { 2831 int i = 0, ret; 2832 bool was_enabled = p->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED; 2833 2834 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_DISABLED; 2835 p->runtime_info.r_debug = 0; 2836 2837 if (p->debug_trap_enabled) { 2838 if (was_enabled) 2839 kfd_dbg_trap_deactivate(p, false, 0); 2840 2841 if (!p->is_runtime_retry) 2842 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME), 2843 p, NULL, 0, false, NULL, 0); 2844 2845 mutex_unlock(&p->mutex); 2846 ret = down_interruptible(&p->runtime_enable_sema); 2847 mutex_lock(&p->mutex); 2848 2849 p->is_runtime_retry = !!ret; 2850 if (ret) 2851 return ret; 2852 } 2853 2854 if (was_enabled && p->runtime_info.ttmp_setup) { 2855 for (i = 0; i < p->n_pdds; i++) { 2856 struct kfd_process_device *pdd = p->pdds[i]; 2857 2858 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) 2859 amdgpu_gfx_off_ctrl(pdd->dev->adev, true); 2860 } 2861 } 2862 2863 p->runtime_info.ttmp_setup = false; 2864 2865 /* disable ttmp setup */ 2866 for (i = 0; i < p->n_pdds; i++) { 2867 struct kfd_process_device *pdd = p->pdds[i]; 2868 2869 if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { 2870 pdd->spi_dbg_override = 2871 pdd->dev->kfd2kgd->disable_debug_trap( 2872 pdd->dev->adev, 2873 false, 2874 pdd->dev->vm_info.last_vmid_kfd); 2875 2876 if (!pdd->dev->kfd->shared_resources.enable_mes) 2877 debug_refresh_runlist(pdd->dev->dqm); 2878 else 2879 kfd_dbg_set_mes_debug_mode(pdd, 2880 !kfd_dbg_has_cwsr_workaround(pdd->dev)); 2881 } 2882 } 2883 2884 return 0; 2885 } 2886 2887 static int kfd_ioctl_runtime_enable(struct file *filep, struct kfd_process *p, void *data) 2888 { 2889 struct kfd_ioctl_runtime_enable_args *args = data; 2890 int r; 2891 2892 mutex_lock(&p->mutex); 2893 2894 if (args->mode_mask & KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK) 2895 r = runtime_enable(p, args->r_debug, 2896 !!(args->mode_mask & KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK)); 2897 else 2898 r = runtime_disable(p); 2899 2900 mutex_unlock(&p->mutex); 2901 2902 return r; 2903 } 2904 2905 static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, void *data) 2906 { 2907 struct kfd_ioctl_dbg_trap_args *args = data; 2908 struct task_struct *thread = NULL; 2909 struct mm_struct *mm = NULL; 2910 struct pid *pid = NULL; 2911 struct kfd_process *target = NULL; 2912 struct kfd_process_device *pdd = NULL; 2913 int r = 0; 2914 2915 if (sched_policy == KFD_SCHED_POLICY_NO_HWS) { 2916 pr_err("Debugging does not support sched_policy %i", sched_policy); 2917 return -EINVAL; 2918 } 2919 2920 pid = find_get_pid(args->pid); 2921 if (!pid) { 2922 pr_debug("Cannot find pid info for %i\n", args->pid); 2923 r = -ESRCH; 2924 goto out; 2925 } 2926 2927 thread = get_pid_task(pid, PIDTYPE_PID); 2928 if (!thread) { 2929 r = -ESRCH; 2930 goto out; 2931 } 2932 2933 mm = get_task_mm(thread); 2934 if (!mm) { 2935 r = -ESRCH; 2936 goto out; 2937 } 2938 2939 if (args->op == KFD_IOC_DBG_TRAP_ENABLE) { 2940 bool create_process; 2941 2942 rcu_read_lock(); 2943 create_process = thread && thread != current && ptrace_parent(thread) == current; 2944 rcu_read_unlock(); 2945 2946 target = create_process ? kfd_create_process(thread) : 2947 kfd_lookup_process_by_pid(pid); 2948 } else { 2949 target = kfd_lookup_process_by_pid(pid); 2950 } 2951 2952 if (IS_ERR_OR_NULL(target)) { 2953 pr_debug("Cannot find process PID %i to debug\n", args->pid); 2954 r = target ? PTR_ERR(target) : -ESRCH; 2955 target = NULL; 2956 goto out; 2957 } 2958 2959 /* Check if target is still PTRACED. */ 2960 rcu_read_lock(); 2961 if (target != p && args->op != KFD_IOC_DBG_TRAP_DISABLE 2962 && ptrace_parent(target->lead_thread) != current) { 2963 pr_err("PID %i is not PTRACED and cannot be debugged\n", args->pid); 2964 r = -EPERM; 2965 } 2966 rcu_read_unlock(); 2967 2968 if (r) 2969 goto out; 2970 2971 mutex_lock(&target->mutex); 2972 2973 if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !target->debug_trap_enabled) { 2974 pr_err("PID %i not debug enabled for op %i\n", args->pid, args->op); 2975 r = -EINVAL; 2976 goto unlock_out; 2977 } 2978 2979 if (target->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_ENABLED && 2980 (args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE || 2981 args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE || 2982 args->op == KFD_IOC_DBG_TRAP_SUSPEND_QUEUES || 2983 args->op == KFD_IOC_DBG_TRAP_RESUME_QUEUES || 2984 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH || 2985 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH || 2986 args->op == KFD_IOC_DBG_TRAP_SET_FLAGS)) { 2987 r = -EPERM; 2988 goto unlock_out; 2989 } 2990 2991 if (args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH || 2992 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH) { 2993 int user_gpu_id = kfd_process_get_user_gpu_id(target, 2994 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ? 2995 args->set_node_address_watch.gpu_id : 2996 args->clear_node_address_watch.gpu_id); 2997 2998 pdd = kfd_process_device_data_by_id(target, user_gpu_id); 2999 if (user_gpu_id == -EINVAL || !pdd) { 3000 r = -ENODEV; 3001 goto unlock_out; 3002 } 3003 } 3004 3005 switch (args->op) { 3006 case KFD_IOC_DBG_TRAP_ENABLE: 3007 if (target != p) 3008 target->debugger_process = p; 3009 3010 r = kfd_dbg_trap_enable(target, 3011 args->enable.dbg_fd, 3012 (void __user *)args->enable.rinfo_ptr, 3013 &args->enable.rinfo_size); 3014 if (!r) 3015 target->exception_enable_mask = args->enable.exception_mask; 3016 3017 break; 3018 case KFD_IOC_DBG_TRAP_DISABLE: 3019 r = kfd_dbg_trap_disable(target); 3020 break; 3021 case KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT: 3022 r = kfd_dbg_send_exception_to_runtime(target, 3023 args->send_runtime_event.gpu_id, 3024 args->send_runtime_event.queue_id, 3025 args->send_runtime_event.exception_mask); 3026 break; 3027 case KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED: 3028 kfd_dbg_set_enabled_debug_exception_mask(target, 3029 args->set_exceptions_enabled.exception_mask); 3030 break; 3031 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE: 3032 r = kfd_dbg_trap_set_wave_launch_override(target, 3033 args->launch_override.override_mode, 3034 args->launch_override.enable_mask, 3035 args->launch_override.support_request_mask, 3036 &args->launch_override.enable_mask, 3037 &args->launch_override.support_request_mask); 3038 break; 3039 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE: 3040 r = kfd_dbg_trap_set_wave_launch_mode(target, 3041 args->launch_mode.launch_mode); 3042 break; 3043 case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES: 3044 r = suspend_queues(target, 3045 args->suspend_queues.num_queues, 3046 args->suspend_queues.grace_period, 3047 args->suspend_queues.exception_mask, 3048 (uint32_t *)args->suspend_queues.queue_array_ptr); 3049 3050 break; 3051 case KFD_IOC_DBG_TRAP_RESUME_QUEUES: 3052 r = resume_queues(target, args->resume_queues.num_queues, 3053 (uint32_t *)args->resume_queues.queue_array_ptr); 3054 break; 3055 case KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH: 3056 r = kfd_dbg_trap_set_dev_address_watch(pdd, 3057 args->set_node_address_watch.address, 3058 args->set_node_address_watch.mask, 3059 &args->set_node_address_watch.id, 3060 args->set_node_address_watch.mode); 3061 break; 3062 case KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH: 3063 r = kfd_dbg_trap_clear_dev_address_watch(pdd, 3064 args->clear_node_address_watch.id); 3065 break; 3066 case KFD_IOC_DBG_TRAP_SET_FLAGS: 3067 r = kfd_dbg_trap_set_flags(target, &args->set_flags.flags); 3068 break; 3069 case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT: 3070 r = kfd_dbg_ev_query_debug_event(target, 3071 &args->query_debug_event.queue_id, 3072 &args->query_debug_event.gpu_id, 3073 args->query_debug_event.exception_mask, 3074 &args->query_debug_event.exception_mask); 3075 break; 3076 case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO: 3077 r = kfd_dbg_trap_query_exception_info(target, 3078 args->query_exception_info.source_id, 3079 args->query_exception_info.exception_code, 3080 args->query_exception_info.clear_exception, 3081 (void __user *)args->query_exception_info.info_ptr, 3082 &args->query_exception_info.info_size); 3083 break; 3084 case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT: 3085 r = pqm_get_queue_snapshot(&target->pqm, 3086 args->queue_snapshot.exception_mask, 3087 (void __user *)args->queue_snapshot.snapshot_buf_ptr, 3088 &args->queue_snapshot.num_queues, 3089 &args->queue_snapshot.entry_size); 3090 break; 3091 case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT: 3092 r = kfd_dbg_trap_device_snapshot(target, 3093 args->device_snapshot.exception_mask, 3094 (void __user *)args->device_snapshot.snapshot_buf_ptr, 3095 &args->device_snapshot.num_devices, 3096 &args->device_snapshot.entry_size); 3097 break; 3098 default: 3099 pr_err("Invalid option: %i\n", args->op); 3100 r = -EINVAL; 3101 } 3102 3103 unlock_out: 3104 mutex_unlock(&target->mutex); 3105 3106 out: 3107 if (thread) 3108 put_task_struct(thread); 3109 3110 if (mm) 3111 mmput(mm); 3112 3113 if (pid) 3114 put_pid(pid); 3115 3116 if (target) 3117 kfd_unref_process(target); 3118 3119 return r; 3120 } 3121 3122 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ 3123 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ 3124 .cmd_drv = 0, .name = #ioctl} 3125 3126 /** Ioctl table */ 3127 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { 3128 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION, 3129 kfd_ioctl_get_version, 0), 3130 3131 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE, 3132 kfd_ioctl_create_queue, 0), 3133 3134 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE, 3135 kfd_ioctl_destroy_queue, 0), 3136 3137 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY, 3138 kfd_ioctl_set_memory_policy, 0), 3139 3140 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS, 3141 kfd_ioctl_get_clock_counters, 0), 3142 3143 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES, 3144 kfd_ioctl_get_process_apertures, 0), 3145 3146 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE, 3147 kfd_ioctl_update_queue, 0), 3148 3149 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT, 3150 kfd_ioctl_create_event, 0), 3151 3152 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT, 3153 kfd_ioctl_destroy_event, 0), 3154 3155 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT, 3156 kfd_ioctl_set_event, 0), 3157 3158 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT, 3159 kfd_ioctl_reset_event, 0), 3160 3161 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS, 3162 kfd_ioctl_wait_events, 0), 3163 3164 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER_DEPRECATED, 3165 kfd_ioctl_dbg_register, 0), 3166 3167 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED, 3168 kfd_ioctl_dbg_unregister, 0), 3169 3170 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED, 3171 kfd_ioctl_dbg_address_watch, 0), 3172 3173 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED, 3174 kfd_ioctl_dbg_wave_control, 0), 3175 3176 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA, 3177 kfd_ioctl_set_scratch_backing_va, 0), 3178 3179 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG, 3180 kfd_ioctl_get_tile_config, 0), 3181 3182 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER, 3183 kfd_ioctl_set_trap_handler, 0), 3184 3185 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW, 3186 kfd_ioctl_get_process_apertures_new, 0), 3187 3188 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM, 3189 kfd_ioctl_acquire_vm, 0), 3190 3191 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU, 3192 kfd_ioctl_alloc_memory_of_gpu, 0), 3193 3194 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU, 3195 kfd_ioctl_free_memory_of_gpu, 0), 3196 3197 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU, 3198 kfd_ioctl_map_memory_to_gpu, 0), 3199 3200 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU, 3201 kfd_ioctl_unmap_memory_from_gpu, 0), 3202 3203 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK, 3204 kfd_ioctl_set_cu_mask, 0), 3205 3206 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE, 3207 kfd_ioctl_get_queue_wave_state, 0), 3208 3209 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO, 3210 kfd_ioctl_get_dmabuf_info, 0), 3211 3212 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF, 3213 kfd_ioctl_import_dmabuf, 0), 3214 3215 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS, 3216 kfd_ioctl_alloc_queue_gws, 0), 3217 3218 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS, 3219 kfd_ioctl_smi_events, 0), 3220 3221 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0), 3222 3223 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE, 3224 kfd_ioctl_set_xnack_mode, 0), 3225 3226 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP, 3227 kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE), 3228 3229 AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY, 3230 kfd_ioctl_get_available_memory, 0), 3231 3232 AMDKFD_IOCTL_DEF(AMDKFD_IOC_EXPORT_DMABUF, 3233 kfd_ioctl_export_dmabuf, 0), 3234 3235 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RUNTIME_ENABLE, 3236 kfd_ioctl_runtime_enable, 0), 3237 3238 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP, 3239 kfd_ioctl_set_debug_trap, 0), 3240 }; 3241 3242 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) 3243 3244 static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) 3245 { 3246 struct kfd_process *process; 3247 amdkfd_ioctl_t *func; 3248 const struct amdkfd_ioctl_desc *ioctl = NULL; 3249 unsigned int nr = _IOC_NR(cmd); 3250 char stack_kdata[128]; 3251 char *kdata = NULL; 3252 unsigned int usize, asize; 3253 int retcode = -EINVAL; 3254 bool ptrace_attached = false; 3255 3256 if (nr >= AMDKFD_CORE_IOCTL_COUNT) 3257 goto err_i1; 3258 3259 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) { 3260 u32 amdkfd_size; 3261 3262 ioctl = &amdkfd_ioctls[nr]; 3263 3264 amdkfd_size = _IOC_SIZE(ioctl->cmd); 3265 usize = asize = _IOC_SIZE(cmd); 3266 if (amdkfd_size > asize) 3267 asize = amdkfd_size; 3268 3269 cmd = ioctl->cmd; 3270 } else 3271 goto err_i1; 3272 3273 dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg); 3274 3275 /* Get the process struct from the filep. Only the process 3276 * that opened /dev/kfd can use the file descriptor. Child 3277 * processes need to create their own KFD device context. 3278 */ 3279 process = filep->private_data; 3280 3281 rcu_read_lock(); 3282 if ((ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE) && 3283 ptrace_parent(process->lead_thread) == current) 3284 ptrace_attached = true; 3285 rcu_read_unlock(); 3286 3287 if (process->lead_thread != current->group_leader 3288 && !ptrace_attached) { 3289 dev_dbg(kfd_device, "Using KFD FD in wrong process\n"); 3290 retcode = -EBADF; 3291 goto err_i1; 3292 } 3293 3294 /* Do not trust userspace, use our own definition */ 3295 func = ioctl->func; 3296 3297 if (unlikely(!func)) { 3298 dev_dbg(kfd_device, "no function\n"); 3299 retcode = -EINVAL; 3300 goto err_i1; 3301 } 3302 3303 /* 3304 * Versions of docker shipped in Ubuntu 18.xx and 20.xx do not support 3305 * CAP_CHECKPOINT_RESTORE, so we also allow access if CAP_SYS_ADMIN as CAP_SYS_ADMIN is a 3306 * more priviledged access. 3307 */ 3308 if (unlikely(ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE)) { 3309 if (!capable(CAP_CHECKPOINT_RESTORE) && 3310 !capable(CAP_SYS_ADMIN)) { 3311 retcode = -EACCES; 3312 goto err_i1; 3313 } 3314 } 3315 3316 if (cmd & (IOC_IN | IOC_OUT)) { 3317 if (asize <= sizeof(stack_kdata)) { 3318 kdata = stack_kdata; 3319 } else { 3320 kdata = kmalloc(asize, GFP_KERNEL); 3321 if (!kdata) { 3322 retcode = -ENOMEM; 3323 goto err_i1; 3324 } 3325 } 3326 if (asize > usize) 3327 memset(kdata + usize, 0, asize - usize); 3328 } 3329 3330 if (cmd & IOC_IN) { 3331 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) { 3332 retcode = -EFAULT; 3333 goto err_i1; 3334 } 3335 } else if (cmd & IOC_OUT) { 3336 memset(kdata, 0, usize); 3337 } 3338 3339 retcode = func(filep, process, kdata); 3340 3341 if (cmd & IOC_OUT) 3342 if (copy_to_user((void __user *)arg, kdata, usize) != 0) 3343 retcode = -EFAULT; 3344 3345 err_i1: 3346 if (!ioctl) 3347 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n", 3348 task_pid_nr(current), cmd, nr); 3349 3350 if (kdata != stack_kdata) 3351 kfree(kdata); 3352 3353 if (retcode) 3354 dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n", 3355 nr, arg, retcode); 3356 3357 return retcode; 3358 } 3359 3360 static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process, 3361 struct vm_area_struct *vma) 3362 { 3363 phys_addr_t address; 3364 3365 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 3366 return -EINVAL; 3367 3368 if (PAGE_SIZE > 4096) 3369 return -EINVAL; 3370 3371 address = dev->adev->rmmio_remap.bus_addr; 3372 3373 vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE | 3374 VM_DONTDUMP | VM_PFNMAP); 3375 3376 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 3377 3378 pr_debug("process pid %d mapping mmio page\n" 3379 " target user address == 0x%08llX\n" 3380 " physical address == 0x%08llX\n" 3381 " vm_flags == 0x%04lX\n" 3382 " size == 0x%04lX\n", 3383 process->lead_thread->pid, (unsigned long long) vma->vm_start, 3384 address, vma->vm_flags, PAGE_SIZE); 3385 3386 return io_remap_pfn_range(vma, 3387 vma->vm_start, 3388 address >> PAGE_SHIFT, 3389 PAGE_SIZE, 3390 vma->vm_page_prot); 3391 } 3392 3393 3394 static int kfd_mmap(struct file *filp, struct vm_area_struct *vma) 3395 { 3396 struct kfd_process *process; 3397 struct kfd_node *dev = NULL; 3398 unsigned long mmap_offset; 3399 unsigned int gpu_id; 3400 3401 process = kfd_get_process(current); 3402 if (IS_ERR(process)) 3403 return PTR_ERR(process); 3404 3405 mmap_offset = vma->vm_pgoff << PAGE_SHIFT; 3406 gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset); 3407 if (gpu_id) 3408 dev = kfd_device_by_id(gpu_id); 3409 3410 switch (mmap_offset & KFD_MMAP_TYPE_MASK) { 3411 case KFD_MMAP_TYPE_DOORBELL: 3412 if (!dev) 3413 return -ENODEV; 3414 return kfd_doorbell_mmap(dev, process, vma); 3415 3416 case KFD_MMAP_TYPE_EVENTS: 3417 return kfd_event_mmap(process, vma); 3418 3419 case KFD_MMAP_TYPE_RESERVED_MEM: 3420 if (!dev) 3421 return -ENODEV; 3422 return kfd_reserved_mem_mmap(dev, process, vma); 3423 case KFD_MMAP_TYPE_MMIO: 3424 if (!dev) 3425 return -ENODEV; 3426 return kfd_mmio_mmap(dev, process, vma); 3427 } 3428 3429 return -EFAULT; 3430 } 3431