1b889ef4aSJames Zhu /* 2b889ef4aSJames Zhu * Copyright 2022 Advanced Micro Devices, Inc. 3b889ef4aSJames Zhu * 4b889ef4aSJames Zhu * Permission is hereby granted, free of charge, to any person obtaining a 5b889ef4aSJames Zhu * copy of this software and associated documentation files (the "Software"), 6b889ef4aSJames Zhu * to deal in the Software without restriction, including without limitation 7b889ef4aSJames Zhu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8b889ef4aSJames Zhu * and/or sell copies of the Software, and to permit persons to whom the 9b889ef4aSJames Zhu * Software is furnished to do so, subject to the following conditions: 10b889ef4aSJames Zhu * 11b889ef4aSJames Zhu * The above copyright notice and this permission notice shall be included in 12b889ef4aSJames Zhu * all copies or substantial portions of the Software. 13b889ef4aSJames Zhu * 14b889ef4aSJames Zhu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15b889ef4aSJames Zhu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16b889ef4aSJames Zhu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17b889ef4aSJames Zhu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18b889ef4aSJames Zhu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19b889ef4aSJames Zhu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20b889ef4aSJames Zhu * OTHER DEALINGS IN THE SOFTWARE. 21b889ef4aSJames Zhu * 22b889ef4aSJames Zhu */ 23b889ef4aSJames Zhu 24b889ef4aSJames Zhu #ifndef __VCN_V4_0_3_H__ 25b889ef4aSJames Zhu #define __VCN_V4_0_3_H__ 26b889ef4aSJames Zhu 27*4c4a8914SStanley.Yang enum amdgpu_vcn_v4_0_3_sub_block { 28*4c4a8914SStanley.Yang AMDGPU_VCN_V4_0_3_VCPU_VCODEC = 0, 29*4c4a8914SStanley.Yang 30*4c4a8914SStanley.Yang AMDGPU_VCN_V4_0_3_MAX_SUB_BLOCK, 31*4c4a8914SStanley.Yang }; 32*4c4a8914SStanley.Yang 33b889ef4aSJames Zhu extern const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block; 34b889ef4aSJames Zhu 350b9647d4SLijo Lazar void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 360b9647d4SLijo Lazar uint32_t val, uint32_t mask); 370b9647d4SLijo Lazar 380b9647d4SLijo Lazar void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 390b9647d4SLijo Lazar uint32_t val); 400b9647d4SLijo Lazar void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 410b9647d4SLijo Lazar unsigned int vmid, uint64_t pd_addr); 420b9647d4SLijo Lazar void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring); 430b9647d4SLijo Lazar 44b889ef4aSJames Zhu #endif /* __VCN_V4_0_3_H__ */ 45