1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "vcn_v2_0.h" 32 #include "mmsch_v3_0.h" 33 #include "vcn_sw_ring.h" 34 35 #include "vcn/vcn_3_0_0_offset.h" 36 #include "vcn/vcn_3_0_0_sh_mask.h" 37 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 38 39 #include <drm/drm_drv.h> 40 41 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 42 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 43 44 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 45 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 46 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 47 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 48 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 49 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 50 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 51 52 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 54 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 55 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 56 57 #define VCN_INSTANCES_SIENNA_CICHLID 2 58 #define DEC_SW_RING_ENABLED FALSE 59 60 #define RDECODE_MSG_CREATE 0x00000000 61 #define RDECODE_MESSAGE_CREATE 0x00000001 62 63 static const struct amdgpu_hwip_reg_entry vcn_reg_list_3_0[] = { 64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), 65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), 66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID), 67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2), 68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0), 69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1), 70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD), 71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI), 72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO), 73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2), 74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2), 75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3), 76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3), 77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4), 78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4), 79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), 80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR), 81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2), 82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2), 83 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3), 84 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3), 85 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4), 86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4), 87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE), 88 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2), 89 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3), 90 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4), 91 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG), 92 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS), 93 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL), 94 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA), 95 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK), 96 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE) 97 }; 98 99 static int amdgpu_ih_clientid_vcns[] = { 100 SOC15_IH_CLIENTID_VCN, 101 SOC15_IH_CLIENTID_VCN1 102 }; 103 104 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 105 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 106 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 107 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 108 static int vcn_v3_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 109 enum amd_powergating_state state); 110 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 111 struct dpg_pause_state *new_state); 112 113 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 114 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 115 116 /** 117 * vcn_v3_0_early_init - set function pointers and load microcode 118 * 119 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 120 * 121 * Set ring and irq function pointers 122 * Load microcode from filesystem 123 */ 124 static int vcn_v3_0_early_init(struct amdgpu_ip_block *ip_block) 125 { 126 struct amdgpu_device *adev = ip_block->adev; 127 int i, r; 128 129 if (amdgpu_sriov_vf(adev)) { 130 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 131 adev->vcn.harvest_config = 0; 132 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 133 adev->vcn.inst[i].num_enc_rings = 1; 134 135 } else { 136 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 137 AMDGPU_VCN_HARVEST_VCN1)) 138 /* both instances are harvested, disable the block */ 139 return -ENOENT; 140 141 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 142 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 143 IP_VERSION(3, 0, 33)) 144 adev->vcn.inst[i].num_enc_rings = 0; 145 else 146 adev->vcn.inst[i].num_enc_rings = 2; 147 } 148 } 149 150 vcn_v3_0_set_dec_ring_funcs(adev); 151 vcn_v3_0_set_enc_ring_funcs(adev); 152 vcn_v3_0_set_irq_funcs(adev); 153 154 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 155 adev->vcn.inst[i].set_pg_state = vcn_v3_0_set_pg_state; 156 157 r = amdgpu_vcn_early_init(adev, i); 158 if (r) 159 return r; 160 } 161 return 0; 162 } 163 164 /** 165 * vcn_v3_0_sw_init - sw init for VCN block 166 * 167 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 168 * 169 * Load firmware and sw initialization 170 */ 171 static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block) 172 { 173 struct amdgpu_ring *ring; 174 int i, j, r; 175 int vcn_doorbell_index = 0; 176 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0); 177 uint32_t *ptr; 178 struct amdgpu_device *adev = ip_block->adev; 179 180 /* 181 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines 182 * Formula: 183 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 184 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) 185 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j 186 */ 187 if (amdgpu_sriov_vf(adev)) { 188 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 189 /* get DWORD offset */ 190 vcn_doorbell_index = vcn_doorbell_index << 1; 191 } 192 193 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 194 volatile struct amdgpu_fw_shared *fw_shared; 195 196 if (adev->vcn.harvest_config & (1 << i)) 197 continue; 198 199 r = amdgpu_vcn_sw_init(adev, i); 200 if (r) 201 return r; 202 203 amdgpu_vcn_setup_ucode(adev, i); 204 205 r = amdgpu_vcn_resume(adev, i); 206 if (r) 207 return r; 208 209 adev->vcn.inst[i].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 210 adev->vcn.inst[i].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 211 adev->vcn.inst[i].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 212 adev->vcn.inst[i].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 213 adev->vcn.inst[i].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 214 adev->vcn.inst[i].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 215 216 adev->vcn.inst[i].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 217 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 218 adev->vcn.inst[i].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 219 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 220 adev->vcn.inst[i].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 221 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 222 adev->vcn.inst[i].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 223 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 224 adev->vcn.inst[i].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 225 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 226 227 /* VCN DEC TRAP */ 228 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 229 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 230 if (r) 231 return r; 232 233 atomic_set(&adev->vcn.inst[i].sched_score, 0); 234 235 ring = &adev->vcn.inst[i].ring_dec; 236 ring->use_doorbell = true; 237 if (amdgpu_sriov_vf(adev)) { 238 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.inst[i].num_enc_rings + 1); 239 } else { 240 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 241 } 242 ring->vm_hub = AMDGPU_MMHUB0(0); 243 sprintf(ring->name, "vcn_dec_%d", i); 244 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 245 AMDGPU_RING_PRIO_DEFAULT, 246 &adev->vcn.inst[i].sched_score); 247 if (r) 248 return r; 249 250 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) { 251 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j); 252 253 /* VCN ENC TRAP */ 254 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 255 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 256 if (r) 257 return r; 258 259 ring = &adev->vcn.inst[i].ring_enc[j]; 260 ring->use_doorbell = true; 261 if (amdgpu_sriov_vf(adev)) { 262 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.inst[i].num_enc_rings + 1) + 1 + j; 263 } else { 264 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 265 } 266 ring->vm_hub = AMDGPU_MMHUB0(0); 267 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 268 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 269 hw_prio, &adev->vcn.inst[i].sched_score); 270 if (r) 271 return r; 272 } 273 274 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 275 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) | 276 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) | 277 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB); 278 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); 279 fw_shared->present_flag_0 |= AMDGPU_VCN_SMU_VERSION_INFO_FLAG; 280 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 1, 2)) 281 fw_shared->smu_interface_info.smu_interface_type = 2; 282 else if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 283 IP_VERSION(3, 1, 1)) 284 fw_shared->smu_interface_info.smu_interface_type = 1; 285 286 if (amdgpu_vcnfw_log) 287 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 288 289 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 290 adev->vcn.inst[i].pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 291 } 292 293 if (amdgpu_sriov_vf(adev)) { 294 r = amdgpu_virt_alloc_mm_table(adev); 295 if (r) 296 return r; 297 } 298 299 /* Allocate memory for VCN IP Dump buffer */ 300 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 301 if (ptr == NULL) { 302 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 303 adev->vcn.ip_dump = NULL; 304 } else { 305 adev->vcn.ip_dump = ptr; 306 } 307 308 return 0; 309 } 310 311 /** 312 * vcn_v3_0_sw_fini - sw fini for VCN block 313 * 314 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 315 * 316 * VCN suspend and free up sw allocation 317 */ 318 static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) 319 { 320 struct amdgpu_device *adev = ip_block->adev; 321 int i, r, idx; 322 323 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 324 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 325 volatile struct amdgpu_fw_shared *fw_shared; 326 327 if (adev->vcn.harvest_config & (1 << i)) 328 continue; 329 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 330 fw_shared->present_flag_0 = 0; 331 fw_shared->sw_ring.is_enabled = false; 332 } 333 334 drm_dev_exit(idx); 335 } 336 337 if (amdgpu_sriov_vf(adev)) 338 amdgpu_virt_free_mm_table(adev); 339 340 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 341 r = amdgpu_vcn_suspend(adev, i); 342 if (r) 343 return r; 344 345 r = amdgpu_vcn_sw_fini(adev, i); 346 if (r) 347 return r; 348 } 349 350 kfree(adev->vcn.ip_dump); 351 return 0; 352 } 353 354 /** 355 * vcn_v3_0_hw_init - start and test VCN block 356 * 357 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 358 * 359 * Initialize the hardware, boot up the VCPU and do some testing 360 */ 361 static int vcn_v3_0_hw_init(struct amdgpu_ip_block *ip_block) 362 { 363 struct amdgpu_device *adev = ip_block->adev; 364 struct amdgpu_ring *ring; 365 int i, j, r; 366 367 if (amdgpu_sriov_vf(adev)) { 368 r = vcn_v3_0_start_sriov(adev); 369 if (r) 370 return r; 371 372 /* initialize VCN dec and enc ring buffers */ 373 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 374 if (adev->vcn.harvest_config & (1 << i)) 375 continue; 376 377 ring = &adev->vcn.inst[i].ring_dec; 378 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i)) { 379 ring->sched.ready = false; 380 ring->no_scheduler = true; 381 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 382 } else { 383 ring->wptr = 0; 384 ring->wptr_old = 0; 385 vcn_v3_0_dec_ring_set_wptr(ring); 386 ring->sched.ready = true; 387 } 388 389 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) { 390 ring = &adev->vcn.inst[i].ring_enc[j]; 391 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 392 ring->sched.ready = false; 393 ring->no_scheduler = true; 394 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 395 } else { 396 ring->wptr = 0; 397 ring->wptr_old = 0; 398 vcn_v3_0_enc_ring_set_wptr(ring); 399 ring->sched.ready = true; 400 } 401 } 402 } 403 } else { 404 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 405 if (adev->vcn.harvest_config & (1 << i)) 406 continue; 407 408 ring = &adev->vcn.inst[i].ring_dec; 409 410 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 411 ring->doorbell_index, i); 412 413 r = amdgpu_ring_test_helper(ring); 414 if (r) 415 return r; 416 417 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) { 418 ring = &adev->vcn.inst[i].ring_enc[j]; 419 r = amdgpu_ring_test_helper(ring); 420 if (r) 421 return r; 422 } 423 } 424 } 425 426 return 0; 427 } 428 429 /** 430 * vcn_v3_0_hw_fini - stop the hardware block 431 * 432 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 433 * 434 * Stop the VCN block, mark ring as not ready any more 435 */ 436 static int vcn_v3_0_hw_fini(struct amdgpu_ip_block *ip_block) 437 { 438 struct amdgpu_device *adev = ip_block->adev; 439 int i; 440 441 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 442 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 443 444 if (adev->vcn.harvest_config & (1 << i)) 445 continue; 446 447 cancel_delayed_work_sync(&vinst->idle_work); 448 449 if (!amdgpu_sriov_vf(adev)) { 450 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 451 (vinst->cur_state != AMD_PG_STATE_GATE && 452 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 453 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 454 } 455 } 456 } 457 458 return 0; 459 } 460 461 /** 462 * vcn_v3_0_suspend - suspend VCN block 463 * 464 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 465 * 466 * HW fini and suspend VCN block 467 */ 468 static int vcn_v3_0_suspend(struct amdgpu_ip_block *ip_block) 469 { 470 struct amdgpu_device *adev = ip_block->adev; 471 int r, i; 472 473 r = vcn_v3_0_hw_fini(ip_block); 474 if (r) 475 return r; 476 477 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 478 r = amdgpu_vcn_suspend(ip_block->adev, i); 479 if (r) 480 return r; 481 } 482 483 return 0; 484 } 485 486 /** 487 * vcn_v3_0_resume - resume VCN block 488 * 489 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 490 * 491 * Resume firmware and hw init VCN block 492 */ 493 static int vcn_v3_0_resume(struct amdgpu_ip_block *ip_block) 494 { 495 struct amdgpu_device *adev = ip_block->adev; 496 int r, i; 497 498 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 499 r = amdgpu_vcn_resume(ip_block->adev, i); 500 if (r) 501 return r; 502 } 503 504 r = vcn_v3_0_hw_init(ip_block); 505 506 return r; 507 } 508 509 /** 510 * vcn_v3_0_mc_resume - memory controller programming 511 * 512 * @vinst: VCN instance 513 * 514 * Let the VCN memory controller know it's offsets 515 */ 516 static void vcn_v3_0_mc_resume(struct amdgpu_vcn_inst *vinst) 517 { 518 struct amdgpu_device *adev = vinst->adev; 519 int inst = vinst->inst; 520 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst].fw->size + 4); 521 uint32_t offset; 522 523 /* cache window 0: fw */ 524 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 525 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 526 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 527 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 528 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 529 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 530 offset = 0; 531 } else { 532 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 533 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 534 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 535 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 536 offset = size; 537 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 538 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 539 } 540 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 541 542 /* cache window 1: stack */ 543 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 544 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 545 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 546 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 547 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 548 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 549 550 /* cache window 2: context */ 551 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 552 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 553 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 554 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 555 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 556 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 557 558 /* non-cache window */ 559 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 560 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 561 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 562 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 563 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 564 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, 565 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 566 } 567 568 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 569 bool indirect) 570 { 571 struct amdgpu_device *adev = vinst->adev; 572 int inst_idx = vinst->inst; 573 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4); 574 uint32_t offset; 575 576 /* cache window 0: fw */ 577 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 578 if (!indirect) { 579 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 580 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 581 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 582 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 583 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 584 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 585 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 586 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 587 } else { 588 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 589 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 590 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 591 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 592 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 593 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 594 } 595 offset = 0; 596 } else { 597 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 598 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 599 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 600 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 601 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 602 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 603 offset = size; 604 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 605 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 606 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 607 } 608 609 if (!indirect) 610 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 611 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 612 else 613 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 614 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 615 616 /* cache window 1: stack */ 617 if (!indirect) { 618 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 619 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 620 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 621 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 622 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 623 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 624 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 625 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 626 } else { 627 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 628 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 629 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 630 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 631 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 632 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 633 } 634 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 635 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 636 637 /* cache window 2: context */ 638 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 639 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 640 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 641 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 642 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 643 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 644 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 645 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 646 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 647 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 648 649 /* non-cache window */ 650 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 651 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 652 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 653 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 654 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 655 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 656 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 657 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 658 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 659 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 660 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 661 662 /* VCN global tiling registers */ 663 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 664 UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 665 } 666 667 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst) 668 { 669 struct amdgpu_device *adev = vinst->adev; 670 int inst = vinst->inst; 671 uint32_t data = 0; 672 673 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 674 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 675 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 676 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 677 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 678 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 679 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 680 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 681 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 682 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 683 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 684 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 685 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 686 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 687 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 688 689 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 690 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 691 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 692 } else { 693 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 694 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 695 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 696 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 697 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 698 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 699 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 700 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 701 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 702 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 703 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 704 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 705 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 706 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 707 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 708 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 709 } 710 711 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 712 data &= ~0x103; 713 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 714 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 715 UVD_POWER_STATUS__UVD_PG_EN_MASK; 716 717 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 718 } 719 720 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) 721 { 722 struct amdgpu_device *adev = vinst->adev; 723 int inst = vinst->inst; 724 uint32_t data; 725 726 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 727 /* Before power off, this indicator has to be turned on */ 728 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 729 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 730 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 731 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 732 733 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 734 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 735 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 736 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 737 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 738 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 739 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 740 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 741 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 742 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 743 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 744 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 745 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 746 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 747 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 748 749 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 750 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 751 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 752 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 753 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 754 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 755 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 756 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 757 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 758 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 759 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 760 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 761 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 762 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 763 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 764 } 765 } 766 767 /** 768 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 769 * 770 * @vinst: Pointer to the VCN instance structure 771 * 772 * Disable clock gating for VCN block 773 */ 774 static void vcn_v3_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 775 { 776 struct amdgpu_device *adev = vinst->adev; 777 int inst = vinst->inst; 778 uint32_t data; 779 780 /* VCN disable CGC */ 781 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 782 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 783 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 784 else 785 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 786 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 787 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 788 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 789 790 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 791 data &= ~(UVD_CGC_GATE__SYS_MASK 792 | UVD_CGC_GATE__UDEC_MASK 793 | UVD_CGC_GATE__MPEG2_MASK 794 | UVD_CGC_GATE__REGS_MASK 795 | UVD_CGC_GATE__RBC_MASK 796 | UVD_CGC_GATE__LMI_MC_MASK 797 | UVD_CGC_GATE__LMI_UMC_MASK 798 | UVD_CGC_GATE__IDCT_MASK 799 | UVD_CGC_GATE__MPRD_MASK 800 | UVD_CGC_GATE__MPC_MASK 801 | UVD_CGC_GATE__LBSI_MASK 802 | UVD_CGC_GATE__LRBBM_MASK 803 | UVD_CGC_GATE__UDEC_RE_MASK 804 | UVD_CGC_GATE__UDEC_CM_MASK 805 | UVD_CGC_GATE__UDEC_IT_MASK 806 | UVD_CGC_GATE__UDEC_DB_MASK 807 | UVD_CGC_GATE__UDEC_MP_MASK 808 | UVD_CGC_GATE__WCB_MASK 809 | UVD_CGC_GATE__VCPU_MASK 810 | UVD_CGC_GATE__MMSCH_MASK); 811 812 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 813 814 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 815 816 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 817 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 818 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 819 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 820 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 821 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 822 | UVD_CGC_CTRL__SYS_MODE_MASK 823 | UVD_CGC_CTRL__UDEC_MODE_MASK 824 | UVD_CGC_CTRL__MPEG2_MODE_MASK 825 | UVD_CGC_CTRL__REGS_MODE_MASK 826 | UVD_CGC_CTRL__RBC_MODE_MASK 827 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 828 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 829 | UVD_CGC_CTRL__IDCT_MODE_MASK 830 | UVD_CGC_CTRL__MPRD_MODE_MASK 831 | UVD_CGC_CTRL__MPC_MODE_MASK 832 | UVD_CGC_CTRL__LBSI_MODE_MASK 833 | UVD_CGC_CTRL__LRBBM_MODE_MASK 834 | UVD_CGC_CTRL__WCB_MODE_MASK 835 | UVD_CGC_CTRL__VCPU_MODE_MASK 836 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 837 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 838 839 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 840 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 841 | UVD_SUVD_CGC_GATE__SIT_MASK 842 | UVD_SUVD_CGC_GATE__SMP_MASK 843 | UVD_SUVD_CGC_GATE__SCM_MASK 844 | UVD_SUVD_CGC_GATE__SDB_MASK 845 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 846 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 847 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 848 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 849 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 850 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 851 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 852 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 853 | UVD_SUVD_CGC_GATE__SCLR_MASK 854 | UVD_SUVD_CGC_GATE__ENT_MASK 855 | UVD_SUVD_CGC_GATE__IME_MASK 856 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 857 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 858 | UVD_SUVD_CGC_GATE__SITE_MASK 859 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 860 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 861 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 862 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 863 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 864 | UVD_SUVD_CGC_GATE__EFC_MASK 865 | UVD_SUVD_CGC_GATE__SAOE_MASK 866 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 867 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 868 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 869 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 870 | UVD_SUVD_CGC_GATE__SMPA_MASK); 871 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 872 873 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 874 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 875 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 876 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 877 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 878 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 879 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 880 881 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 882 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 883 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 884 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 885 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 886 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 887 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 888 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 889 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 890 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 891 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 892 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 893 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 894 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 895 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 896 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 897 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 898 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 899 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 900 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 901 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 902 } 903 904 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 905 uint8_t sram_sel, 906 uint8_t indirect) 907 { 908 struct amdgpu_device *adev = vinst->adev; 909 int inst_idx = vinst->inst; 910 uint32_t reg_data = 0; 911 912 /* enable sw clock gating control */ 913 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 914 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 915 else 916 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 917 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 918 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 919 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 920 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 921 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 922 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 923 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 924 UVD_CGC_CTRL__SYS_MODE_MASK | 925 UVD_CGC_CTRL__UDEC_MODE_MASK | 926 UVD_CGC_CTRL__MPEG2_MODE_MASK | 927 UVD_CGC_CTRL__REGS_MODE_MASK | 928 UVD_CGC_CTRL__RBC_MODE_MASK | 929 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 930 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 931 UVD_CGC_CTRL__IDCT_MODE_MASK | 932 UVD_CGC_CTRL__MPRD_MODE_MASK | 933 UVD_CGC_CTRL__MPC_MODE_MASK | 934 UVD_CGC_CTRL__LBSI_MODE_MASK | 935 UVD_CGC_CTRL__LRBBM_MODE_MASK | 936 UVD_CGC_CTRL__WCB_MODE_MASK | 937 UVD_CGC_CTRL__VCPU_MODE_MASK | 938 UVD_CGC_CTRL__MMSCH_MODE_MASK); 939 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 940 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 941 942 /* turn off clock gating */ 943 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 944 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 945 946 /* turn on SUVD clock gating */ 947 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 948 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 949 950 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 951 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 952 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 953 } 954 955 /** 956 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 957 * 958 * @vinst: Pointer to the VCN instance structure 959 * 960 * Enable clock gating for VCN block 961 */ 962 static void vcn_v3_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 963 { 964 struct amdgpu_device *adev = vinst->adev; 965 int inst = vinst->inst; 966 uint32_t data; 967 968 /* enable VCN CGC */ 969 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 970 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 971 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 972 else 973 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 974 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 975 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 976 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 977 978 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 979 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 980 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 981 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 982 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 983 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 984 | UVD_CGC_CTRL__SYS_MODE_MASK 985 | UVD_CGC_CTRL__UDEC_MODE_MASK 986 | UVD_CGC_CTRL__MPEG2_MODE_MASK 987 | UVD_CGC_CTRL__REGS_MODE_MASK 988 | UVD_CGC_CTRL__RBC_MODE_MASK 989 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 990 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 991 | UVD_CGC_CTRL__IDCT_MODE_MASK 992 | UVD_CGC_CTRL__MPRD_MODE_MASK 993 | UVD_CGC_CTRL__MPC_MODE_MASK 994 | UVD_CGC_CTRL__LBSI_MODE_MASK 995 | UVD_CGC_CTRL__LRBBM_MODE_MASK 996 | UVD_CGC_CTRL__WCB_MODE_MASK 997 | UVD_CGC_CTRL__VCPU_MODE_MASK 998 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 999 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 1000 1001 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 1002 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 1003 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 1004 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 1005 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 1006 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 1007 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 1008 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 1009 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 1010 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 1011 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 1012 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 1013 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 1014 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 1015 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 1016 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 1017 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 1018 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 1019 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 1020 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 1021 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 1022 } 1023 1024 static int vcn_v3_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) 1025 { 1026 struct amdgpu_device *adev = vinst->adev; 1027 int inst_idx = vinst->inst; 1028 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1029 struct amdgpu_ring *ring; 1030 uint32_t rb_bufsz, tmp; 1031 1032 /* disable register anti-hang mechanism */ 1033 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 1034 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1035 /* enable dynamic power gating mode */ 1036 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 1037 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 1038 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 1039 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 1040 1041 if (indirect) 1042 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 1043 1044 /* enable clock gating */ 1045 vcn_v3_0_clock_gating_dpg_mode(vinst, 0, indirect); 1046 1047 /* enable VCPU clock */ 1048 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1049 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1050 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 1051 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1052 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1053 1054 /* disable master interupt */ 1055 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1056 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 1057 1058 /* setup mmUVD_LMI_CTRL */ 1059 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1060 UVD_LMI_CTRL__REQ_MODE_MASK | 1061 UVD_LMI_CTRL__CRC_RESET_MASK | 1062 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1063 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1064 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1065 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1066 0x00100000L); 1067 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1068 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 1069 1070 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1071 VCN, inst_idx, mmUVD_MPC_CNTL), 1072 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 1073 1074 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1075 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 1076 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1077 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1078 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1079 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 1080 1081 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1082 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 1083 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1084 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1085 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1086 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 1087 1088 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1089 VCN, inst_idx, mmUVD_MPC_SET_MUX), 1090 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1091 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1092 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1093 1094 vcn_v3_0_mc_resume_dpg_mode(vinst, indirect); 1095 1096 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1097 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1098 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1099 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1100 1101 /* enable LMI MC and UMC channels */ 1102 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1103 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 1104 1105 /* unblock VCPU register access */ 1106 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1107 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 1108 1109 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1110 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1111 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1112 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1113 1114 /* enable master interrupt */ 1115 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1116 VCN, inst_idx, mmUVD_MASTINT_EN), 1117 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1118 1119 /* add nop to workaround PSP size check */ 1120 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1121 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1122 1123 if (indirect) 1124 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 1125 1126 ring = &adev->vcn.inst[inst_idx].ring_dec; 1127 /* force RBC into idle state */ 1128 rb_bufsz = order_base_2(ring->ring_size); 1129 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1130 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1131 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1132 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1133 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1134 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1135 1136 /* Stall DPG before WPTR/RPTR reset */ 1137 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1138 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1139 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1140 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1141 1142 /* set the write pointer delay */ 1143 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1144 1145 /* set the wb address */ 1146 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1147 (upper_32_bits(ring->gpu_addr) >> 2)); 1148 1149 /* programm the RB_BASE for ring buffer */ 1150 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1151 lower_32_bits(ring->gpu_addr)); 1152 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1153 upper_32_bits(ring->gpu_addr)); 1154 1155 /* Initialize the ring buffer's read and write pointers */ 1156 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1157 1158 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1159 1160 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1161 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1162 lower_32_bits(ring->wptr)); 1163 1164 /* Reset FW shared memory RBC WPTR/RPTR */ 1165 fw_shared->rb.rptr = 0; 1166 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1167 1168 /*resetting done, fw can check RB ring */ 1169 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1170 1171 /* Unstall DPG */ 1172 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1173 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1174 1175 return 0; 1176 } 1177 1178 static int vcn_v3_0_start(struct amdgpu_vcn_inst *vinst) 1179 { 1180 struct amdgpu_device *adev = vinst->adev; 1181 int i = vinst->inst; 1182 volatile struct amdgpu_fw_shared *fw_shared; 1183 struct amdgpu_ring *ring; 1184 uint32_t rb_bufsz, tmp; 1185 int j, k, r; 1186 1187 if (adev->vcn.harvest_config & (1 << i)) 1188 return 0; 1189 1190 if (adev->pm.dpm_enabled) 1191 amdgpu_dpm_enable_vcn(adev, true, i); 1192 1193 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1194 return vcn_v3_0_start_dpg_mode(vinst, vinst->indirect_sram); 1195 1196 /* disable VCN power gating */ 1197 vcn_v3_0_disable_static_power_gating(vinst); 1198 1199 /* set VCN status busy */ 1200 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1201 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1202 1203 /* SW clock gating */ 1204 vcn_v3_0_disable_clock_gating(vinst); 1205 1206 /* enable VCPU clock */ 1207 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1208 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1209 1210 /* disable master interrupt */ 1211 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1212 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1213 1214 /* enable LMI MC and UMC channels */ 1215 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1216 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1217 1218 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1219 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1220 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1221 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1222 1223 /* setup mmUVD_LMI_CTRL */ 1224 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1225 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1226 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1227 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1228 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1229 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1230 1231 /* setup mmUVD_MPC_CNTL */ 1232 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1233 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1234 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1235 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1236 1237 /* setup UVD_MPC_SET_MUXA0 */ 1238 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1239 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1240 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1241 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1242 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1243 1244 /* setup UVD_MPC_SET_MUXB0 */ 1245 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1246 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1247 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1248 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1249 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1250 1251 /* setup mmUVD_MPC_SET_MUX */ 1252 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1253 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1254 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1255 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1256 1257 vcn_v3_0_mc_resume(vinst); 1258 1259 /* VCN global tiling registers */ 1260 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1261 adev->gfx.config.gb_addr_config); 1262 1263 /* unblock VCPU register access */ 1264 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1265 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1266 1267 /* release VCPU reset to boot */ 1268 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1269 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1270 1271 for (j = 0; j < 10; ++j) { 1272 uint32_t status; 1273 1274 for (k = 0; k < 100; ++k) { 1275 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1276 if (status & 2) 1277 break; 1278 mdelay(10); 1279 } 1280 r = 0; 1281 if (status & 2) 1282 break; 1283 1284 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1285 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1286 UVD_VCPU_CNTL__BLK_RST_MASK, 1287 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1288 mdelay(10); 1289 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1290 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1291 1292 mdelay(10); 1293 r = -1; 1294 } 1295 1296 if (r) { 1297 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1298 return r; 1299 } 1300 1301 /* enable master interrupt */ 1302 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1303 UVD_MASTINT_EN__VCPU_EN_MASK, 1304 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1305 1306 /* clear the busy bit of VCN_STATUS */ 1307 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1308 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1309 1310 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1311 1312 ring = &adev->vcn.inst[i].ring_dec; 1313 /* force RBC into idle state */ 1314 rb_bufsz = order_base_2(ring->ring_size); 1315 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1316 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1317 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1318 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1319 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1320 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1321 1322 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1323 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1324 1325 /* programm the RB_BASE for ring buffer */ 1326 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1327 lower_32_bits(ring->gpu_addr)); 1328 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1329 upper_32_bits(ring->gpu_addr)); 1330 1331 /* Initialize the ring buffer's read and write pointers */ 1332 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1333 1334 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); 1335 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1336 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1337 lower_32_bits(ring->wptr)); 1338 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1339 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1340 1341 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != 1342 IP_VERSION(3, 0, 33)) { 1343 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1344 ring = &adev->vcn.inst[i].ring_enc[0]; 1345 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1346 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1347 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1348 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1349 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1350 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1351 1352 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1353 ring = &adev->vcn.inst[i].ring_enc[1]; 1354 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1355 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1356 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1357 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1358 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1359 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1360 } 1361 1362 return 0; 1363 } 1364 1365 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1366 { 1367 int i, j; 1368 struct amdgpu_ring *ring; 1369 uint64_t cache_addr; 1370 uint64_t rb_addr; 1371 uint64_t ctx_addr; 1372 uint32_t param, resp, expected; 1373 uint32_t offset, cache_size; 1374 uint32_t tmp, timeout; 1375 1376 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1377 uint32_t *table_loc; 1378 uint32_t table_size; 1379 uint32_t size, size_dw; 1380 1381 struct mmsch_v3_0_cmd_direct_write 1382 direct_wt = { {0} }; 1383 struct mmsch_v3_0_cmd_direct_read_modify_write 1384 direct_rd_mod_wt = { {0} }; 1385 struct mmsch_v3_0_cmd_end end = { {0} }; 1386 struct mmsch_v3_0_init_header header; 1387 1388 direct_wt.cmd_header.command_type = 1389 MMSCH_COMMAND__DIRECT_REG_WRITE; 1390 direct_rd_mod_wt.cmd_header.command_type = 1391 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1392 end.cmd_header.command_type = 1393 MMSCH_COMMAND__END; 1394 1395 header.version = MMSCH_VERSION; 1396 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1397 for (i = 0; i < MMSCH_V3_0_VCN_INSTANCES; i++) { 1398 header.inst[i].init_status = 0; 1399 header.inst[i].table_offset = 0; 1400 header.inst[i].table_size = 0; 1401 } 1402 1403 table_loc = (uint32_t *)table->cpu_addr; 1404 table_loc += header.total_size; 1405 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1406 if (adev->vcn.harvest_config & (1 << i)) 1407 continue; 1408 1409 table_size = 0; 1410 1411 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1412 mmUVD_STATUS), 1413 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1414 1415 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 1416 1417 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1418 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1419 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1420 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1421 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1422 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1423 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1424 offset = 0; 1425 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1426 mmUVD_VCPU_CACHE_OFFSET0), 1427 0); 1428 } else { 1429 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1430 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1431 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1432 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1433 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1434 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1435 offset = cache_size; 1436 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1437 mmUVD_VCPU_CACHE_OFFSET0), 1438 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1439 } 1440 1441 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1442 mmUVD_VCPU_CACHE_SIZE0), 1443 cache_size); 1444 1445 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1446 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1447 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1448 lower_32_bits(cache_addr)); 1449 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1450 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1451 upper_32_bits(cache_addr)); 1452 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1453 mmUVD_VCPU_CACHE_OFFSET1), 1454 0); 1455 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1456 mmUVD_VCPU_CACHE_SIZE1), 1457 AMDGPU_VCN_STACK_SIZE); 1458 1459 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1460 AMDGPU_VCN_STACK_SIZE; 1461 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1462 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1463 lower_32_bits(cache_addr)); 1464 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1465 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1466 upper_32_bits(cache_addr)); 1467 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1468 mmUVD_VCPU_CACHE_OFFSET2), 1469 0); 1470 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1471 mmUVD_VCPU_CACHE_SIZE2), 1472 AMDGPU_VCN_CONTEXT_SIZE); 1473 1474 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) { 1475 ring = &adev->vcn.inst[i].ring_enc[j]; 1476 ring->wptr = 0; 1477 rb_addr = ring->gpu_addr; 1478 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1479 mmUVD_RB_BASE_LO), 1480 lower_32_bits(rb_addr)); 1481 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1482 mmUVD_RB_BASE_HI), 1483 upper_32_bits(rb_addr)); 1484 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1485 mmUVD_RB_SIZE), 1486 ring->ring_size / 4); 1487 } 1488 1489 ring = &adev->vcn.inst[i].ring_dec; 1490 ring->wptr = 0; 1491 rb_addr = ring->gpu_addr; 1492 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1493 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1494 lower_32_bits(rb_addr)); 1495 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1496 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1497 upper_32_bits(rb_addr)); 1498 /* force RBC into idle state */ 1499 tmp = order_base_2(ring->ring_size); 1500 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1501 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1502 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1503 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1504 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1505 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1506 mmUVD_RBC_RB_CNTL), 1507 tmp); 1508 1509 /* add end packet */ 1510 MMSCH_V3_0_INSERT_END(); 1511 1512 /* refine header */ 1513 header.inst[i].init_status = 0; 1514 header.inst[i].table_offset = header.total_size; 1515 header.inst[i].table_size = table_size; 1516 header.total_size += table_size; 1517 } 1518 1519 /* Update init table header in memory */ 1520 size = sizeof(struct mmsch_v3_0_init_header); 1521 table_loc = (uint32_t *)table->cpu_addr; 1522 memcpy((void *)table_loc, &header, size); 1523 1524 /* message MMSCH (in VCN[0]) to initialize this client 1525 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1526 * of memory descriptor location 1527 */ 1528 ctx_addr = table->gpu_addr; 1529 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1530 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1531 1532 /* 2, update vmid of descriptor */ 1533 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1534 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1535 /* use domain0 for MM scheduler */ 1536 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1537 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1538 1539 /* 3, notify mmsch about the size of this descriptor */ 1540 size = header.total_size; 1541 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1542 1543 /* 4, set resp to zero */ 1544 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1545 1546 /* 5, kick off the initialization and wait until 1547 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1548 */ 1549 param = 0x10000001; 1550 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1551 tmp = 0; 1552 timeout = 1000; 1553 resp = 0; 1554 expected = param + 1; 1555 while (resp != expected) { 1556 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1557 if (resp == expected) 1558 break; 1559 1560 udelay(10); 1561 tmp = tmp + 10; 1562 if (tmp >= timeout) { 1563 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1564 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1565 "(expected=0x%08x, readback=0x%08x)\n", 1566 tmp, expected, resp); 1567 return -EBUSY; 1568 } 1569 } 1570 1571 return 0; 1572 } 1573 1574 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1575 { 1576 struct amdgpu_device *adev = vinst->adev; 1577 int inst_idx = vinst->inst; 1578 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1579 uint32_t tmp; 1580 1581 vcn_v3_0_pause_dpg_mode(vinst, &state); 1582 1583 /* Wait for power status to be 1 */ 1584 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1585 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1586 1587 /* wait for read ptr to be equal to write ptr */ 1588 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1589 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1590 1591 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1592 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1593 1594 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1595 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1596 1597 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1598 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1599 1600 /* disable dynamic power gating mode */ 1601 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1602 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1603 1604 return 0; 1605 } 1606 1607 static int vcn_v3_0_stop(struct amdgpu_vcn_inst *vinst) 1608 { 1609 struct amdgpu_device *adev = vinst->adev; 1610 int i = vinst->inst; 1611 uint32_t tmp; 1612 int r = 0; 1613 1614 if (adev->vcn.harvest_config & (1 << i)) 1615 return 0; 1616 1617 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1618 r = vcn_v3_0_stop_dpg_mode(vinst); 1619 goto done; 1620 } 1621 1622 /* wait for vcn idle */ 1623 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1624 if (r) 1625 goto done; 1626 1627 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1628 UVD_LMI_STATUS__READ_CLEAN_MASK | 1629 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1630 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1631 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1632 if (r) 1633 goto done; 1634 1635 /* disable LMI UMC channel */ 1636 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1637 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1638 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1639 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1640 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1641 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1642 if (r) 1643 goto done; 1644 1645 /* block VCPU register access */ 1646 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1647 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1648 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1649 1650 /* reset VCPU */ 1651 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1652 UVD_VCPU_CNTL__BLK_RST_MASK, 1653 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1654 1655 /* disable VCPU clock */ 1656 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1657 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1658 1659 /* apply soft reset */ 1660 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1661 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1662 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1663 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1664 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1665 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1666 1667 /* clear status */ 1668 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1669 1670 /* apply HW clock gating */ 1671 vcn_v3_0_enable_clock_gating(vinst); 1672 1673 /* enable VCN power gating */ 1674 vcn_v3_0_enable_static_power_gating(vinst); 1675 1676 done: 1677 if (adev->pm.dpm_enabled) 1678 amdgpu_dpm_enable_vcn(adev, false, i); 1679 1680 return r; 1681 } 1682 1683 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1684 struct dpg_pause_state *new_state) 1685 { 1686 struct amdgpu_device *adev = vinst->adev; 1687 int inst_idx = vinst->inst; 1688 volatile struct amdgpu_fw_shared *fw_shared; 1689 struct amdgpu_ring *ring; 1690 uint32_t reg_data = 0; 1691 int ret_code; 1692 1693 /* pause/unpause if state is changed */ 1694 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1695 DRM_DEBUG("dpg pause state changed %d -> %d", 1696 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1697 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1698 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1699 1700 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1701 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1702 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1703 1704 if (!ret_code) { 1705 /* pause DPG */ 1706 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1707 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1708 1709 /* wait for ACK */ 1710 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1711 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1712 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1713 1714 /* Stall DPG before WPTR/RPTR reset */ 1715 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1716 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1717 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1718 1719 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != 1720 IP_VERSION(3, 0, 33)) { 1721 /* Restore */ 1722 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1723 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1724 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1725 ring->wptr = 0; 1726 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1727 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1728 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1729 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1730 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1731 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1732 1733 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1734 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1735 ring->wptr = 0; 1736 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1737 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1738 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1739 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1740 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1741 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1742 1743 /* restore wptr/rptr with pointers saved in FW shared memory*/ 1744 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); 1745 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); 1746 } 1747 1748 /* Unstall DPG */ 1749 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1750 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1751 1752 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1753 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1754 } 1755 } else { 1756 /* unpause dpg, no need to wait */ 1757 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1758 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1759 } 1760 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1761 } 1762 1763 return 0; 1764 } 1765 1766 /** 1767 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1768 * 1769 * @ring: amdgpu_ring pointer 1770 * 1771 * Returns the current hardware read pointer 1772 */ 1773 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1774 { 1775 struct amdgpu_device *adev = ring->adev; 1776 1777 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1778 } 1779 1780 /** 1781 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1782 * 1783 * @ring: amdgpu_ring pointer 1784 * 1785 * Returns the current hardware write pointer 1786 */ 1787 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1788 { 1789 struct amdgpu_device *adev = ring->adev; 1790 1791 if (ring->use_doorbell) 1792 return *ring->wptr_cpu_addr; 1793 else 1794 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1795 } 1796 1797 /** 1798 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1799 * 1800 * @ring: amdgpu_ring pointer 1801 * 1802 * Commits the write pointer to the hardware 1803 */ 1804 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1805 { 1806 struct amdgpu_device *adev = ring->adev; 1807 volatile struct amdgpu_fw_shared *fw_shared; 1808 1809 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1810 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */ 1811 fw_shared = adev->vcn.inst[ring->me].fw_shared.cpu_addr; 1812 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1813 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, 1814 lower_32_bits(ring->wptr)); 1815 } 1816 1817 if (ring->use_doorbell) { 1818 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1819 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1820 } else { 1821 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1822 } 1823 } 1824 1825 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { 1826 .type = AMDGPU_RING_TYPE_VCN_DEC, 1827 .align_mask = 0x3f, 1828 .nop = VCN_DEC_SW_CMD_NO_OP, 1829 .secure_submission_supported = true, 1830 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1831 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1832 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1833 .emit_frame_size = 1834 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1835 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1836 VCN_SW_RING_EMIT_FRAME_SIZE, 1837 .emit_ib_size = 5, /* vcn_dec_sw_ring_emit_ib */ 1838 .emit_ib = vcn_dec_sw_ring_emit_ib, 1839 .emit_fence = vcn_dec_sw_ring_emit_fence, 1840 .emit_vm_flush = vcn_dec_sw_ring_emit_vm_flush, 1841 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring, 1842 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib, 1843 .insert_nop = amdgpu_ring_insert_nop, 1844 .insert_end = vcn_dec_sw_ring_insert_end, 1845 .pad_ib = amdgpu_ring_generic_pad_ib, 1846 .begin_use = amdgpu_vcn_ring_begin_use, 1847 .end_use = amdgpu_vcn_ring_end_use, 1848 .emit_wreg = vcn_dec_sw_ring_emit_wreg, 1849 .emit_reg_wait = vcn_dec_sw_ring_emit_reg_wait, 1850 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1851 }; 1852 1853 static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p, 1854 struct amdgpu_job *job) 1855 { 1856 struct drm_gpu_scheduler **scheds; 1857 1858 /* The create msg must be in the first IB submitted */ 1859 if (atomic_read(&job->base.entity->fence_seq)) 1860 return -EINVAL; 1861 1862 /* if VCN0 is harvested, we can't support AV1 */ 1863 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) 1864 return -EINVAL; 1865 1866 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] 1867 [AMDGPU_RING_PRIO_DEFAULT].sched; 1868 drm_sched_entity_modify_sched(job->base.entity, scheds, 1); 1869 return 0; 1870 } 1871 1872 static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, 1873 uint64_t addr) 1874 { 1875 struct ttm_operation_ctx ctx = { false, false }; 1876 struct amdgpu_bo_va_mapping *map; 1877 uint32_t *msg, num_buffers; 1878 struct amdgpu_bo *bo; 1879 uint64_t start, end; 1880 unsigned int i; 1881 void *ptr; 1882 int r; 1883 1884 addr &= AMDGPU_GMC_HOLE_MASK; 1885 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1886 if (r) { 1887 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 1888 return r; 1889 } 1890 1891 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1892 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1893 if (addr & 0x7) { 1894 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1895 return -EINVAL; 1896 } 1897 1898 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1899 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1900 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1901 if (r) { 1902 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1903 return r; 1904 } 1905 1906 r = amdgpu_bo_kmap(bo, &ptr); 1907 if (r) { 1908 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1909 return r; 1910 } 1911 1912 msg = ptr + addr - start; 1913 1914 /* Check length */ 1915 if (msg[1] > end - addr) { 1916 r = -EINVAL; 1917 goto out; 1918 } 1919 1920 if (msg[3] != RDECODE_MSG_CREATE) 1921 goto out; 1922 1923 num_buffers = msg[2]; 1924 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1925 uint32_t offset, size, *create; 1926 1927 if (msg[0] != RDECODE_MESSAGE_CREATE) 1928 continue; 1929 1930 offset = msg[1]; 1931 size = msg[2]; 1932 1933 if (offset + size > end) { 1934 r = -EINVAL; 1935 goto out; 1936 } 1937 1938 create = ptr + addr + offset - start; 1939 1940 /* H246, HEVC and VP9 can run on any instance */ 1941 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1942 continue; 1943 1944 r = vcn_v3_0_limit_sched(p, job); 1945 if (r) 1946 goto out; 1947 } 1948 1949 out: 1950 amdgpu_bo_kunmap(bo); 1951 return r; 1952 } 1953 1954 static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1955 struct amdgpu_job *job, 1956 struct amdgpu_ib *ib) 1957 { 1958 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1959 uint32_t msg_lo = 0, msg_hi = 0; 1960 unsigned i; 1961 int r; 1962 1963 /* The first instance can decode anything */ 1964 if (!ring->me) 1965 return 0; 1966 1967 for (i = 0; i < ib->length_dw; i += 2) { 1968 uint32_t reg = amdgpu_ib_get_value(ib, i); 1969 uint32_t val = amdgpu_ib_get_value(ib, i + 1); 1970 1971 if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.data0, 0)) { 1972 msg_lo = val; 1973 } else if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.data1, 0)) { 1974 msg_hi = val; 1975 } else if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.cmd, 0) && 1976 val == 0) { 1977 r = vcn_v3_0_dec_msg(p, job, 1978 ((u64)msg_hi) << 32 | msg_lo); 1979 if (r) 1980 return r; 1981 } 1982 } 1983 return 0; 1984 } 1985 1986 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 1987 .type = AMDGPU_RING_TYPE_VCN_DEC, 1988 .align_mask = 0xf, 1989 .secure_submission_supported = true, 1990 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1991 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1992 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1993 .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place, 1994 .emit_frame_size = 1995 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1996 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1997 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1998 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1999 6, 2000 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 2001 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 2002 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 2003 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 2004 .test_ring = vcn_v2_0_dec_ring_test_ring, 2005 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2006 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 2007 .insert_start = vcn_v2_0_dec_ring_insert_start, 2008 .insert_end = vcn_v2_0_dec_ring_insert_end, 2009 .pad_ib = amdgpu_ring_generic_pad_ib, 2010 .begin_use = amdgpu_vcn_ring_begin_use, 2011 .end_use = amdgpu_vcn_ring_end_use, 2012 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2013 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2014 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2015 }; 2016 2017 /** 2018 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 2019 * 2020 * @ring: amdgpu_ring pointer 2021 * 2022 * Returns the current hardware enc read pointer 2023 */ 2024 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 2025 { 2026 struct amdgpu_device *adev = ring->adev; 2027 2028 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 2029 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 2030 else 2031 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 2032 } 2033 2034 /** 2035 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 2036 * 2037 * @ring: amdgpu_ring pointer 2038 * 2039 * Returns the current hardware enc write pointer 2040 */ 2041 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 2042 { 2043 struct amdgpu_device *adev = ring->adev; 2044 2045 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2046 if (ring->use_doorbell) 2047 return *ring->wptr_cpu_addr; 2048 else 2049 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 2050 } else { 2051 if (ring->use_doorbell) 2052 return *ring->wptr_cpu_addr; 2053 else 2054 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 2055 } 2056 } 2057 2058 /** 2059 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 2060 * 2061 * @ring: amdgpu_ring pointer 2062 * 2063 * Commits the enc write pointer to the hardware 2064 */ 2065 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 2066 { 2067 struct amdgpu_device *adev = ring->adev; 2068 2069 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2070 if (ring->use_doorbell) { 2071 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 2072 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2073 } else { 2074 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 2075 } 2076 } else { 2077 if (ring->use_doorbell) { 2078 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 2079 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2080 } else { 2081 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 2082 } 2083 } 2084 } 2085 2086 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 2087 .type = AMDGPU_RING_TYPE_VCN_ENC, 2088 .align_mask = 0x3f, 2089 .nop = VCN_ENC_CMD_NO_OP, 2090 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 2091 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 2092 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 2093 .emit_frame_size = 2094 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2095 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2096 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2097 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2098 1, /* vcn_v2_0_enc_ring_insert_end */ 2099 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2100 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2101 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2102 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2103 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2104 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2105 .insert_nop = amdgpu_ring_insert_nop, 2106 .insert_end = vcn_v2_0_enc_ring_insert_end, 2107 .pad_ib = amdgpu_ring_generic_pad_ib, 2108 .begin_use = amdgpu_vcn_ring_begin_use, 2109 .end_use = amdgpu_vcn_ring_end_use, 2110 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2111 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2112 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2113 }; 2114 2115 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2116 { 2117 int i; 2118 2119 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2120 if (adev->vcn.harvest_config & (1 << i)) 2121 continue; 2122 2123 if (!DEC_SW_RING_ENABLED) 2124 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 2125 else 2126 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs; 2127 adev->vcn.inst[i].ring_dec.me = i; 2128 } 2129 } 2130 2131 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2132 { 2133 int i, j; 2134 2135 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2136 if (adev->vcn.harvest_config & (1 << i)) 2137 continue; 2138 2139 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) { 2140 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 2141 adev->vcn.inst[i].ring_enc[j].me = i; 2142 } 2143 } 2144 } 2145 2146 static bool vcn_v3_0_is_idle(struct amdgpu_ip_block *ip_block) 2147 { 2148 struct amdgpu_device *adev = ip_block->adev; 2149 int i, ret = 1; 2150 2151 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2152 if (adev->vcn.harvest_config & (1 << i)) 2153 continue; 2154 2155 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 2156 } 2157 2158 return ret; 2159 } 2160 2161 static int vcn_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 2162 { 2163 struct amdgpu_device *adev = ip_block->adev; 2164 int i, ret = 0; 2165 2166 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2167 if (adev->vcn.harvest_config & (1 << i)) 2168 continue; 2169 2170 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 2171 UVD_STATUS__IDLE); 2172 if (ret) 2173 return ret; 2174 } 2175 2176 return ret; 2177 } 2178 2179 static int vcn_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2180 enum amd_clockgating_state state) 2181 { 2182 struct amdgpu_device *adev = ip_block->adev; 2183 bool enable = state == AMD_CG_STATE_GATE; 2184 int i; 2185 2186 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2187 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 2188 if (adev->vcn.harvest_config & (1 << i)) 2189 continue; 2190 2191 if (enable) { 2192 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 2193 return -EBUSY; 2194 vcn_v3_0_enable_clock_gating(vinst); 2195 } else { 2196 vcn_v3_0_disable_clock_gating(vinst); 2197 } 2198 } 2199 2200 return 0; 2201 } 2202 2203 static int vcn_v3_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 2204 enum amd_powergating_state state) 2205 { 2206 struct amdgpu_device *adev = vinst->adev; 2207 int ret = 0; 2208 2209 /* for SRIOV, guest should not control VCN Power-gating 2210 * MMSCH FW should control Power-gating and clock-gating 2211 * guest should avoid touching CGC and PG 2212 */ 2213 if (amdgpu_sriov_vf(adev)) { 2214 vinst->cur_state = AMD_PG_STATE_UNGATE; 2215 return 0; 2216 } 2217 2218 if (state == vinst->cur_state) 2219 return 0; 2220 2221 if (state == AMD_PG_STATE_GATE) 2222 ret = vcn_v3_0_stop(vinst); 2223 else 2224 ret = vcn_v3_0_start(vinst); 2225 2226 if (!ret) 2227 vinst->cur_state = state; 2228 2229 return ret; 2230 } 2231 2232 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 2233 struct amdgpu_irq_src *source, 2234 unsigned type, 2235 enum amdgpu_interrupt_state state) 2236 { 2237 return 0; 2238 } 2239 2240 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 2241 struct amdgpu_irq_src *source, 2242 struct amdgpu_iv_entry *entry) 2243 { 2244 uint32_t ip_instance; 2245 2246 switch (entry->client_id) { 2247 case SOC15_IH_CLIENTID_VCN: 2248 ip_instance = 0; 2249 break; 2250 case SOC15_IH_CLIENTID_VCN1: 2251 ip_instance = 1; 2252 break; 2253 default: 2254 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2255 return 0; 2256 } 2257 2258 DRM_DEBUG("IH: VCN TRAP\n"); 2259 2260 switch (entry->src_id) { 2261 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2262 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 2263 break; 2264 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2265 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2266 break; 2267 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2268 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 2269 break; 2270 default: 2271 DRM_ERROR("Unhandled interrupt: %d %d\n", 2272 entry->src_id, entry->src_data[0]); 2273 break; 2274 } 2275 2276 return 0; 2277 } 2278 2279 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 2280 .set = vcn_v3_0_set_interrupt_state, 2281 .process = vcn_v3_0_process_interrupt, 2282 }; 2283 2284 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 2285 { 2286 int i; 2287 2288 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2289 if (adev->vcn.harvest_config & (1 << i)) 2290 continue; 2291 2292 adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 2293 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 2294 } 2295 } 2296 2297 static void vcn_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 2298 { 2299 struct amdgpu_device *adev = ip_block->adev; 2300 int i, j; 2301 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0); 2302 uint32_t inst_off; 2303 bool is_powered; 2304 2305 if (!adev->vcn.ip_dump) 2306 return; 2307 2308 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 2309 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2310 if (adev->vcn.harvest_config & (1 << i)) { 2311 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 2312 continue; 2313 } 2314 2315 inst_off = i * reg_count; 2316 is_powered = (adev->vcn.ip_dump[inst_off] & 2317 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 2318 2319 if (is_powered) { 2320 drm_printf(p, "\nActive Instance:VCN%d\n", i); 2321 for (j = 0; j < reg_count; j++) 2322 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_3_0[j].reg_name, 2323 adev->vcn.ip_dump[inst_off + j]); 2324 } else { 2325 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 2326 } 2327 } 2328 } 2329 2330 static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 2331 { 2332 struct amdgpu_device *adev = ip_block->adev; 2333 int i, j; 2334 bool is_powered; 2335 uint32_t inst_off; 2336 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0); 2337 2338 if (!adev->vcn.ip_dump) 2339 return; 2340 2341 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2342 if (adev->vcn.harvest_config & (1 << i)) 2343 continue; 2344 2345 inst_off = i * reg_count; 2346 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 2347 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS); 2348 is_powered = (adev->vcn.ip_dump[inst_off] & 2349 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 2350 2351 if (is_powered) 2352 for (j = 1; j < reg_count; j++) 2353 adev->vcn.ip_dump[inst_off + j] = 2354 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], i)); 2355 } 2356 } 2357 2358 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 2359 .name = "vcn_v3_0", 2360 .early_init = vcn_v3_0_early_init, 2361 .sw_init = vcn_v3_0_sw_init, 2362 .sw_fini = vcn_v3_0_sw_fini, 2363 .hw_init = vcn_v3_0_hw_init, 2364 .hw_fini = vcn_v3_0_hw_fini, 2365 .suspend = vcn_v3_0_suspend, 2366 .resume = vcn_v3_0_resume, 2367 .is_idle = vcn_v3_0_is_idle, 2368 .wait_for_idle = vcn_v3_0_wait_for_idle, 2369 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 2370 .set_powergating_state = vcn_set_powergating_state, 2371 .dump_ip_state = vcn_v3_0_dump_ip_state, 2372 .print_ip_state = vcn_v3_0_print_ip_state, 2373 }; 2374 2375 const struct amdgpu_ip_block_version vcn_v3_0_ip_block = { 2376 .type = AMD_IP_BLOCK_TYPE_VCN, 2377 .major = 3, 2378 .minor = 0, 2379 .rev = 0, 2380 .funcs = &vcn_v3_0_ip_funcs, 2381 }; 2382