1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "hdp_v5_2.h" 25 26 #include "hdp/hdp_5_2_1_offset.h" 27 #include "hdp/hdp_5_2_1_sh_mask.h" 28 #include <uapi/linux/kfd_ioctl.h> 29 30 static void hdp_v5_2_flush_hdp(struct amdgpu_device *adev, 31 struct amdgpu_ring *ring) 32 { 33 if (!ring || !ring->funcs->emit_wreg) { 34 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 35 0); 36 RREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); 37 } else { 38 amdgpu_ring_emit_wreg(ring, 39 (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 40 0); 41 } 42 } 43 44 static void hdp_v5_2_update_mem_power_gating(struct amdgpu_device *adev, 45 bool enable) 46 { 47 uint32_t hdp_clk_cntl; 48 uint32_t hdp_mem_pwr_cntl; 49 50 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 51 AMD_CG_SUPPORT_HDP_DS | 52 AMD_CG_SUPPORT_HDP_SD))) 53 return; 54 55 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); 56 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); 57 58 /* Before doing clock/power mode switch, forced on MEM clock */ 59 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 60 ATOMIC_MEM_CLK_SOFT_OVERRIDE, 1); 61 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 62 RC_MEM_CLK_SOFT_OVERRIDE, 1); 63 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); 64 65 /* disable clock and power gating before any changing */ 66 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 67 ATOMIC_MEM_POWER_CTRL_EN, 0); 68 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 69 ATOMIC_MEM_POWER_LS_EN, 0); 70 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 71 ATOMIC_MEM_POWER_DS_EN, 0); 72 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 73 ATOMIC_MEM_POWER_SD_EN, 0); 74 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 75 RC_MEM_POWER_CTRL_EN, 0); 76 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 77 RC_MEM_POWER_LS_EN, 0); 78 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 79 RC_MEM_POWER_DS_EN, 0); 80 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 81 RC_MEM_POWER_SD_EN, 0); 82 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 83 84 /* Already disabled above. The actions below are for "enabled" only */ 85 if (enable) { 86 /* only one clock gating mode (LS/DS/SD) can be enabled */ 87 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 88 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 89 HDP_MEM_POWER_CTRL, 90 ATOMIC_MEM_POWER_SD_EN, 1); 91 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 92 HDP_MEM_POWER_CTRL, 93 RC_MEM_POWER_SD_EN, 1); 94 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 95 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 96 HDP_MEM_POWER_CTRL, 97 ATOMIC_MEM_POWER_LS_EN, 1); 98 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 99 HDP_MEM_POWER_CTRL, 100 RC_MEM_POWER_LS_EN, 1); 101 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 102 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 103 HDP_MEM_POWER_CTRL, 104 ATOMIC_MEM_POWER_DS_EN, 1); 105 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 106 HDP_MEM_POWER_CTRL, 107 RC_MEM_POWER_DS_EN, 1); 108 } 109 110 /* confirmed that ATOMIC/RC_MEM_POWER_CTRL_EN have to be set for SRAM LS/DS/SD */ 111 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 112 AMD_CG_SUPPORT_HDP_SD)) { 113 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 114 ATOMIC_MEM_POWER_CTRL_EN, 1); 115 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 116 RC_MEM_POWER_CTRL_EN, 1); 117 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 118 } 119 } 120 121 /* disable MEM clock override after clock/power mode changing */ 122 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 123 ATOMIC_MEM_CLK_SOFT_OVERRIDE, 0); 124 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 125 RC_MEM_CLK_SOFT_OVERRIDE, 0); 126 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); 127 } 128 129 static void hdp_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 130 bool enable) 131 { 132 uint32_t hdp_clk_cntl; 133 134 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 135 return; 136 137 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); 138 139 if (enable) { 140 hdp_clk_cntl &= 141 ~(uint32_t) 142 (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK | 143 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 144 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 145 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 146 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 147 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 148 } else { 149 hdp_clk_cntl |= HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK | 150 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 151 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 152 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 153 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 154 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 155 } 156 157 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); 158 } 159 160 static void hdp_v5_2_get_clockgating_state(struct amdgpu_device *adev, 161 u64 *flags) 162 { 163 uint32_t tmp; 164 165 /* AMD_CG_SUPPORT_HDP_MGCG */ 166 tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); 167 if (!(tmp & (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK | 168 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 169 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 170 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 171 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 172 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 173 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 174 175 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 176 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); 177 if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK) 178 *flags |= AMD_CG_SUPPORT_HDP_LS; 179 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK) 180 *flags |= AMD_CG_SUPPORT_HDP_DS; 181 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK) 182 *flags |= AMD_CG_SUPPORT_HDP_SD; 183 } 184 185 static void hdp_v5_2_update_clock_gating(struct amdgpu_device *adev, 186 bool enable) 187 { 188 hdp_v5_2_update_mem_power_gating(adev, enable); 189 hdp_v5_2_update_medium_grain_clock_gating(adev, enable); 190 } 191 192 const struct amdgpu_hdp_funcs hdp_v5_2_funcs = { 193 .flush_hdp = hdp_v5_2_flush_hdp, 194 .update_clock_gating = hdp_v5_2_update_clock_gating, 195 .get_clock_gating_state = hdp_v5_2_get_clockgating_state, 196 }; 197