1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2011-2012 Avionic Design GmbH 4 */ 5 6 #include <linux/cleanup.h> 7 #include <linux/gpio/driver.h> 8 #include <linux/i2c.h> 9 #include <linux/interrupt.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/mutex.h> 13 #include <linux/property.h> 14 #include <linux/seq_file.h> 15 #include <linux/slab.h> 16 17 #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift) 18 #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift) 19 #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift) 20 #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift) 21 #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift) 22 23 struct adnp { 24 struct i2c_client *client; 25 struct gpio_chip gpio; 26 unsigned int reg_shift; 27 28 struct mutex i2c_lock; 29 struct mutex irq_lock; 30 31 u8 *irq_enable; 32 u8 *irq_level; 33 u8 *irq_rise; 34 u8 *irq_fall; 35 u8 *irq_high; 36 u8 *irq_low; 37 }; 38 39 static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value) 40 { 41 int err; 42 43 err = i2c_smbus_read_byte_data(adnp->client, offset); 44 if (err < 0) { 45 dev_err(adnp->gpio.parent, "%s failed: %d\n", 46 "i2c_smbus_read_byte_data()", err); 47 return err; 48 } 49 50 *value = err; 51 return 0; 52 } 53 54 static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value) 55 { 56 int err; 57 58 err = i2c_smbus_write_byte_data(adnp->client, offset, value); 59 if (err < 0) { 60 dev_err(adnp->gpio.parent, "%s failed: %d\n", 61 "i2c_smbus_write_byte_data()", err); 62 return err; 63 } 64 65 return 0; 66 } 67 68 static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset) 69 { 70 struct adnp *adnp = gpiochip_get_data(chip); 71 unsigned int reg = offset >> adnp->reg_shift; 72 unsigned int pos = offset & 7; 73 u8 value; 74 int err; 75 76 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value); 77 if (err < 0) 78 return err; 79 80 return (value & BIT(pos)) ? 1 : 0; 81 } 82 83 static int __adnp_gpio_set(struct adnp *adnp, unsigned int offset, int value) 84 { 85 unsigned int reg = offset >> adnp->reg_shift; 86 unsigned int pos = offset & 7; 87 int err; 88 u8 val; 89 90 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val); 91 if (err < 0) 92 return err; 93 94 if (value) 95 val |= BIT(pos); 96 else 97 val &= ~BIT(pos); 98 99 return adnp_write(adnp, GPIO_PLR(adnp) + reg, val); 100 } 101 102 static int adnp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 103 { 104 struct adnp *adnp = gpiochip_get_data(chip); 105 106 guard(mutex)(&adnp->i2c_lock); 107 108 return __adnp_gpio_set(adnp, offset, value); 109 } 110 111 static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 112 { 113 struct adnp *adnp = gpiochip_get_data(chip); 114 unsigned int reg = offset >> adnp->reg_shift; 115 unsigned int pos = offset & 7; 116 u8 value; 117 int err; 118 119 guard(mutex)(&adnp->i2c_lock); 120 121 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); 122 if (err < 0) 123 return err; 124 125 value &= ~BIT(pos); 126 127 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value); 128 if (err < 0) 129 return err; 130 131 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value); 132 if (err < 0) 133 return err; 134 135 if (value & BIT(pos)) 136 return -EPERM; 137 138 return 0; 139 } 140 141 static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 142 int value) 143 { 144 struct adnp *adnp = gpiochip_get_data(chip); 145 unsigned int reg = offset >> adnp->reg_shift; 146 unsigned int pos = offset & 7; 147 int err; 148 u8 val; 149 150 guard(mutex)(&adnp->i2c_lock); 151 152 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); 153 if (err < 0) 154 return err; 155 156 val |= BIT(pos); 157 158 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val); 159 if (err < 0) 160 return err; 161 162 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val); 163 if (err < 0) 164 return err; 165 166 if (!(val & BIT(pos))) 167 return -EPERM; 168 169 __adnp_gpio_set(adnp, offset, value); 170 171 return 0; 172 } 173 174 static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 175 { 176 struct adnp *adnp = gpiochip_get_data(chip); 177 unsigned int num_regs = 1 << adnp->reg_shift, i, j; 178 int err; 179 180 for (i = 0; i < num_regs; i++) { 181 u8 ddr = 0, plr = 0, ier = 0, isr = 0; 182 183 scoped_guard(mutex, &adnp->i2c_lock) { 184 err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr); 185 if (err < 0) 186 return; 187 188 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr); 189 if (err < 0) 190 return; 191 192 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); 193 if (err < 0) 194 return; 195 196 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); 197 if (err < 0) 198 return; 199 200 } 201 202 for (j = 0; j < 8; j++) { 203 unsigned int bit = (i << adnp->reg_shift) + j; 204 const char *direction = "input "; 205 const char *level = "low "; 206 const char *interrupt = "disabled"; 207 const char *pending = ""; 208 209 if (ddr & BIT(j)) 210 direction = "output"; 211 212 if (plr & BIT(j)) 213 level = "high"; 214 215 if (ier & BIT(j)) 216 interrupt = "enabled "; 217 218 if (isr & BIT(j)) 219 pending = "pending"; 220 221 seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit, 222 direction, level, interrupt, pending); 223 } 224 } 225 } 226 227 static irqreturn_t adnp_irq(int irq, void *data) 228 { 229 struct adnp *adnp = data; 230 unsigned int num_regs, i; 231 232 num_regs = 1 << adnp->reg_shift; 233 234 for (i = 0; i < num_regs; i++) { 235 unsigned int base = i << adnp->reg_shift, bit; 236 u8 changed, level = 0, isr = 0, ier = 0; 237 unsigned long pending; 238 int err; 239 240 scoped_guard(mutex, &adnp->i2c_lock) { 241 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level); 242 if (err < 0) 243 continue; 244 245 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr); 246 if (err < 0) 247 continue; 248 249 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier); 250 if (err < 0) 251 continue; 252 } 253 254 /* determine pins that changed levels */ 255 changed = level ^ adnp->irq_level[i]; 256 257 /* compute edge-triggered interrupts */ 258 pending = changed & ((adnp->irq_fall[i] & ~level) | 259 (adnp->irq_rise[i] & level)); 260 261 /* add in level-triggered interrupts */ 262 pending |= (adnp->irq_high[i] & level) | 263 (adnp->irq_low[i] & ~level); 264 265 /* mask out non-pending and disabled interrupts */ 266 pending &= isr & ier; 267 268 for_each_set_bit(bit, &pending, 8) { 269 unsigned int child_irq; 270 child_irq = irq_find_mapping(adnp->gpio.irq.domain, 271 base + bit); 272 handle_nested_irq(child_irq); 273 } 274 } 275 276 return IRQ_HANDLED; 277 } 278 279 static void adnp_irq_mask(struct irq_data *d) 280 { 281 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 282 struct adnp *adnp = gpiochip_get_data(gc); 283 unsigned int reg = d->hwirq >> adnp->reg_shift; 284 unsigned int pos = d->hwirq & 7; 285 286 adnp->irq_enable[reg] &= ~BIT(pos); 287 gpiochip_disable_irq(gc, irqd_to_hwirq(d)); 288 } 289 290 static void adnp_irq_unmask(struct irq_data *d) 291 { 292 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 293 struct adnp *adnp = gpiochip_get_data(gc); 294 unsigned int reg = d->hwirq >> adnp->reg_shift; 295 unsigned int pos = d->hwirq & 7; 296 297 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); 298 adnp->irq_enable[reg] |= BIT(pos); 299 } 300 301 static int adnp_irq_set_type(struct irq_data *d, unsigned int type) 302 { 303 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 304 struct adnp *adnp = gpiochip_get_data(gc); 305 unsigned int reg = d->hwirq >> adnp->reg_shift; 306 unsigned int pos = d->hwirq & 7; 307 308 if (type & IRQ_TYPE_EDGE_RISING) 309 adnp->irq_rise[reg] |= BIT(pos); 310 else 311 adnp->irq_rise[reg] &= ~BIT(pos); 312 313 if (type & IRQ_TYPE_EDGE_FALLING) 314 adnp->irq_fall[reg] |= BIT(pos); 315 else 316 adnp->irq_fall[reg] &= ~BIT(pos); 317 318 if (type & IRQ_TYPE_LEVEL_HIGH) 319 adnp->irq_high[reg] |= BIT(pos); 320 else 321 adnp->irq_high[reg] &= ~BIT(pos); 322 323 if (type & IRQ_TYPE_LEVEL_LOW) 324 adnp->irq_low[reg] |= BIT(pos); 325 else 326 adnp->irq_low[reg] &= ~BIT(pos); 327 328 return 0; 329 } 330 331 static void adnp_irq_bus_lock(struct irq_data *d) 332 { 333 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 334 struct adnp *adnp = gpiochip_get_data(gc); 335 336 mutex_lock(&adnp->irq_lock); 337 } 338 339 static void adnp_irq_bus_unlock(struct irq_data *d) 340 { 341 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 342 struct adnp *adnp = gpiochip_get_data(gc); 343 unsigned int num_regs = 1 << adnp->reg_shift, i; 344 345 scoped_guard(mutex, &adnp->i2c_lock) { 346 for (i = 0; i < num_regs; i++) 347 adnp_write(adnp, GPIO_IER(adnp) + i, 348 adnp->irq_enable[i]); 349 } 350 351 mutex_unlock(&adnp->irq_lock); 352 } 353 354 static const struct irq_chip adnp_irq_chip = { 355 .name = "gpio-adnp", 356 .irq_mask = adnp_irq_mask, 357 .irq_unmask = adnp_irq_unmask, 358 .irq_set_type = adnp_irq_set_type, 359 .irq_bus_lock = adnp_irq_bus_lock, 360 .irq_bus_sync_unlock = adnp_irq_bus_unlock, 361 .flags = IRQCHIP_IMMUTABLE, 362 GPIOCHIP_IRQ_RESOURCE_HELPERS, 363 }; 364 365 static int adnp_irq_setup(struct adnp *adnp) 366 { 367 unsigned int num_regs = 1 << adnp->reg_shift, i; 368 struct gpio_chip *chip = &adnp->gpio; 369 int err; 370 371 mutex_init(&adnp->irq_lock); 372 373 /* 374 * Allocate memory to keep track of the current level and trigger 375 * modes of the interrupts. To avoid multiple allocations, a single 376 * large buffer is allocated and pointers are setup to point at the 377 * corresponding offsets. For consistency, the layout of the buffer 378 * is chosen to match the register layout of the hardware in that 379 * each segment contains the corresponding bits for all interrupts. 380 */ 381 adnp->irq_enable = devm_kcalloc(chip->parent, num_regs, 6, 382 GFP_KERNEL); 383 if (!adnp->irq_enable) 384 return -ENOMEM; 385 386 adnp->irq_level = adnp->irq_enable + (num_regs * 1); 387 adnp->irq_rise = adnp->irq_enable + (num_regs * 2); 388 adnp->irq_fall = adnp->irq_enable + (num_regs * 3); 389 adnp->irq_high = adnp->irq_enable + (num_regs * 4); 390 adnp->irq_low = adnp->irq_enable + (num_regs * 5); 391 392 for (i = 0; i < num_regs; i++) { 393 /* 394 * Read the initial level of all pins to allow the emulation 395 * of edge triggered interrupts. 396 */ 397 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]); 398 if (err < 0) 399 return err; 400 401 /* disable all interrupts */ 402 err = adnp_write(adnp, GPIO_IER(adnp) + i, 0); 403 if (err < 0) 404 return err; 405 406 adnp->irq_enable[i] = 0x00; 407 } 408 409 err = devm_request_threaded_irq(chip->parent, adnp->client->irq, 410 NULL, adnp_irq, 411 IRQF_TRIGGER_RISING | IRQF_ONESHOT, 412 dev_name(chip->parent), adnp); 413 if (err != 0) { 414 dev_err(chip->parent, "can't request IRQ#%d: %d\n", 415 adnp->client->irq, err); 416 return err; 417 } 418 419 return 0; 420 } 421 422 static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios, 423 bool is_irq_controller) 424 { 425 struct gpio_chip *chip = &adnp->gpio; 426 int err; 427 428 adnp->reg_shift = get_count_order(num_gpios) - 3; 429 430 chip->direction_input = adnp_gpio_direction_input; 431 chip->direction_output = adnp_gpio_direction_output; 432 chip->get = adnp_gpio_get; 433 chip->set_rv = adnp_gpio_set; 434 chip->can_sleep = true; 435 436 if (IS_ENABLED(CONFIG_DEBUG_FS)) 437 chip->dbg_show = adnp_gpio_dbg_show; 438 439 chip->base = -1; 440 chip->ngpio = num_gpios; 441 chip->label = adnp->client->name; 442 chip->parent = &adnp->client->dev; 443 chip->owner = THIS_MODULE; 444 445 if (is_irq_controller) { 446 struct gpio_irq_chip *girq; 447 448 err = adnp_irq_setup(adnp); 449 if (err) 450 return err; 451 452 girq = &chip->irq; 453 gpio_irq_chip_set_chip(girq, &adnp_irq_chip); 454 455 /* This will let us handle the parent IRQ in the driver */ 456 girq->parent_handler = NULL; 457 girq->num_parents = 0; 458 girq->parents = NULL; 459 girq->default_type = IRQ_TYPE_NONE; 460 girq->handler = handle_simple_irq; 461 girq->threaded = true; 462 } 463 464 err = devm_gpiochip_add_data(&adnp->client->dev, chip, adnp); 465 if (err) 466 return err; 467 468 return 0; 469 } 470 471 static int adnp_i2c_probe(struct i2c_client *client) 472 { 473 struct device *dev = &client->dev; 474 struct adnp *adnp; 475 u32 num_gpios; 476 int err; 477 478 err = device_property_read_u32(dev, "nr-gpios", &num_gpios); 479 if (err < 0) 480 return err; 481 482 adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL); 483 if (!adnp) 484 return -ENOMEM; 485 486 err = devm_mutex_init(&client->dev, &adnp->i2c_lock); 487 if (err) 488 return err; 489 490 adnp->client = client; 491 492 err = adnp_gpio_setup(adnp, num_gpios, device_property_read_bool(dev, "interrupt-controller")); 493 if (err) 494 return err; 495 496 i2c_set_clientdata(client, adnp); 497 498 return 0; 499 } 500 501 static const struct i2c_device_id adnp_i2c_id[] = { 502 { "gpio-adnp" }, 503 { }, 504 }; 505 MODULE_DEVICE_TABLE(i2c, adnp_i2c_id); 506 507 static const struct of_device_id adnp_of_match[] = { 508 { .compatible = "ad,gpio-adnp", }, 509 { }, 510 }; 511 MODULE_DEVICE_TABLE(of, adnp_of_match); 512 513 static struct i2c_driver adnp_i2c_driver = { 514 .driver = { 515 .name = "gpio-adnp", 516 .of_match_table = adnp_of_match, 517 }, 518 .probe = adnp_i2c_probe, 519 .id_table = adnp_i2c_id, 520 }; 521 module_i2c_driver(adnp_i2c_driver); 522 523 MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander"); 524 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); 525 MODULE_LICENSE("GPL"); 526