1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Texas Instruments System Control Interface (TISCI) Protocol 4 * 5 * Communication protocol with TI SCI hardware 6 * The system works in a message response protocol 7 * See: https://software-dl.ti.com/tisci/esd/latest/index.html for details 8 * 9 * Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/ 10 */ 11 12 #ifndef __TI_SCI_H 13 #define __TI_SCI_H 14 15 /* Generic Messages */ 16 #define TI_SCI_MSG_ENABLE_WDT 0x0000 17 #define TI_SCI_MSG_WAKE_RESET 0x0001 18 #define TI_SCI_MSG_VERSION 0x0002 19 #define TI_SCI_MSG_WAKE_REASON 0x0003 20 #define TI_SCI_MSG_GOODBYE 0x0004 21 #define TI_SCI_MSG_SYS_RESET 0x0005 22 #define TI_SCI_MSG_QUERY_FW_CAPS 0x0022 23 24 /* Device requests */ 25 #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200 26 #define TI_SCI_MSG_GET_DEVICE_STATE 0x0201 27 #define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202 28 29 /* Clock requests */ 30 #define TI_SCI_MSG_SET_CLOCK_STATE 0x0100 31 #define TI_SCI_MSG_GET_CLOCK_STATE 0x0101 32 #define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102 33 #define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103 34 #define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104 35 #define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c 36 #define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d 37 #define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e 38 39 /* Low Power Mode Requests */ 40 #define TI_SCI_MSG_PREPARE_SLEEP 0x0300 41 #define TI_SCI_MSG_SET_IO_ISOLATION 0x0307 42 43 /* Resource Management Requests */ 44 #define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500 45 46 /* IRQ requests */ 47 #define TI_SCI_MSG_SET_IRQ 0x1000 48 #define TI_SCI_MSG_FREE_IRQ 0x1001 49 50 /* NAVSS resource management */ 51 /* Ringacc requests */ 52 #define TI_SCI_MSG_RM_RING_ALLOCATE 0x1100 53 #define TI_SCI_MSG_RM_RING_FREE 0x1101 54 #define TI_SCI_MSG_RM_RING_RECONFIG 0x1102 55 #define TI_SCI_MSG_RM_RING_RESET 0x1103 56 #define TI_SCI_MSG_RM_RING_CFG 0x1110 57 58 /* PSI-L requests */ 59 #define TI_SCI_MSG_RM_PSIL_PAIR 0x1280 60 #define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281 61 62 #define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200 63 #define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201 64 #define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210 65 #define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211 66 #define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220 67 #define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221 68 69 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205 70 #define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG 0x1206 71 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215 72 #define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG 0x1216 73 #define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230 74 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231 75 #define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG 0x1232 76 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG 0x1233 77 78 /* Processor Control requests */ 79 #define TI_SCI_MSG_PROC_REQUEST 0xc000 80 #define TI_SCI_MSG_PROC_RELEASE 0xc001 81 #define TI_SCI_MSG_PROC_HANDOVER 0xc005 82 #define TI_SCI_MSG_SET_CONFIG 0xc100 83 #define TI_SCI_MSG_SET_CTRL 0xc101 84 #define TI_SCI_MSG_GET_STATUS 0xc400 85 86 /** 87 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses 88 * @type: Type of messages: One of TI_SCI_MSG* values 89 * @host: Host of the message 90 * @seq: Message identifier indicating a transfer sequence 91 * @flags: Flag for the message 92 */ 93 struct ti_sci_msg_hdr { 94 u16 type; 95 u8 host; 96 u8 seq; 97 #define TI_SCI_MSG_FLAG(val) (1 << (val)) 98 #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0 99 #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0) 100 #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1) 101 #define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0 102 #define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1) 103 /* Additional Flags */ 104 u32 flags; 105 } __packed; 106 107 /** 108 * struct ti_sci_msg_resp_version - Response for a message 109 * @hdr: Generic header 110 * @firmware_description: String describing the firmware 111 * @firmware_revision: Firmware revision 112 * @abi_major: Major version of the ABI that firmware supports 113 * @abi_minor: Minor version of the ABI that firmware supports 114 * 115 * In general, ABI version changes follow the rule that minor version increments 116 * are backward compatible. Major revision changes in ABI may not be 117 * backward compatible. 118 * 119 * Response to a generic message with message type TI_SCI_MSG_VERSION 120 */ 121 struct ti_sci_msg_resp_version { 122 struct ti_sci_msg_hdr hdr; 123 char firmware_description[32]; 124 u16 firmware_revision; 125 u8 abi_major; 126 u8 abi_minor; 127 } __packed; 128 129 /** 130 * struct ti_sci_msg_req_reboot - Reboot the SoC 131 * @hdr: Generic Header 132 * 133 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic 134 * ACK/NACK message. 135 */ 136 struct ti_sci_msg_req_reboot { 137 struct ti_sci_msg_hdr hdr; 138 } __packed; 139 140 /** 141 * struct ti_sci_msg_resp_query_fw_caps - Response for query firmware caps 142 * @hdr: Generic header 143 * @fw_caps: Each bit in fw_caps indicating one FW/SOC capability 144 * MSG_FLAG_CAPS_GENERIC: Generic capability (LPM not supported) 145 * MSG_FLAG_CAPS_LPM_PARTIAL_IO: Partial IO in LPM 146 * MSG_FLAG_CAPS_LPM_DM_MANAGED: LPM can be managed by DM 147 * 148 * Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS 149 * providing currently available SOC/firmware capabilities. SoC that don't 150 * support low power modes return only MSG_FLAG_CAPS_GENERIC capability. 151 */ 152 struct ti_sci_msg_resp_query_fw_caps { 153 struct ti_sci_msg_hdr hdr; 154 #define MSG_FLAG_CAPS_GENERIC TI_SCI_MSG_FLAG(0) 155 #define MSG_FLAG_CAPS_LPM_PARTIAL_IO TI_SCI_MSG_FLAG(4) 156 #define MSG_FLAG_CAPS_LPM_DM_MANAGED TI_SCI_MSG_FLAG(5) 157 #define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1) 158 u64 fw_caps; 159 } __packed; 160 161 /** 162 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device 163 * @hdr: Generic header 164 * @id: Indicates which device to modify 165 * @reserved: Reserved space in message, must be 0 for backward compatibility 166 * @state: The desired state of the device. 167 * 168 * Certain flags can also be set to alter the device state: 169 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source. 170 * The meaning of this flag will vary slightly from device to device and from 171 * SoC to SoC but it generally allows the device to wake the SoC out of deep 172 * suspend states. 173 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device. 174 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed 175 * with STATE_RETENTION or STATE_ON, it will claim the device exclusively. 176 * If another host already has this device set to STATE_RETENTION or STATE_ON, 177 * the message will fail. Once successful, other hosts attempting to set 178 * STATE_RETENTION or STATE_ON will fail. 179 * 180 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic 181 * ACK/NACK message. 182 */ 183 struct ti_sci_msg_req_set_device_state { 184 /* Additional hdr->flags options */ 185 #define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8) 186 #define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9) 187 #define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10) 188 struct ti_sci_msg_hdr hdr; 189 u32 id; 190 u32 reserved; 191 192 #define MSG_DEVICE_SW_STATE_AUTO_OFF 0 193 #define MSG_DEVICE_SW_STATE_RETENTION 1 194 #define MSG_DEVICE_SW_STATE_ON 2 195 u8 state; 196 } __packed; 197 198 /** 199 * struct ti_sci_msg_req_get_device_state - Request to get device. 200 * @hdr: Generic header 201 * @id: Device Identifier 202 * 203 * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state 204 * information 205 */ 206 struct ti_sci_msg_req_get_device_state { 207 struct ti_sci_msg_hdr hdr; 208 u32 id; 209 } __packed; 210 211 /** 212 * struct ti_sci_msg_resp_get_device_state - Response to get device request. 213 * @hdr: Generic header 214 * @context_loss_count: Indicates how many times the device has lost context. A 215 * driver can use this monotonic counter to determine if the device has 216 * lost context since the last time this message was exchanged. 217 * @resets: Programmed state of the reset lines. 218 * @programmed_state: The state as programmed by set_device. 219 * - Uses the MSG_DEVICE_SW_* macros 220 * @current_state: The actual state of the hardware. 221 * 222 * Response to request TI_SCI_MSG_GET_DEVICE_STATE. 223 */ 224 struct ti_sci_msg_resp_get_device_state { 225 struct ti_sci_msg_hdr hdr; 226 u32 context_loss_count; 227 u32 resets; 228 u8 programmed_state; 229 #define MSG_DEVICE_HW_STATE_OFF 0 230 #define MSG_DEVICE_HW_STATE_ON 1 231 #define MSG_DEVICE_HW_STATE_TRANS 2 232 u8 current_state; 233 } __packed; 234 235 /** 236 * struct ti_sci_msg_req_set_device_resets - Set the desired resets 237 * configuration of the device 238 * @hdr: Generic header 239 * @id: Indicates which device to modify 240 * @resets: A bit field of resets for the device. The meaning, behavior, 241 * and usage of the reset flags are device specific. 0 for a bit 242 * indicates releasing the reset represented by that bit while 1 243 * indicates keeping it held. 244 * 245 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic 246 * ACK/NACK message. 247 */ 248 struct ti_sci_msg_req_set_device_resets { 249 struct ti_sci_msg_hdr hdr; 250 u32 id; 251 u32 resets; 252 } __packed; 253 254 /** 255 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state 256 * @hdr: Generic Header, Certain flags can be set specific to the clocks: 257 * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified 258 * via spread spectrum clocking. 259 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's 260 * frequency to be changed while it is running so long as it 261 * is within the min/max limits. 262 * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this 263 * is only applicable to clock inputs on the SoC pseudo-device. 264 * @dev_id: Device identifier this request is for 265 * @clk_id: Clock identifier for the device for this request. 266 * Each device has it's own set of clock inputs. This indexes 267 * which clock input to modify. Set to 255 if clock ID is 268 * greater than or equal to 255. 269 * @request_state: Request the state for the clock to be set to. 270 * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock, 271 * it can be disabled, regardless of the state of the device 272 * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to 273 * automatically manage the state of this clock. If the device 274 * is enabled, then the clock is enabled. If the device is set 275 * to off or retention, then the clock is internally set as not 276 * being required by the device.(default) 277 * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled, 278 * regardless of the state of the device. 279 * @clk_id_32: Clock identifier for the device for this request. 280 * Only to be used if the clock ID is greater than or equal to 281 * 255. 282 * 283 * Normally, all required clocks are managed by TISCI entity, this is used 284 * only for specific control *IF* required. Auto managed state is 285 * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote 286 * will explicitly control. 287 * 288 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic 289 * ACK or NACK message. 290 */ 291 struct ti_sci_msg_req_set_clock_state { 292 /* Additional hdr->flags options */ 293 #define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8) 294 #define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9) 295 #define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10) 296 struct ti_sci_msg_hdr hdr; 297 u32 dev_id; 298 u8 clk_id; 299 #define MSG_CLOCK_SW_STATE_UNREQ 0 300 #define MSG_CLOCK_SW_STATE_AUTO 1 301 #define MSG_CLOCK_SW_STATE_REQ 2 302 u8 request_state; 303 u32 clk_id_32; 304 } __packed; 305 306 /** 307 * struct ti_sci_msg_req_get_clock_state - Request for clock state 308 * @hdr: Generic Header 309 * @dev_id: Device identifier this request is for 310 * @clk_id: Clock identifier for the device for this request. 311 * Each device has it's own set of clock inputs. This indexes 312 * which clock input to get state of. Set to 255 if the clock 313 * ID is greater than or equal to 255. 314 * @clk_id_32: Clock identifier for the device for the request. 315 * Only to be used if the clock ID is greater than or equal to 316 * 255. 317 * 318 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state 319 * of the clock 320 */ 321 struct ti_sci_msg_req_get_clock_state { 322 struct ti_sci_msg_hdr hdr; 323 u32 dev_id; 324 u8 clk_id; 325 u32 clk_id_32; 326 } __packed; 327 328 /** 329 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state 330 * @hdr: Generic Header 331 * @programmed_state: Any programmed state of the clock. This is one of 332 * MSG_CLOCK_SW_STATE* values. 333 * @current_state: Current state of the clock. This is one of: 334 * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready 335 * MSG_CLOCK_HW_STATE_READY: Clock is ready 336 * 337 * Response to TI_SCI_MSG_GET_CLOCK_STATE. 338 */ 339 struct ti_sci_msg_resp_get_clock_state { 340 struct ti_sci_msg_hdr hdr; 341 u8 programmed_state; 342 #define MSG_CLOCK_HW_STATE_NOT_READY 0 343 #define MSG_CLOCK_HW_STATE_READY 1 344 u8 current_state; 345 } __packed; 346 347 /** 348 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent 349 * @hdr: Generic Header 350 * @dev_id: Device identifier this request is for 351 * @clk_id: Clock identifier for the device for this request. 352 * Each device has it's own set of clock inputs. This indexes 353 * which clock input to modify. Set to 255 if clock ID is 354 * greater than or equal to 255. 355 * @parent_id: The new clock parent is selectable by an index via this 356 * parameter. Set to 255 if clock ID is greater than or 357 * equal to 255. 358 * @clk_id_32: Clock identifier if @clk_id field is 255. 359 * @parent_id_32: Parent identifier if @parent_id is 255. 360 * 361 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic 362 * ACK / NACK message. 363 */ 364 struct ti_sci_msg_req_set_clock_parent { 365 struct ti_sci_msg_hdr hdr; 366 u32 dev_id; 367 u8 clk_id; 368 u8 parent_id; 369 u32 clk_id_32; 370 u32 parent_id_32; 371 } __packed; 372 373 /** 374 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent 375 * @hdr: Generic Header 376 * @dev_id: Device identifier this request is for 377 * @clk_id: Clock identifier for the device for this request. 378 * Each device has it's own set of clock inputs. This indexes 379 * which clock input to get the parent for. If this field 380 * contains 255, the actual clock identifier is stored in 381 * @clk_id_32. 382 * @clk_id_32: Clock identifier if the @clk_id field contains 255. 383 * 384 * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information 385 */ 386 struct ti_sci_msg_req_get_clock_parent { 387 struct ti_sci_msg_hdr hdr; 388 u32 dev_id; 389 u8 clk_id; 390 u32 clk_id_32; 391 } __packed; 392 393 /** 394 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent 395 * @hdr: Generic Header 396 * @parent_id: The current clock parent. If set to 255, the current parent 397 * ID can be found from the @parent_id_32 field. 398 * @parent_id_32: Current clock parent if @parent_id field is set to 399 * 255. 400 * 401 * Response to TI_SCI_MSG_GET_CLOCK_PARENT. 402 */ 403 struct ti_sci_msg_resp_get_clock_parent { 404 struct ti_sci_msg_hdr hdr; 405 u8 parent_id; 406 u32 parent_id_32; 407 } __packed; 408 409 /** 410 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents 411 * @hdr: Generic header 412 * @dev_id: Device identifier this request is for 413 * @clk_id: Clock identifier for the device for this request. Set to 414 * 255 if clock ID is greater than or equal to 255. 415 * @clk_id_32: Clock identifier if the @clk_id field contains 255. 416 * 417 * This request provides information about how many clock parent options 418 * are available for a given clock to a device. This is typically used 419 * for input clocks. 420 * 421 * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate 422 * message, or NACK in case of inability to satisfy request. 423 */ 424 struct ti_sci_msg_req_get_clock_num_parents { 425 struct ti_sci_msg_hdr hdr; 426 u32 dev_id; 427 u8 clk_id; 428 u32 clk_id_32; 429 } __packed; 430 431 /** 432 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents 433 * @hdr: Generic header 434 * @num_parents: Number of clock parents. If set to 255, the actual 435 * number of parents is stored into @num_parents_32 436 * field instead. 437 * @num_parents_32: Number of clock parents if @num_parents field is 438 * set to 255. 439 * 440 * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 441 */ 442 struct ti_sci_msg_resp_get_clock_num_parents { 443 struct ti_sci_msg_hdr hdr; 444 u8 num_parents; 445 u32 num_parents_32; 446 } __packed; 447 448 /** 449 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency 450 * @hdr: Generic Header 451 * @dev_id: Device identifier this request is for 452 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 453 * allowable programmed frequency and does not account for clock 454 * tolerances and jitter. 455 * @target_freq_hz: The target clock frequency. A frequency will be found 456 * as close to this target frequency as possible. 457 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 458 * allowable programmed frequency and does not account for clock 459 * tolerances and jitter. 460 * @clk_id: Clock identifier for the device for this request. Set to 461 * 255 if clock identifier is greater than or equal to 255. 462 * @clk_id_32: Clock identifier if @clk_id is set to 255. 463 * 464 * NOTE: Normally clock frequency management is automatically done by TISCI 465 * entity. In case of specific requests, TISCI evaluates capability to achieve 466 * requested frequency within provided range and responds with 467 * result message. 468 * 469 * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message, 470 * or NACK in case of inability to satisfy request. 471 */ 472 struct ti_sci_msg_req_query_clock_freq { 473 struct ti_sci_msg_hdr hdr; 474 u32 dev_id; 475 u64 min_freq_hz; 476 u64 target_freq_hz; 477 u64 max_freq_hz; 478 u8 clk_id; 479 u32 clk_id_32; 480 } __packed; 481 482 /** 483 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query 484 * @hdr: Generic Header 485 * @freq_hz: Frequency that is the best match in Hz. 486 * 487 * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request 488 * cannot be satisfied, the message will be of type NACK. 489 */ 490 struct ti_sci_msg_resp_query_clock_freq { 491 struct ti_sci_msg_hdr hdr; 492 u64 freq_hz; 493 } __packed; 494 495 /** 496 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency 497 * @hdr: Generic Header 498 * @dev_id: Device identifier this request is for 499 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum 500 * allowable programmed frequency and does not account for clock 501 * tolerances and jitter. 502 * @target_freq_hz: The target clock frequency. The clock will be programmed 503 * at a rate as close to this target frequency as possible. 504 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum 505 * allowable programmed frequency and does not account for clock 506 * tolerances and jitter. 507 * @clk_id: Clock identifier for the device for this request. Set to 508 * 255 if clock ID is greater than or equal to 255. 509 * @clk_id_32: Clock identifier if @clk_id field is set to 255. 510 * 511 * NOTE: Normally clock frequency management is automatically done by TISCI 512 * entity. In case of specific requests, TISCI evaluates capability to achieve 513 * requested range and responds with success/failure message. 514 * 515 * This sets the desired frequency for a clock within an allowable 516 * range. This message will fail on an enabled clock unless 517 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally, 518 * if other clocks have their frequency modified due to this message, 519 * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled. 520 * 521 * Calling set frequency on a clock input to the SoC pseudo-device will 522 * inform the PMMC of that clock's frequency. Setting a frequency of 523 * zero will indicate the clock is disabled. 524 * 525 * Calling set frequency on clock outputs from the SoC pseudo-device will 526 * function similarly to setting the clock frequency on a device. 527 * 528 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK 529 * message. 530 */ 531 struct ti_sci_msg_req_set_clock_freq { 532 struct ti_sci_msg_hdr hdr; 533 u32 dev_id; 534 u64 min_freq_hz; 535 u64 target_freq_hz; 536 u64 max_freq_hz; 537 u8 clk_id; 538 u32 clk_id_32; 539 } __packed; 540 541 /** 542 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency 543 * @hdr: Generic Header 544 * @dev_id: Device identifier this request is for 545 * @clk_id: Clock identifier for the device for this request. Set to 546 * 255 if clock ID is greater than or equal to 255. 547 * @clk_id_32: Clock identifier if @clk_id field is set to 255. 548 * 549 * NOTE: Normally clock frequency management is automatically done by TISCI 550 * entity. In some cases, clock frequencies are configured by host. 551 * 552 * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency 553 * that the clock is currently at. 554 */ 555 struct ti_sci_msg_req_get_clock_freq { 556 struct ti_sci_msg_hdr hdr; 557 u32 dev_id; 558 u8 clk_id; 559 u32 clk_id_32; 560 } __packed; 561 562 /** 563 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request 564 * @hdr: Generic Header 565 * @freq_hz: Frequency that the clock is currently on, in Hz. 566 * 567 * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ. 568 */ 569 struct ti_sci_msg_resp_get_clock_freq { 570 struct ti_sci_msg_hdr hdr; 571 u64 freq_hz; 572 } __packed; 573 574 /** 575 * struct tisci_msg_req_prepare_sleep - Request for TISCI_MSG_PREPARE_SLEEP. 576 * 577 * @hdr TISCI header to provide ACK/NAK flags to the host. 578 * @mode Low power mode to enter. 579 * @ctx_lo Low 32-bits of physical pointer to address to use for context save. 580 * @ctx_hi High 32-bits of physical pointer to address to use for context save. 581 * @debug_flags Flags that can be set to halt the sequence during suspend or 582 * resume to allow JTAG connection and debug. 583 * 584 * This message is used as the first step of entering a low power mode. It 585 * allows configurable information, including which state to enter to be 586 * easily shared from the application, as this is a non-secure message and 587 * therefore can be sent by anyone. 588 */ 589 struct ti_sci_msg_req_prepare_sleep { 590 struct ti_sci_msg_hdr hdr; 591 592 #define TISCI_MSG_VALUE_SLEEP_MODE_DM_MANAGED 0xfd 593 u8 mode; 594 u32 ctx_lo; 595 u32 ctx_hi; 596 u32 debug_flags; 597 } __packed; 598 599 /** 600 * struct tisci_msg_set_io_isolation_req - Request for TI_SCI_MSG_SET_IO_ISOLATION. 601 * 602 * @hdr: Generic header 603 * @state: The deseared state of the IO isolation. 604 * 605 * This message is used to enable/disable IO isolation for low power modes. 606 * Response is generic ACK / NACK message. 607 */ 608 struct ti_sci_msg_req_set_io_isolation { 609 struct ti_sci_msg_hdr hdr; 610 u8 state; 611 } __packed; 612 613 #define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff 614 615 /** 616 * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned 617 * range of resources. 618 * @hdr: Generic Header 619 * @type: Unique resource assignment type 620 * @subtype: Resource assignment subtype within the resource type. 621 * @secondary_host: Host processing entity to which the resources are 622 * allocated. This is required only when the destination 623 * host id id different from ti sci interface host id, 624 * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed. 625 * 626 * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested 627 * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE. 628 */ 629 struct ti_sci_msg_req_get_resource_range { 630 struct ti_sci_msg_hdr hdr; 631 #define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0) 632 #define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0) 633 u16 type; 634 u8 subtype; 635 u8 secondary_host; 636 } __packed; 637 638 /** 639 * struct ti_sci_msg_resp_get_resource_range - Response to resource get range. 640 * @hdr: Generic Header 641 * @range_start: Start index of the first resource range. 642 * @range_num: Number of resources in the first range. 643 * @range_start_sec: Start index of the second resource range. 644 * @range_num_sec: Number of resources in the second range. 645 * 646 * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE. 647 */ 648 struct ti_sci_msg_resp_get_resource_range { 649 struct ti_sci_msg_hdr hdr; 650 u16 range_start; 651 u16 range_num; 652 u16 range_start_sec; 653 u16 range_num_sec; 654 } __packed; 655 656 /** 657 * struct ti_sci_msg_req_manage_irq - Request to configure/release the route 658 * between the dev and the host. 659 * @hdr: Generic Header 660 * @valid_params: Bit fields defining the validity of interrupt source 661 * parameters. If a bit is not set, then corresponding 662 * field is not valid and will not be used for route set. 663 * Bit field definitions: 664 * 0 - Valid bit for @dst_id 665 * 1 - Valid bit for @dst_host_irq 666 * 2 - Valid bit for @ia_id 667 * 3 - Valid bit for @vint 668 * 4 - Valid bit for @global_event 669 * 5 - Valid bit for @vint_status_bit_index 670 * 31 - Valid bit for @secondary_host 671 * @src_id: IRQ source peripheral ID. 672 * @src_index: IRQ source index within the peripheral 673 * @dst_id: IRQ Destination ID. Based on the architecture it can be 674 * IRQ controller or host processor ID. 675 * @dst_host_irq: IRQ number of the destination host IRQ controller 676 * @ia_id: Device ID of the interrupt aggregator in which the 677 * vint resides. 678 * @vint: Virtual interrupt number if the interrupt route 679 * is through an interrupt aggregator. 680 * @global_event: Global event that is to be mapped to interrupt 681 * aggregator virtual interrupt status bit. 682 * @vint_status_bit: Virtual interrupt status bit if the interrupt route 683 * utilizes an interrupt aggregator status bit. 684 * @secondary_host: Host ID of the IRQ destination computing entity. This is 685 * required only when destination host id is different 686 * from ti sci interface host id. 687 * 688 * Request type is TI_SCI_MSG_SET/RELEASE_IRQ. 689 * Response is generic ACK / NACK message. 690 */ 691 struct ti_sci_msg_req_manage_irq { 692 struct ti_sci_msg_hdr hdr; 693 #define MSG_FLAG_DST_ID_VALID TI_SCI_MSG_FLAG(0) 694 #define MSG_FLAG_DST_HOST_IRQ_VALID TI_SCI_MSG_FLAG(1) 695 #define MSG_FLAG_IA_ID_VALID TI_SCI_MSG_FLAG(2) 696 #define MSG_FLAG_VINT_VALID TI_SCI_MSG_FLAG(3) 697 #define MSG_FLAG_GLB_EVNT_VALID TI_SCI_MSG_FLAG(4) 698 #define MSG_FLAG_VINT_STS_BIT_VALID TI_SCI_MSG_FLAG(5) 699 #define MSG_FLAG_SHOST_VALID TI_SCI_MSG_FLAG(31) 700 u32 valid_params; 701 u16 src_id; 702 u16 src_index; 703 u16 dst_id; 704 u16 dst_host_irq; 705 u16 ia_id; 706 u16 vint; 707 u16 global_event; 708 u8 vint_status_bit; 709 u8 secondary_host; 710 } __packed; 711 712 /** 713 * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring 714 * 715 * Configures the non-real-time registers of a Navigator Subsystem ring. 716 * @hdr: Generic Header 717 * @valid_params: Bitfield defining validity of ring configuration parameters. 718 * The ring configuration fields are not valid, and will not be used for 719 * ring configuration, if their corresponding valid bit is zero. 720 * Valid bit usage: 721 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo 722 * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi 723 * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count 724 * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode 725 * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size 726 * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id 727 * 6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid 728 * 7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL 729 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated 730 * @index: ring index to be configured. 731 * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's 732 * RING_BA_LO register 733 * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's 734 * RING_BA_HI register. 735 * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM 736 * modes. 737 * @mode: Specifies the mode the ring is to be configured. 738 * @size: Specifies encoded ring element size. To calculate the encoded size use 739 * the formula (log2(size_bytes) - 2), where size_bytes cannot be 740 * greater than 256. 741 * @order_id: Specifies the ring's bus order ID. 742 * @virtid: Ring virt ID value 743 * @asel: Ring ASEL (address select) value to be set into the ASEL field of the 744 * ring's RING_BA_HI register. 745 */ 746 struct ti_sci_msg_rm_ring_cfg_req { 747 struct ti_sci_msg_hdr hdr; 748 u32 valid_params; 749 u16 nav_id; 750 u16 index; 751 u32 addr_lo; 752 u32 addr_hi; 753 u32 count; 754 u8 mode; 755 u8 size; 756 u8 order_id; 757 u16 virtid; 758 u8 asel; 759 } __packed; 760 761 /** 762 * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination 763 * thread 764 * @hdr: Generic Header 765 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is 766 * used to pair the source and destination threads. 767 * @src_thread: PSI-L source thread ID within the PSI-L System thread map. 768 * 769 * UDMAP transmit channels mapped to source threads will have their 770 * TCHAN_THRD_ID register programmed with the destination thread if the pairing 771 * is successful. 772 773 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map. 774 * PSI-L destination threads start at index 0x8000. The request is NACK'd if 775 * the destination thread is not greater than or equal to 0x8000. 776 * 777 * UDMAP receive channels mapped to destination threads will have their 778 * RCHAN_THRD_ID register programmed with the source thread if the pairing 779 * is successful. 780 * 781 * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK 782 * message. 783 */ 784 struct ti_sci_msg_psil_pair { 785 struct ti_sci_msg_hdr hdr; 786 u32 nav_id; 787 u32 src_thread; 788 u32 dst_thread; 789 } __packed; 790 791 /** 792 * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a 793 * destination thread 794 * @hdr: Generic Header 795 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is 796 * used to unpair the source and destination threads. 797 * @src_thread: PSI-L source thread ID within the PSI-L System thread map. 798 * 799 * UDMAP transmit channels mapped to source threads will have their 800 * TCHAN_THRD_ID register cleared if the unpairing is successful. 801 * 802 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map. 803 * PSI-L destination threads start at index 0x8000. The request is NACK'd if 804 * the destination thread is not greater than or equal to 0x8000. 805 * 806 * UDMAP receive channels mapped to destination threads will have their 807 * RCHAN_THRD_ID register cleared if the unpairing is successful. 808 * 809 * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK 810 * message. 811 */ 812 struct ti_sci_msg_psil_unpair { 813 struct ti_sci_msg_hdr hdr; 814 u32 nav_id; 815 u32 src_thread; 816 u32 dst_thread; 817 } __packed; 818 819 /** 820 * struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration 821 * message 822 * @hdr: Generic Header 823 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is 824 * allocated 825 * @flow_index: UDMAP receive flow index for non-optional configuration. 826 * @rx_ch_index: Specifies the index of the receive channel using the flow_index 827 * @rx_einfo_present: UDMAP receive flow extended packet info present. 828 * @rx_psinfo_present: UDMAP receive flow PS words present. 829 * @rx_error_handling: UDMAP receive flow error handling configuration. Valid 830 * values are TI_SCI_RM_UDMAP_RX_FLOW_ERR_DROP/RETRY. 831 * @rx_desc_type: UDMAP receive flow descriptor type. It can be one of 832 * TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST/MONO. 833 * @rx_sop_offset: UDMAP receive flow start of packet offset. 834 * @rx_dest_qnum: UDMAP receive flow destination queue number. 835 * @rx_ps_location: UDMAP receive flow PS words location. 836 * 0 - end of packet descriptor 837 * 1 - Beginning of the data buffer 838 * @rx_src_tag_hi: UDMAP receive flow source tag high byte constant 839 * @rx_src_tag_lo: UDMAP receive flow source tag low byte constant 840 * @rx_dest_tag_hi: UDMAP receive flow destination tag high byte constant 841 * @rx_dest_tag_lo: UDMAP receive flow destination tag low byte constant 842 * @rx_src_tag_hi_sel: UDMAP receive flow source tag high byte selector 843 * @rx_src_tag_lo_sel: UDMAP receive flow source tag low byte selector 844 * @rx_dest_tag_hi_sel: UDMAP receive flow destination tag high byte selector 845 * @rx_dest_tag_lo_sel: UDMAP receive flow destination tag low byte selector 846 * @rx_size_thresh_en: UDMAP receive flow packet size based free buffer queue 847 * enable. If enabled, the ti_sci_rm_udmap_rx_flow_opt_cfg also need to be 848 * configured and sent. 849 * @rx_fdq0_sz0_qnum: UDMAP receive flow free descriptor queue 0. 850 * @rx_fdq1_qnum: UDMAP receive flow free descriptor queue 1. 851 * @rx_fdq2_qnum: UDMAP receive flow free descriptor queue 2. 852 * @rx_fdq3_qnum: UDMAP receive flow free descriptor queue 3. 853 * 854 * For detailed information on the settings, see the UDMAP section of the TRM. 855 */ 856 struct ti_sci_msg_udmap_rx_flow_cfg { 857 struct ti_sci_msg_hdr hdr; 858 u32 nav_id; 859 u32 flow_index; 860 u32 rx_ch_index; 861 u8 rx_einfo_present; 862 u8 rx_psinfo_present; 863 u8 rx_error_handling; 864 u8 rx_desc_type; 865 u16 rx_sop_offset; 866 u16 rx_dest_qnum; 867 u8 rx_ps_location; 868 u8 rx_src_tag_hi; 869 u8 rx_src_tag_lo; 870 u8 rx_dest_tag_hi; 871 u8 rx_dest_tag_lo; 872 u8 rx_src_tag_hi_sel; 873 u8 rx_src_tag_lo_sel; 874 u8 rx_dest_tag_hi_sel; 875 u8 rx_dest_tag_lo_sel; 876 u8 rx_size_thresh_en; 877 u16 rx_fdq0_sz0_qnum; 878 u16 rx_fdq1_qnum; 879 u16 rx_fdq2_qnum; 880 u16 rx_fdq3_qnum; 881 } __packed; 882 883 /** 884 * struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg - parameters for UDMAP receive 885 * flow optional configuration 886 * @hdr: Generic Header 887 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is 888 * allocated 889 * @flow_index: UDMAP receive flow index for optional configuration. 890 * @rx_ch_index: Specifies the index of the receive channel using the flow_index 891 * @rx_size_thresh0: UDMAP receive flow packet size threshold 0. 892 * @rx_size_thresh1: UDMAP receive flow packet size threshold 1. 893 * @rx_size_thresh2: UDMAP receive flow packet size threshold 2. 894 * @rx_fdq0_sz1_qnum: UDMAP receive flow free descriptor queue for size 895 * threshold 1. 896 * @rx_fdq0_sz2_qnum: UDMAP receive flow free descriptor queue for size 897 * threshold 2. 898 * @rx_fdq0_sz3_qnum: UDMAP receive flow free descriptor queue for size 899 * threshold 3. 900 * 901 * For detailed information on the settings, see the UDMAP section of the TRM. 902 */ 903 struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg { 904 struct ti_sci_msg_hdr hdr; 905 u32 nav_id; 906 u32 flow_index; 907 u32 rx_ch_index; 908 u16 rx_size_thresh0; 909 u16 rx_size_thresh1; 910 u16 rx_size_thresh2; 911 u16 rx_fdq0_sz1_qnum; 912 u16 rx_fdq0_sz2_qnum; 913 u16 rx_fdq0_sz3_qnum; 914 } __packed; 915 916 /** 917 * Configures a Navigator Subsystem UDMAP transmit channel 918 * 919 * Configures the non-real-time registers of a Navigator Subsystem UDMAP 920 * transmit channel. The channel index must be assigned to the host defined 921 * in the TISCI header via the RM board configuration resource assignment 922 * range list. 923 * 924 * @hdr: Generic Header 925 * 926 * @valid_params: Bitfield defining validity of tx channel configuration 927 * parameters. The tx channel configuration fields are not valid, and will not 928 * be used for ch configuration, if their corresponding valid bit is zero. 929 * Valid bit usage: 930 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err 931 * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype 932 * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type 933 * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size 934 * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum 935 * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority 936 * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos 937 * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid 938 * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority 939 * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo 940 * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords 941 * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt 942 * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count 943 * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth 944 * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size 945 * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype 946 * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type 947 * 948 * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located 949 * 950 * @index: UDMAP transmit channel index. 951 * 952 * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to 953 * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG 954 * register. 955 * 956 * @tx_filt_einfo: UDMAP transmit channel extended packet information passing 957 * configuration to be programmed into the tx_filt_einfo field of the 958 * channel's TCHAN_TCFG register. 959 * 960 * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing 961 * configuration to be programmed into the tx_filt_pswords field of the 962 * channel's TCHAN_TCFG register. 963 * 964 * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer 965 * interpretation configuration to be programmed into the tx_atype field of 966 * the channel's TCHAN_TCFG register. 967 * 968 * @tx_chan_type: UDMAP transmit channel functional channel type and work 969 * passing mechanism configuration to be programmed into the tx_chan_type 970 * field of the channel's TCHAN_TCFG register. 971 * 972 * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression 973 * configuration to be programmed into the tx_supr_tdpkt field of the channel's 974 * TCHAN_TCFG register. 975 * 976 * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to 977 * fetch configuration to be programmed into the tx_fetch_size field of the 978 * channel's TCHAN_TCFG register. The user must make sure to set the maximum 979 * word count that can pass through the channel for any allowed descriptor type. 980 * 981 * @tx_credit_count: UDMAP transmit channel transfer request credit count 982 * configuration to be programmed into the count field of the TCHAN_TCREDIT 983 * register. Specifies how many credits for complete TRs are available. 984 * 985 * @txcq_qnum: UDMAP transmit channel completion queue configuration to be 986 * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified 987 * completion queue must be assigned to the host, or a subordinate of the host, 988 * requesting configuration of the transmit channel. 989 * 990 * @tx_priority: UDMAP transmit channel transmit priority value to be programmed 991 * into the priority field of the channel's TCHAN_TPRI_CTRL register. 992 * 993 * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the 994 * qos field of the channel's TCHAN_TPRI_CTRL register. 995 * 996 * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into 997 * the orderid field of the channel's TCHAN_TPRI_CTRL register. 998 * 999 * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed 1000 * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of 1001 * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP 1002 * section of the TRM for restrictions regarding this parameter. 1003 * 1004 * @tx_sched_priority: UDMAP transmit channel tx scheduling priority 1005 * configuration to be programmed into the priority field of the channel's 1006 * TCHAN_TST_SCHED register. 1007 * 1008 * @tx_burst_size: UDMAP transmit channel burst size configuration to be 1009 * programmed into the tx_burst_size field of the TCHAN_TCFG register. 1010 * 1011 * @tx_tdtype: UDMAP transmit channel teardown type configuration to be 1012 * programmed into the tdtype field of the TCHAN_TCFG register: 1013 * 0 - Return immediately 1014 * 1 - Wait for completion message from remote peer 1015 * 1016 * @extended_ch_type: Valid for BCDMA. 1017 * 0 - the channel is split tx channel (tchan) 1018 * 1 - the channel is block copy channel (bchan) 1019 */ 1020 struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { 1021 struct ti_sci_msg_hdr hdr; 1022 u32 valid_params; 1023 u16 nav_id; 1024 u16 index; 1025 u8 tx_pause_on_err; 1026 u8 tx_filt_einfo; 1027 u8 tx_filt_pswords; 1028 u8 tx_atype; 1029 u8 tx_chan_type; 1030 u8 tx_supr_tdpkt; 1031 u16 tx_fetch_size; 1032 u8 tx_credit_count; 1033 u16 txcq_qnum; 1034 u8 tx_priority; 1035 u8 tx_qos; 1036 u8 tx_orderid; 1037 u16 fdepth; 1038 u8 tx_sched_priority; 1039 u8 tx_burst_size; 1040 u8 tx_tdtype; 1041 u8 extended_ch_type; 1042 } __packed; 1043 1044 /** 1045 * Configures a Navigator Subsystem UDMAP receive channel 1046 * 1047 * Configures the non-real-time registers of a Navigator Subsystem UDMAP 1048 * receive channel. The channel index must be assigned to the host defined 1049 * in the TISCI header via the RM board configuration resource assignment 1050 * range list. 1051 * 1052 * @hdr: Generic Header 1053 * 1054 * @valid_params: Bitfield defining validity of rx channel configuration 1055 * parameters. 1056 * The rx channel configuration fields are not valid, and will not be used for 1057 * ch configuration, if their corresponding valid bit is zero. 1058 * Valid bit usage: 1059 * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err 1060 * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype 1061 * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type 1062 * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size 1063 * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum 1064 * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority 1065 * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos 1066 * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid 1067 * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority 1068 * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start 1069 * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt 1070 * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short 1071 * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long 1072 * 14 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size 1073 * 1074 * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located 1075 * 1076 * @index: UDMAP receive channel index. 1077 * 1078 * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to 1079 * fetch configuration to be programmed into the rx_fetch_size field of the 1080 * channel's RCHAN_RCFG register. 1081 * 1082 * @rxcq_qnum: UDMAP receive channel completion queue configuration to be 1083 * programmed into the rxcq_qnum field of the RCHAN_RCQ register. 1084 * The specified completion queue must be assigned to the host, or a subordinate 1085 * of the host, requesting configuration of the receive channel. 1086 * 1087 * @rx_priority: UDMAP receive channel receive priority value to be programmed 1088 * into the priority field of the channel's RCHAN_RPRI_CTRL register. 1089 * 1090 * @rx_qos: UDMAP receive channel receive qos value to be programmed into the 1091 * qos field of the channel's RCHAN_RPRI_CTRL register. 1092 * 1093 * @rx_orderid: UDMAP receive channel bus order id value to be programmed into 1094 * the orderid field of the channel's RCHAN_RPRI_CTRL register. 1095 * 1096 * @rx_sched_priority: UDMAP receive channel rx scheduling priority 1097 * configuration to be programmed into the priority field of the channel's 1098 * RCHAN_RST_SCHED register. 1099 * 1100 * @flowid_start: UDMAP receive channel additional flows starting index 1101 * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG 1102 * register. Specifies the starting index for flow IDs the receive channel is to 1103 * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be 1104 * set as valid and configured together. The starting flow ID set by 1105 * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset 1106 * of flows beyond the default flows statically mapped to receive channels. 1107 * The additional flows must be assigned to the host, or a subordinate of the 1108 * host, requesting configuration of the receive channel. 1109 * 1110 * @flowid_cnt: UDMAP receive channel additional flows count configuration to 1111 * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register. 1112 * This field specifies how many flow IDs are in the additional contiguous range 1113 * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be 1114 * set as valid and configured together. Disabling the valid_params field bit 1115 * for flowid_cnt indicates no flow IDs other than the default are to be 1116 * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt 1117 * cannot be greater than the number of receive flows in the receive channel's 1118 * Navigator Subsystem. The additional flows must be assigned to the host, or a 1119 * subordinate of the host, requesting configuration of the receive channel. 1120 * 1121 * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be 1122 * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG 1123 * register. 1124 * 1125 * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer 1126 * interpretation configuration to be programmed into the rx_atype field of the 1127 * channel's RCHAN_RCFG register. 1128 * 1129 * @rx_chan_type: UDMAP receive channel functional channel type and work passing 1130 * mechanism configuration to be programmed into the rx_chan_type field of the 1131 * channel's RCHAN_RCFG register. 1132 * 1133 * @rx_ignore_short: UDMAP receive channel short packet treatment configuration 1134 * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register. 1135 * 1136 * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to 1137 * be programmed into the rx_ignore_long field of the RCHAN_RCFG register. 1138 * 1139 * @rx_burst_size: UDMAP receive channel burst size configuration to be 1140 * programmed into the rx_burst_size field of the RCHAN_RCFG register. 1141 */ 1142 struct ti_sci_msg_rm_udmap_rx_ch_cfg_req { 1143 struct ti_sci_msg_hdr hdr; 1144 u32 valid_params; 1145 u16 nav_id; 1146 u16 index; 1147 u16 rx_fetch_size; 1148 u16 rxcq_qnum; 1149 u8 rx_priority; 1150 u8 rx_qos; 1151 u8 rx_orderid; 1152 u8 rx_sched_priority; 1153 u16 flowid_start; 1154 u16 flowid_cnt; 1155 u8 rx_pause_on_err; 1156 u8 rx_atype; 1157 u8 rx_chan_type; 1158 u8 rx_ignore_short; 1159 u8 rx_ignore_long; 1160 u8 rx_burst_size; 1161 } __packed; 1162 1163 /** 1164 * Configures a Navigator Subsystem UDMAP receive flow 1165 * 1166 * Configures a Navigator Subsystem UDMAP receive flow's registers. 1167 * Configuration does not include the flow registers which handle size-based 1168 * free descriptor queue routing. 1169 * 1170 * The flow index must be assigned to the host defined in the TISCI header via 1171 * the RM board configuration resource assignment range list. 1172 * 1173 * @hdr: Standard TISCI header 1174 * 1175 * @valid_params 1176 * Bitfield defining validity of rx flow configuration parameters. The 1177 * rx flow configuration fields are not valid, and will not be used for flow 1178 * configuration, if their corresponding valid bit is zero. Valid bit usage: 1179 * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present 1180 * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present 1181 * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling 1182 * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type 1183 * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset 1184 * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum 1185 * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi 1186 * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo 1187 * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi 1188 * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo 1189 * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel 1190 * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel 1191 * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel 1192 * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel 1193 * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum 1194 * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum 1195 * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum 1196 * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum 1197 * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location 1198 * 1199 * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is 1200 * allocated 1201 * 1202 * @flow_index: UDMAP receive flow index for non-optional configuration. 1203 * 1204 * @rx_einfo_present: 1205 * UDMAP receive flow extended packet info present configuration to be 1206 * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register. 1207 * 1208 * @rx_psinfo_present: 1209 * UDMAP receive flow PS words present configuration to be programmed into the 1210 * rx_psinfo_present field of the flow's RFLOW_RFA register. 1211 * 1212 * @rx_error_handling: 1213 * UDMAP receive flow error handling configuration to be programmed into the 1214 * rx_error_handling field of the flow's RFLOW_RFA register. 1215 * 1216 * @rx_desc_type: 1217 * UDMAP receive flow descriptor type configuration to be programmed into the 1218 * rx_desc_type field field of the flow's RFLOW_RFA register. 1219 * 1220 * @rx_sop_offset: 1221 * UDMAP receive flow start of packet offset configuration to be programmed 1222 * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP 1223 * section of the TRM for more information on this setting. Valid values for 1224 * this field are 0-255 bytes. 1225 * 1226 * @rx_dest_qnum: 1227 * UDMAP receive flow destination queue configuration to be programmed into the 1228 * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified 1229 * destination queue must be valid within the Navigator Subsystem and must be 1230 * owned by the host, or a subordinate of the host, requesting allocation and 1231 * configuration of the receive flow. 1232 * 1233 * @rx_src_tag_hi: 1234 * UDMAP receive flow source tag high byte constant configuration to be 1235 * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register. 1236 * See the UDMAP section of the TRM for more information on this setting. 1237 * 1238 * @rx_src_tag_lo: 1239 * UDMAP receive flow source tag low byte constant configuration to be 1240 * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register. 1241 * See the UDMAP section of the TRM for more information on this setting. 1242 * 1243 * @rx_dest_tag_hi: 1244 * UDMAP receive flow destination tag high byte constant configuration to be 1245 * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register. 1246 * See the UDMAP section of the TRM for more information on this setting. 1247 * 1248 * @rx_dest_tag_lo: 1249 * UDMAP receive flow destination tag low byte constant configuration to be 1250 * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register. 1251 * See the UDMAP section of the TRM for more information on this setting. 1252 * 1253 * @rx_src_tag_hi_sel: 1254 * UDMAP receive flow source tag high byte selector configuration to be 1255 * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See 1256 * the UDMAP section of the TRM for more information on this setting. 1257 * 1258 * @rx_src_tag_lo_sel: 1259 * UDMAP receive flow source tag low byte selector configuration to be 1260 * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See 1261 * the UDMAP section of the TRM for more information on this setting. 1262 * 1263 * @rx_dest_tag_hi_sel: 1264 * UDMAP receive flow destination tag high byte selector configuration to be 1265 * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See 1266 * the UDMAP section of the TRM for more information on this setting. 1267 * 1268 * @rx_dest_tag_lo_sel: 1269 * UDMAP receive flow destination tag low byte selector configuration to be 1270 * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See 1271 * the UDMAP section of the TRM for more information on this setting. 1272 * 1273 * @rx_fdq0_sz0_qnum: 1274 * UDMAP receive flow free descriptor queue 0 configuration to be programmed 1275 * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the 1276 * UDMAP section of the TRM for more information on this setting. The specified 1277 * free queue must be valid within the Navigator Subsystem and must be owned 1278 * by the host, or a subordinate of the host, requesting allocation and 1279 * configuration of the receive flow. 1280 * 1281 * @rx_fdq1_qnum: 1282 * UDMAP receive flow free descriptor queue 1 configuration to be programmed 1283 * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the 1284 * UDMAP section of the TRM for more information on this setting. The specified 1285 * free queue must be valid within the Navigator Subsystem and must be owned 1286 * by the host, or a subordinate of the host, requesting allocation and 1287 * configuration of the receive flow. 1288 * 1289 * @rx_fdq2_qnum: 1290 * UDMAP receive flow free descriptor queue 2 configuration to be programmed 1291 * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the 1292 * UDMAP section of the TRM for more information on this setting. The specified 1293 * free queue must be valid within the Navigator Subsystem and must be owned 1294 * by the host, or a subordinate of the host, requesting allocation and 1295 * configuration of the receive flow. 1296 * 1297 * @rx_fdq3_qnum: 1298 * UDMAP receive flow free descriptor queue 3 configuration to be programmed 1299 * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the 1300 * UDMAP section of the TRM for more information on this setting. The specified 1301 * free queue must be valid within the Navigator Subsystem and must be owned 1302 * by the host, or a subordinate of the host, requesting allocation and 1303 * configuration of the receive flow. 1304 * 1305 * @rx_ps_location: 1306 * UDMAP receive flow PS words location configuration to be programmed into the 1307 * rx_ps_location field of the flow's RFLOW_RFA register. 1308 */ 1309 struct ti_sci_msg_rm_udmap_flow_cfg_req { 1310 struct ti_sci_msg_hdr hdr; 1311 u32 valid_params; 1312 u16 nav_id; 1313 u16 flow_index; 1314 u8 rx_einfo_present; 1315 u8 rx_psinfo_present; 1316 u8 rx_error_handling; 1317 u8 rx_desc_type; 1318 u16 rx_sop_offset; 1319 u16 rx_dest_qnum; 1320 u8 rx_src_tag_hi; 1321 u8 rx_src_tag_lo; 1322 u8 rx_dest_tag_hi; 1323 u8 rx_dest_tag_lo; 1324 u8 rx_src_tag_hi_sel; 1325 u8 rx_src_tag_lo_sel; 1326 u8 rx_dest_tag_hi_sel; 1327 u8 rx_dest_tag_lo_sel; 1328 u16 rx_fdq0_sz0_qnum; 1329 u16 rx_fdq1_qnum; 1330 u16 rx_fdq2_qnum; 1331 u16 rx_fdq3_qnum; 1332 u8 rx_ps_location; 1333 } __packed; 1334 1335 /** 1336 * struct ti_sci_msg_req_proc_request - Request a processor 1337 * @hdr: Generic Header 1338 * @processor_id: ID of processor being requested 1339 * 1340 * Request type is TI_SCI_MSG_PROC_REQUEST, response is a generic ACK/NACK 1341 * message. 1342 */ 1343 struct ti_sci_msg_req_proc_request { 1344 struct ti_sci_msg_hdr hdr; 1345 u8 processor_id; 1346 } __packed; 1347 1348 /** 1349 * struct ti_sci_msg_req_proc_release - Release a processor 1350 * @hdr: Generic Header 1351 * @processor_id: ID of processor being released 1352 * 1353 * Request type is TI_SCI_MSG_PROC_RELEASE, response is a generic ACK/NACK 1354 * message. 1355 */ 1356 struct ti_sci_msg_req_proc_release { 1357 struct ti_sci_msg_hdr hdr; 1358 u8 processor_id; 1359 } __packed; 1360 1361 /** 1362 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host 1363 * @hdr: Generic Header 1364 * @processor_id: ID of processor being handed over 1365 * @host_id: Host ID the control needs to be transferred to 1366 * 1367 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK 1368 * message. 1369 */ 1370 struct ti_sci_msg_req_proc_handover { 1371 struct ti_sci_msg_hdr hdr; 1372 u8 processor_id; 1373 u8 host_id; 1374 } __packed; 1375 1376 /* Boot Vector masks */ 1377 #define TI_SCI_ADDR_LOW_MASK GENMASK_ULL(31, 0) 1378 #define TI_SCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32) 1379 #define TI_SCI_ADDR_HIGH_SHIFT 32 1380 1381 /** 1382 * struct ti_sci_msg_req_set_config - Set Processor boot configuration 1383 * @hdr: Generic Header 1384 * @processor_id: ID of processor being configured 1385 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector 1386 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector 1387 * @config_flags_set: Optional Processor specific Config Flags to set. 1388 * Setting a bit here implies the corresponding mode 1389 * will be set 1390 * @config_flags_clear: Optional Processor specific Config Flags to clear. 1391 * Setting a bit here implies the corresponding mode 1392 * will be cleared 1393 * 1394 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK 1395 * message. 1396 */ 1397 struct ti_sci_msg_req_set_config { 1398 struct ti_sci_msg_hdr hdr; 1399 u8 processor_id; 1400 u32 bootvector_low; 1401 u32 bootvector_high; 1402 u32 config_flags_set; 1403 u32 config_flags_clear; 1404 } __packed; 1405 1406 /** 1407 * struct ti_sci_msg_req_set_ctrl - Set Processor boot control flags 1408 * @hdr: Generic Header 1409 * @processor_id: ID of processor being configured 1410 * @control_flags_set: Optional Processor specific Control Flags to set. 1411 * Setting a bit here implies the corresponding mode 1412 * will be set 1413 * @control_flags_clear:Optional Processor specific Control Flags to clear. 1414 * Setting a bit here implies the corresponding mode 1415 * will be cleared 1416 * 1417 * Request type is TI_SCI_MSG_SET_CTRL, response is a generic ACK/NACK 1418 * message. 1419 */ 1420 struct ti_sci_msg_req_set_ctrl { 1421 struct ti_sci_msg_hdr hdr; 1422 u8 processor_id; 1423 u32 control_flags_set; 1424 u32 control_flags_clear; 1425 } __packed; 1426 1427 /** 1428 * struct ti_sci_msg_req_get_status - Processor boot status request 1429 * @hdr: Generic Header 1430 * @processor_id: ID of processor whose status is being requested 1431 * 1432 * Request type is TI_SCI_MSG_GET_STATUS, response is an appropriate 1433 * message, or NACK in case of inability to satisfy request. 1434 */ 1435 struct ti_sci_msg_req_get_status { 1436 struct ti_sci_msg_hdr hdr; 1437 u8 processor_id; 1438 } __packed; 1439 1440 /** 1441 * struct ti_sci_msg_resp_get_status - Processor boot status response 1442 * @hdr: Generic Header 1443 * @processor_id: ID of processor whose status is returned 1444 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector 1445 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector 1446 * @config_flags: Optional Processor specific Config Flags set currently 1447 * @control_flags: Optional Processor specific Control Flags set currently 1448 * @status_flags: Optional Processor specific Status Flags set currently 1449 * 1450 * Response structure to a TI_SCI_MSG_GET_STATUS request. 1451 */ 1452 struct ti_sci_msg_resp_get_status { 1453 struct ti_sci_msg_hdr hdr; 1454 u8 processor_id; 1455 u32 bootvector_low; 1456 u32 bootvector_high; 1457 u32 config_flags; 1458 u32 control_flags; 1459 u32 status_flags; 1460 } __packed; 1461 1462 #endif /* __TI_SCI_H */ 1463