1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Intel(R) 10nm server memory controller. 4 * Copyright (c) 2019, Intel Corporation. 5 * 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/io.h> 10 #include <asm/cpu_device_id.h> 11 #include <asm/intel-family.h> 12 #include <asm/mce.h> 13 #include "edac_module.h" 14 #include "skx_common.h" 15 16 #define I10NM_REVISION "v0.0.6" 17 #define EDAC_MOD_STR "i10nm_edac" 18 19 /* Debug macros */ 20 #define i10nm_printk(level, fmt, arg...) \ 21 edac_printk(level, "i10nm", fmt, ##arg) 22 23 #define I10NM_GET_SCK_BAR(d, reg) \ 24 pci_read_config_dword((d)->uracu, 0xd0, &(reg)) 25 #define I10NM_GET_IMC_BAR(d, i, reg) \ 26 pci_read_config_dword((d)->uracu, \ 27 (res_cfg->type == GNR ? 0xd4 : 0xd8) + (i) * 4, &(reg)) 28 #define I10NM_GET_SAD(d, offset, i, reg)\ 29 pci_read_config_dword((d)->sad_all, (offset) + (i) * \ 30 (res_cfg->type == GNR ? 12 : 8), &(reg)) 31 #define I10NM_GET_HBM_IMC_BAR(d, reg) \ 32 pci_read_config_dword((d)->uracu, 0xd4, &(reg)) 33 #define I10NM_GET_CAPID3_CFG(d, reg) \ 34 pci_read_config_dword((d)->pcu_cr3, \ 35 res_cfg->type == GNR ? 0x290 : 0x90, &(reg)) 36 #define I10NM_GET_CAPID5_CFG(d, reg) \ 37 pci_read_config_dword((d)->pcu_cr3, \ 38 res_cfg->type == GNR ? 0x298 : 0x98, &(reg)) 39 #define I10NM_GET_DIMMMTR(m, i, j) \ 40 readl((m)->mbase + ((m)->hbm_mc ? 0x80c : \ 41 (res_cfg->type == GNR ? 0xc0c : 0x2080c)) + \ 42 (i) * (m)->chan_mmio_sz + (j) * 4) 43 #define I10NM_GET_MCDDRTCFG(m, i) \ 44 readl((m)->mbase + ((m)->hbm_mc ? 0x970 : 0x20970) + \ 45 (i) * (m)->chan_mmio_sz) 46 #define I10NM_GET_MCMTR(m, i) \ 47 readl((m)->mbase + ((m)->hbm_mc ? 0xef8 : \ 48 (res_cfg->type == GNR ? 0xaf8 : 0x20ef8)) + \ 49 (i) * (m)->chan_mmio_sz) 50 #define I10NM_GET_REG32(m, i, offset) \ 51 readl((m)->mbase + (i) * (m)->chan_mmio_sz + (offset)) 52 #define I10NM_GET_REG64(m, i, offset) \ 53 readq((m)->mbase + (i) * (m)->chan_mmio_sz + (offset)) 54 #define I10NM_SET_REG32(m, i, offset, v) \ 55 writel(v, (m)->mbase + (i) * (m)->chan_mmio_sz + (offset)) 56 57 #define I10NM_GET_SCK_MMIO_BASE(reg) (GET_BITFIELD(reg, 0, 28) << 23) 58 #define I10NM_GET_IMC_MMIO_OFFSET(reg) (GET_BITFIELD(reg, 0, 10) << 12) 59 #define I10NM_GET_IMC_MMIO_SIZE(reg) ((GET_BITFIELD(reg, 13, 23) - \ 60 GET_BITFIELD(reg, 0, 10) + 1) << 12) 61 #define I10NM_GET_HBM_IMC_MMIO_OFFSET(reg) \ 62 ((GET_BITFIELD(reg, 0, 10) << 12) + 0x140000) 63 64 #define I10NM_GNR_IMC_MMIO_OFFSET 0x24c000 65 #define I10NM_GNR_IMC_MMIO_SIZE 0x4000 66 #define I10NM_HBM_IMC_MMIO_SIZE 0x9000 67 #define I10NM_DDR_IMC_CH_CNT(reg) GET_BITFIELD(reg, 21, 24) 68 #define I10NM_IS_HBM_PRESENT(reg) GET_BITFIELD(reg, 27, 30) 69 #define I10NM_IS_HBM_IMC(reg) GET_BITFIELD(reg, 29, 29) 70 71 #define I10NM_MAX_SAD 16 72 #define I10NM_SAD_ENABLE(reg) GET_BITFIELD(reg, 0, 0) 73 #define I10NM_SAD_NM_CACHEABLE(reg) GET_BITFIELD(reg, 5, 5) 74 75 static struct list_head *i10nm_edac_list; 76 77 static struct res_config *res_cfg; 78 static int retry_rd_err_log; 79 static int decoding_via_mca; 80 static bool mem_cfg_2lm; 81 82 static struct reg_rrl icx_reg_rrl_ddr = { 83 .set_num = 2, 84 .reg_num = 6, 85 .modes = {LRE_SCRUB, LRE_DEMAND}, 86 .offsets = { 87 {0x22c60, 0x22c54, 0x22c5c, 0x22c58, 0x22c28, 0x20ed8}, 88 {0x22e54, 0x22e60, 0x22e64, 0x22e58, 0x22e5c, 0x20ee0}, 89 }, 90 .widths = {4, 4, 4, 4, 4, 8}, 91 .v_mask = BIT(0), 92 .uc_mask = BIT(1), 93 .over_mask = BIT(2), 94 .en_patspr_mask = BIT(13), 95 .noover_mask = BIT(14), 96 .en_mask = BIT(15), 97 98 .cecnt_num = 4, 99 .cecnt_offsets = {0x22c18, 0x22c1c, 0x22c20, 0x22c24}, 100 .cecnt_widths = {4, 4, 4, 4}, 101 }; 102 103 static struct reg_rrl spr_reg_rrl_ddr = { 104 .set_num = 3, 105 .reg_num = 6, 106 .modes = {LRE_SCRUB, LRE_DEMAND, FRE_DEMAND}, 107 .offsets = { 108 {0x22c60, 0x22c54, 0x22f08, 0x22c58, 0x22c28, 0x20ed8}, 109 {0x22e54, 0x22e60, 0x22f10, 0x22e58, 0x22e5c, 0x20ee0}, 110 {0x22c70, 0x22d80, 0x22f18, 0x22d58, 0x22c64, 0x20f10}, 111 }, 112 .widths = {4, 4, 8, 4, 4, 8}, 113 .v_mask = BIT(0), 114 .uc_mask = BIT(1), 115 .over_mask = BIT(2), 116 .en_patspr_mask = BIT(13), 117 .noover_mask = BIT(14), 118 .en_mask = BIT(15), 119 120 .cecnt_num = 4, 121 .cecnt_offsets = {0x22c18, 0x22c1c, 0x22c20, 0x22c24}, 122 .cecnt_widths = {4, 4, 4, 4}, 123 }; 124 125 static struct reg_rrl spr_reg_rrl_hbm_pch0 = { 126 .set_num = 2, 127 .reg_num = 6, 128 .modes = {LRE_SCRUB, LRE_DEMAND}, 129 .offsets = { 130 {0x2860, 0x2854, 0x2b08, 0x2858, 0x2828, 0x0ed8}, 131 {0x2a54, 0x2a60, 0x2b10, 0x2a58, 0x2a5c, 0x0ee0}, 132 }, 133 .widths = {4, 4, 8, 4, 4, 8}, 134 .v_mask = BIT(0), 135 .uc_mask = BIT(1), 136 .over_mask = BIT(2), 137 .en_patspr_mask = BIT(13), 138 .noover_mask = BIT(14), 139 .en_mask = BIT(15), 140 141 .cecnt_num = 4, 142 .cecnt_offsets = {0x2818, 0x281c, 0x2820, 0x2824}, 143 .cecnt_widths = {4, 4, 4, 4}, 144 }; 145 146 static struct reg_rrl spr_reg_rrl_hbm_pch1 = { 147 .set_num = 2, 148 .reg_num = 6, 149 .modes = {LRE_SCRUB, LRE_DEMAND}, 150 .offsets = { 151 {0x2c60, 0x2c54, 0x2f08, 0x2c58, 0x2c28, 0x0fa8}, 152 {0x2e54, 0x2e60, 0x2f10, 0x2e58, 0x2e5c, 0x0fb0}, 153 }, 154 .widths = {4, 4, 8, 4, 4, 8}, 155 .v_mask = BIT(0), 156 .uc_mask = BIT(1), 157 .over_mask = BIT(2), 158 .en_patspr_mask = BIT(13), 159 .noover_mask = BIT(14), 160 .en_mask = BIT(15), 161 162 .cecnt_num = 4, 163 .cecnt_offsets = {0x2c18, 0x2c1c, 0x2c20, 0x2c24}, 164 .cecnt_widths = {4, 4, 4, 4}, 165 }; 166 167 static struct reg_rrl gnr_reg_rrl_ddr = { 168 .set_num = 4, 169 .reg_num = 6, 170 .modes = {FRE_SCRUB, FRE_DEMAND, LRE_SCRUB, LRE_DEMAND}, 171 .offsets = { 172 {0x2f10, 0x2f20, 0x2f30, 0x2f50, 0x2f60, 0xba0}, 173 {0x2f14, 0x2f24, 0x2f38, 0x2f54, 0x2f64, 0xba8}, 174 {0x2f18, 0x2f28, 0x2f40, 0x2f58, 0x2f68, 0xbb0}, 175 {0x2f1c, 0x2f2c, 0x2f48, 0x2f5c, 0x2f6c, 0xbb8}, 176 }, 177 .widths = {4, 4, 8, 4, 4, 8}, 178 .v_mask = BIT(0), 179 .uc_mask = BIT(1), 180 .over_mask = BIT(2), 181 .en_patspr_mask = BIT(14), 182 .noover_mask = BIT(15), 183 .en_mask = BIT(12), 184 185 .cecnt_num = 8, 186 .cecnt_offsets = {0x2c10, 0x2c14, 0x2c18, 0x2c1c, 0x2c20, 0x2c24, 0x2c28, 0x2c2c}, 187 .cecnt_widths = {4, 4, 4, 4, 4, 4, 4, 4}, 188 }; 189 190 static u64 read_imc_reg(struct skx_imc *imc, int chan, u32 offset, u8 width) 191 { 192 switch (width) { 193 case 4: 194 return I10NM_GET_REG32(imc, chan, offset); 195 case 8: 196 return I10NM_GET_REG64(imc, chan, offset); 197 default: 198 i10nm_printk(KERN_ERR, "Invalid readd RRL 0x%x width %d\n", offset, width); 199 return 0; 200 } 201 } 202 203 static void write_imc_reg(struct skx_imc *imc, int chan, u32 offset, u8 width, u64 val) 204 { 205 switch (width) { 206 case 4: 207 return I10NM_SET_REG32(imc, chan, offset, (u32)val); 208 default: 209 i10nm_printk(KERN_ERR, "Invalid write RRL 0x%x width %d\n", offset, width); 210 } 211 } 212 213 static void enable_rrl(struct skx_imc *imc, int chan, struct reg_rrl *rrl, 214 int rrl_set, bool enable, u32 *rrl_ctl) 215 { 216 enum rrl_mode mode = rrl->modes[rrl_set]; 217 u32 offset = rrl->offsets[rrl_set][0], v; 218 u8 width = rrl->widths[0]; 219 bool first, scrub; 220 221 /* First or last read error. */ 222 first = (mode == FRE_SCRUB || mode == FRE_DEMAND); 223 /* Patrol scrub or on-demand read error. */ 224 scrub = (mode == FRE_SCRUB || mode == LRE_SCRUB); 225 226 v = read_imc_reg(imc, chan, offset, width); 227 228 if (enable) { 229 /* Save default configurations. */ 230 *rrl_ctl = v; 231 v &= ~rrl->uc_mask; 232 233 if (first) 234 v |= rrl->noover_mask; 235 else 236 v &= ~rrl->noover_mask; 237 238 if (scrub) 239 v |= rrl->en_patspr_mask; 240 else 241 v &= ~rrl->en_patspr_mask; 242 243 v |= rrl->en_mask; 244 } else { 245 /* Restore default configurations. */ 246 if (*rrl_ctl & rrl->uc_mask) 247 v |= rrl->uc_mask; 248 249 if (first) { 250 if (!(*rrl_ctl & rrl->noover_mask)) 251 v &= ~rrl->noover_mask; 252 } else { 253 if (*rrl_ctl & rrl->noover_mask) 254 v |= rrl->noover_mask; 255 } 256 257 if (scrub) { 258 if (!(*rrl_ctl & rrl->en_patspr_mask)) 259 v &= ~rrl->en_patspr_mask; 260 } else { 261 if (*rrl_ctl & rrl->en_patspr_mask) 262 v |= rrl->en_patspr_mask; 263 } 264 265 if (!(*rrl_ctl & rrl->en_mask)) 266 v &= ~rrl->en_mask; 267 } 268 269 write_imc_reg(imc, chan, offset, width, v); 270 } 271 272 static void enable_rrls(struct skx_imc *imc, int chan, struct reg_rrl *rrl, 273 bool enable, u32 *rrl_ctl) 274 { 275 for (int i = 0; i < rrl->set_num; i++) 276 enable_rrl(imc, chan, rrl, i, enable, rrl_ctl + i); 277 } 278 279 static void enable_rrls_ddr(struct skx_imc *imc, bool enable) 280 { 281 struct reg_rrl *rrl_ddr = res_cfg->reg_rrl_ddr; 282 int i, chan_num = res_cfg->ddr_chan_num; 283 struct skx_channel *chan = imc->chan; 284 285 if (!imc->mbase) 286 return; 287 288 for (i = 0; i < chan_num; i++) 289 enable_rrls(imc, i, rrl_ddr, enable, chan[i].rrl_ctl[0]); 290 } 291 292 static void enable_rrls_hbm(struct skx_imc *imc, bool enable) 293 { 294 struct reg_rrl **rrl_hbm = res_cfg->reg_rrl_hbm; 295 int i, chan_num = res_cfg->hbm_chan_num; 296 struct skx_channel *chan = imc->chan; 297 298 if (!imc->mbase || !imc->hbm_mc || !rrl_hbm[0] || !rrl_hbm[1]) 299 return; 300 301 for (i = 0; i < chan_num; i++) { 302 enable_rrls(imc, i, rrl_hbm[0], enable, chan[i].rrl_ctl[0]); 303 enable_rrls(imc, i, rrl_hbm[1], enable, chan[i].rrl_ctl[1]); 304 } 305 } 306 307 static void enable_retry_rd_err_log(bool enable) 308 { 309 struct skx_dev *d; 310 int i, imc_num; 311 312 edac_dbg(2, "\n"); 313 314 list_for_each_entry(d, i10nm_edac_list, list) { 315 imc_num = res_cfg->ddr_imc_num; 316 for (i = 0; i < imc_num; i++) 317 enable_rrls_ddr(&d->imc[i], enable); 318 319 imc_num += res_cfg->hbm_imc_num; 320 for (; i < imc_num; i++) 321 enable_rrls_hbm(&d->imc[i], enable); 322 } 323 } 324 325 static void show_retry_rd_err_log(struct decoded_addr *res, char *msg, 326 int len, bool scrub_err) 327 { 328 int i, j, n, ch = res->channel, pch = res->cs & 1; 329 struct skx_imc *imc = &res->dev->imc[res->imc]; 330 u64 log, corr, status_mask; 331 struct reg_rrl *rrl; 332 bool scrub; 333 u32 offset; 334 u8 width; 335 336 if (!imc->mbase) 337 return; 338 339 rrl = imc->hbm_mc ? res_cfg->reg_rrl_hbm[pch] : res_cfg->reg_rrl_ddr; 340 341 if (!rrl) 342 return; 343 344 status_mask = rrl->over_mask | rrl->uc_mask | rrl->v_mask; 345 346 n = snprintf(msg, len, " retry_rd_err_log["); 347 for (i = 0; i < rrl->set_num; i++) { 348 scrub = (rrl->modes[i] == FRE_SCRUB || rrl->modes[i] == LRE_SCRUB); 349 if (scrub_err != scrub) 350 continue; 351 352 for (j = 0; j < rrl->reg_num && len - n > 0; j++) { 353 offset = rrl->offsets[i][j]; 354 width = rrl->widths[j]; 355 log = read_imc_reg(imc, ch, offset, width); 356 357 if (width == 4) 358 n += snprintf(msg + n, len - n, "%.8llx ", log); 359 else 360 n += snprintf(msg + n, len - n, "%.16llx ", log); 361 362 /* Clear RRL status if RRL in Linux control mode. */ 363 if (retry_rd_err_log == 2 && !j && (log & status_mask)) 364 write_imc_reg(imc, ch, offset, width, log & ~status_mask); 365 } 366 } 367 368 /* Move back one space. */ 369 n--; 370 n += snprintf(msg + n, len - n, "]"); 371 372 if (len - n > 0) { 373 n += snprintf(msg + n, len - n, " correrrcnt["); 374 for (i = 0; i < rrl->cecnt_num && len - n > 0; i++) { 375 offset = rrl->cecnt_offsets[i]; 376 width = rrl->cecnt_widths[i]; 377 corr = read_imc_reg(imc, ch, offset, width); 378 379 /* CPUs {ICX,SPR} encode two counters per 4-byte CORRERRCNT register. */ 380 if (res_cfg->type <= SPR) { 381 n += snprintf(msg + n, len - n, "%.4llx %.4llx ", 382 corr & 0xffff, corr >> 16); 383 } else { 384 /* CPUs {GNR} encode one counter per CORRERRCNT register. */ 385 if (width == 4) 386 n += snprintf(msg + n, len - n, "%.8llx ", corr); 387 else 388 n += snprintf(msg + n, len - n, "%.16llx ", corr); 389 } 390 } 391 392 /* Move back one space. */ 393 n--; 394 n += snprintf(msg + n, len - n, "]"); 395 } 396 } 397 398 static struct pci_dev *pci_get_dev_wrapper(int dom, unsigned int bus, 399 unsigned int dev, unsigned int fun) 400 { 401 struct pci_dev *pdev; 402 403 pdev = pci_get_domain_bus_and_slot(dom, bus, PCI_DEVFN(dev, fun)); 404 if (!pdev) { 405 edac_dbg(2, "No device %02x:%02x.%x\n", 406 bus, dev, fun); 407 return NULL; 408 } 409 410 if (unlikely(pci_enable_device(pdev) < 0)) { 411 edac_dbg(2, "Failed to enable device %02x:%02x.%x\n", 412 bus, dev, fun); 413 pci_dev_put(pdev); 414 return NULL; 415 } 416 417 return pdev; 418 } 419 420 /** 421 * i10nm_get_imc_num() - Get the number of present DDR memory controllers. 422 * 423 * @cfg : The pointer to the structure of EDAC resource configurations. 424 * 425 * For Granite Rapids CPUs, the number of present DDR memory controllers read 426 * at runtime overwrites the value statically configured in @cfg->ddr_imc_num. 427 * For other CPUs, the number of present DDR memory controllers is statically 428 * configured in @cfg->ddr_imc_num. 429 * 430 * RETURNS : 0 on success, < 0 on failure. 431 */ 432 static int i10nm_get_imc_num(struct res_config *cfg) 433 { 434 int n, imc_num, chan_num = 0; 435 struct skx_dev *d; 436 u32 reg; 437 438 list_for_each_entry(d, i10nm_edac_list, list) { 439 d->pcu_cr3 = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->pcu_cr3_bdf.bus], 440 res_cfg->pcu_cr3_bdf.dev, 441 res_cfg->pcu_cr3_bdf.fun); 442 if (!d->pcu_cr3) 443 continue; 444 445 if (I10NM_GET_CAPID5_CFG(d, reg)) 446 continue; 447 448 n = I10NM_DDR_IMC_CH_CNT(reg); 449 450 if (!chan_num) { 451 chan_num = n; 452 edac_dbg(2, "Get DDR CH number: %d\n", chan_num); 453 } else if (chan_num != n) { 454 i10nm_printk(KERN_NOTICE, "Get DDR CH numbers: %d, %d\n", chan_num, n); 455 } 456 } 457 458 switch (cfg->type) { 459 case GNR: 460 /* 461 * One channel per DDR memory controller for Granite Rapids CPUs. 462 */ 463 imc_num = chan_num; 464 465 if (!imc_num) { 466 i10nm_printk(KERN_ERR, "Invalid DDR MC number\n"); 467 return -ENODEV; 468 } 469 470 if (imc_num > I10NM_NUM_DDR_IMC) { 471 i10nm_printk(KERN_ERR, "Need to make I10NM_NUM_DDR_IMC >= %d\n", imc_num); 472 return -EINVAL; 473 } 474 475 if (cfg->ddr_imc_num != imc_num) { 476 /* 477 * Store the number of present DDR memory controllers. 478 */ 479 cfg->ddr_imc_num = imc_num; 480 edac_dbg(2, "Set DDR MC number: %d", imc_num); 481 } 482 483 return 0; 484 default: 485 /* 486 * For other CPUs, the number of present DDR memory controllers 487 * is statically pre-configured in cfg->ddr_imc_num. 488 */ 489 return 0; 490 } 491 } 492 493 static bool i10nm_check_2lm(struct res_config *cfg) 494 { 495 struct skx_dev *d; 496 u32 reg; 497 int i; 498 499 list_for_each_entry(d, i10nm_edac_list, list) { 500 d->sad_all = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->sad_all_bdf.bus], 501 res_cfg->sad_all_bdf.dev, 502 res_cfg->sad_all_bdf.fun); 503 if (!d->sad_all) 504 continue; 505 506 for (i = 0; i < I10NM_MAX_SAD; i++) { 507 I10NM_GET_SAD(d, cfg->sad_all_offset, i, reg); 508 if (I10NM_SAD_ENABLE(reg) && I10NM_SAD_NM_CACHEABLE(reg)) { 509 edac_dbg(2, "2-level memory configuration.\n"); 510 return true; 511 } 512 } 513 } 514 515 return false; 516 } 517 518 /* 519 * Check whether the error comes from DDRT by ICX/Tremont/SPR model specific error code. 520 * Refer to SDM vol3B 17.11.3/17.13.2 Intel IMC MC error codes for IA32_MCi_STATUS. 521 */ 522 static bool i10nm_mscod_is_ddrt(u32 mscod) 523 { 524 switch (res_cfg->type) { 525 case I10NM: 526 switch (mscod) { 527 case 0x0106: case 0x0107: 528 case 0x0800: case 0x0804: 529 case 0x0806 ... 0x0808: 530 case 0x080a ... 0x080e: 531 case 0x0810: case 0x0811: 532 case 0x0816: case 0x081e: 533 case 0x081f: 534 return true; 535 } 536 537 break; 538 case SPR: 539 switch (mscod) { 540 case 0x0800: case 0x0804: 541 case 0x0806 ... 0x0808: 542 case 0x080a ... 0x080e: 543 case 0x0810: case 0x0811: 544 case 0x0816: case 0x081e: 545 case 0x081f: 546 return true; 547 } 548 549 break; 550 default: 551 return false; 552 } 553 554 return false; 555 } 556 557 static bool i10nm_mc_decode_available(struct mce *mce) 558 { 559 #define ICX_IMCx_CHy 0x06666000 560 u8 bank; 561 562 if (!decoding_via_mca || mem_cfg_2lm) 563 return false; 564 565 if ((mce->status & (MCI_STATUS_MISCV | MCI_STATUS_ADDRV)) 566 != (MCI_STATUS_MISCV | MCI_STATUS_ADDRV)) 567 return false; 568 569 bank = mce->bank; 570 571 switch (res_cfg->type) { 572 case I10NM: 573 /* Check whether the bank is one of {13,14,17,18,21,22,25,26} */ 574 if (!(ICX_IMCx_CHy & (1 << bank))) 575 return false; 576 break; 577 case SPR: 578 if (bank < 13 || bank > 20) 579 return false; 580 break; 581 default: 582 return false; 583 } 584 585 /* DDRT errors can't be decoded from MCA bank registers */ 586 if (MCI_MISC_ECC_MODE(mce->misc) == MCI_MISC_ECC_DDRT) 587 return false; 588 589 if (i10nm_mscod_is_ddrt(MCI_STATUS_MSCOD(mce->status))) 590 return false; 591 592 return true; 593 } 594 595 static bool i10nm_mc_decode(struct decoded_addr *res) 596 { 597 struct mce *m = res->mce; 598 struct skx_dev *d; 599 u8 bank; 600 601 if (!i10nm_mc_decode_available(m)) 602 return false; 603 604 list_for_each_entry(d, i10nm_edac_list, list) { 605 if (d->imc[0].src_id == m->socketid) { 606 res->socket = m->socketid; 607 res->dev = d; 608 break; 609 } 610 } 611 612 switch (res_cfg->type) { 613 case I10NM: 614 bank = m->bank - 13; 615 res->imc = bank / 4; 616 res->channel = bank % 2; 617 res->column = GET_BITFIELD(m->misc, 9, 18) << 2; 618 res->row = GET_BITFIELD(m->misc, 19, 39); 619 res->bank_group = GET_BITFIELD(m->misc, 40, 41); 620 res->bank_address = GET_BITFIELD(m->misc, 42, 43); 621 res->bank_group |= GET_BITFIELD(m->misc, 44, 44) << 2; 622 res->rank = GET_BITFIELD(m->misc, 56, 58); 623 res->dimm = res->rank >> 2; 624 res->rank = res->rank % 4; 625 break; 626 case SPR: 627 bank = m->bank - 13; 628 res->imc = bank / 2; 629 res->channel = bank % 2; 630 res->column = GET_BITFIELD(m->misc, 9, 18) << 2; 631 res->row = GET_BITFIELD(m->misc, 19, 36); 632 res->bank_group = GET_BITFIELD(m->misc, 37, 38); 633 res->bank_address = GET_BITFIELD(m->misc, 39, 40); 634 res->bank_group |= GET_BITFIELD(m->misc, 41, 41) << 2; 635 res->rank = GET_BITFIELD(m->misc, 57, 57); 636 res->dimm = GET_BITFIELD(m->misc, 58, 58); 637 break; 638 default: 639 return false; 640 } 641 642 if (!res->dev) { 643 skx_printk(KERN_ERR, "No device for src_id %d imc %d\n", 644 m->socketid, res->imc); 645 return false; 646 } 647 648 return true; 649 } 650 651 /** 652 * get_gnr_mdev() - Get the PCI device of the @logical_idx-th DDR memory controller. 653 * 654 * @d : The pointer to the structure of CPU socket EDAC device. 655 * @logical_idx : The logical index of the present memory controller (0 ~ max present MC# - 1). 656 * @physical_idx : To store the corresponding physical index of @logical_idx. 657 * 658 * RETURNS : The PCI device of the @logical_idx-th DDR memory controller, NULL on failure. 659 */ 660 static struct pci_dev *get_gnr_mdev(struct skx_dev *d, int logical_idx, int *physical_idx) 661 { 662 #define GNR_MAX_IMC_PCI_CNT 28 663 664 struct pci_dev *mdev; 665 int i, logical = 0; 666 667 /* 668 * Detect present memory controllers from { PCI device: 8-5, function 7-1 } 669 */ 670 for (i = 0; i < GNR_MAX_IMC_PCI_CNT; i++) { 671 mdev = pci_get_dev_wrapper(d->seg, 672 d->bus[res_cfg->ddr_mdev_bdf.bus], 673 res_cfg->ddr_mdev_bdf.dev + i / 7, 674 res_cfg->ddr_mdev_bdf.fun + i % 7); 675 676 if (mdev) { 677 if (logical == logical_idx) { 678 *physical_idx = i; 679 return mdev; 680 } 681 682 pci_dev_put(mdev); 683 logical++; 684 } 685 } 686 687 return NULL; 688 } 689 690 /** 691 * get_ddr_munit() - Get the resource of the i-th DDR memory controller. 692 * 693 * @d : The pointer to the structure of CPU socket EDAC device. 694 * @i : The index of the CPU socket relative DDR memory controller. 695 * @offset : To store the MMIO offset of the i-th DDR memory controller. 696 * @size : To store the MMIO size of the i-th DDR memory controller. 697 * 698 * RETURNS : The PCI device of the i-th DDR memory controller, NULL on failure. 699 */ 700 static struct pci_dev *get_ddr_munit(struct skx_dev *d, int i, u32 *offset, unsigned long *size) 701 { 702 struct pci_dev *mdev; 703 int physical_idx; 704 u32 reg; 705 706 switch (res_cfg->type) { 707 case GNR: 708 if (I10NM_GET_IMC_BAR(d, 0, reg)) { 709 i10nm_printk(KERN_ERR, "Failed to get mc0 bar\n"); 710 return NULL; 711 } 712 713 mdev = get_gnr_mdev(d, i, &physical_idx); 714 if (!mdev) 715 return NULL; 716 717 *offset = I10NM_GET_IMC_MMIO_OFFSET(reg) + 718 I10NM_GNR_IMC_MMIO_OFFSET + 719 physical_idx * I10NM_GNR_IMC_MMIO_SIZE; 720 *size = I10NM_GNR_IMC_MMIO_SIZE; 721 722 break; 723 default: 724 if (I10NM_GET_IMC_BAR(d, i, reg)) { 725 i10nm_printk(KERN_ERR, "Failed to get mc%d bar\n", i); 726 return NULL; 727 } 728 729 mdev = pci_get_dev_wrapper(d->seg, 730 d->bus[res_cfg->ddr_mdev_bdf.bus], 731 res_cfg->ddr_mdev_bdf.dev + i, 732 res_cfg->ddr_mdev_bdf.fun); 733 if (!mdev) 734 return NULL; 735 736 *offset = I10NM_GET_IMC_MMIO_OFFSET(reg); 737 *size = I10NM_GET_IMC_MMIO_SIZE(reg); 738 } 739 740 return mdev; 741 } 742 743 /** 744 * i10nm_imc_absent() - Check whether the memory controller @imc is absent 745 * 746 * @imc : The pointer to the structure of memory controller EDAC device. 747 * 748 * RETURNS : true if the memory controller EDAC device is absent, false otherwise. 749 */ 750 static bool i10nm_imc_absent(struct skx_imc *imc) 751 { 752 u32 mcmtr; 753 int i; 754 755 switch (res_cfg->type) { 756 case SPR: 757 for (i = 0; i < res_cfg->ddr_chan_num; i++) { 758 mcmtr = I10NM_GET_MCMTR(imc, i); 759 edac_dbg(1, "ch%d mcmtr reg %x\n", i, mcmtr); 760 if (mcmtr != ~0) 761 return false; 762 } 763 764 /* 765 * Some workstations' absent memory controllers still 766 * appear as PCIe devices, misleading the EDAC driver. 767 * By observing that the MMIO registers of these absent 768 * memory controllers consistently hold the value of ~0. 769 * 770 * We identify a memory controller as absent by checking 771 * if its MMIO register "mcmtr" == ~0 in all its channels. 772 */ 773 return true; 774 default: 775 return false; 776 } 777 } 778 779 static int i10nm_get_ddr_munits(void) 780 { 781 struct pci_dev *mdev; 782 void __iomem *mbase; 783 unsigned long size; 784 struct skx_dev *d; 785 int i, lmc, j = 0; 786 u32 reg, off; 787 u64 base; 788 789 list_for_each_entry(d, i10nm_edac_list, list) { 790 d->util_all = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->util_all_bdf.bus], 791 res_cfg->util_all_bdf.dev, 792 res_cfg->util_all_bdf.fun); 793 if (!d->util_all) 794 return -ENODEV; 795 796 d->uracu = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->uracu_bdf.bus], 797 res_cfg->uracu_bdf.dev, 798 res_cfg->uracu_bdf.fun); 799 if (!d->uracu) 800 return -ENODEV; 801 802 if (I10NM_GET_SCK_BAR(d, reg)) { 803 i10nm_printk(KERN_ERR, "Failed to socket bar\n"); 804 return -ENODEV; 805 } 806 807 base = I10NM_GET_SCK_MMIO_BASE(reg); 808 edac_dbg(2, "socket%d mmio base 0x%llx (reg 0x%x)\n", 809 j++, base, reg); 810 811 for (lmc = 0, i = 0; i < res_cfg->ddr_imc_num; i++) { 812 mdev = get_ddr_munit(d, i, &off, &size); 813 814 if (i == 0 && !mdev) { 815 i10nm_printk(KERN_ERR, "No IMC found\n"); 816 return -ENODEV; 817 } 818 if (!mdev) 819 continue; 820 821 edac_dbg(2, "mc%d mmio base 0x%llx size 0x%lx (reg 0x%x)\n", 822 i, base + off, size, reg); 823 824 mbase = ioremap(base + off, size); 825 if (!mbase) { 826 i10nm_printk(KERN_ERR, "Failed to ioremap 0x%llx\n", 827 base + off); 828 return -ENODEV; 829 } 830 831 d->imc[lmc].mbase = mbase; 832 if (i10nm_imc_absent(&d->imc[lmc])) { 833 pci_dev_put(mdev); 834 iounmap(mbase); 835 d->imc[lmc].mbase = NULL; 836 edac_dbg(2, "Skip absent mc%d\n", i); 837 continue; 838 } else { 839 d->imc[lmc].mdev = mdev; 840 if (res_cfg->type == SPR) 841 skx_set_mc_mapping(d, i, lmc); 842 lmc++; 843 } 844 } 845 } 846 847 return 0; 848 } 849 850 static bool i10nm_check_hbm_imc(struct skx_dev *d) 851 { 852 u32 reg; 853 854 if (I10NM_GET_CAPID3_CFG(d, reg)) { 855 i10nm_printk(KERN_ERR, "Failed to get capid3_cfg\n"); 856 return false; 857 } 858 859 return I10NM_IS_HBM_PRESENT(reg) != 0; 860 } 861 862 static int i10nm_get_hbm_munits(void) 863 { 864 struct pci_dev *mdev; 865 void __iomem *mbase; 866 u32 reg, off, mcmtr; 867 struct skx_dev *d; 868 int i, lmc; 869 u64 base; 870 871 list_for_each_entry(d, i10nm_edac_list, list) { 872 if (!d->pcu_cr3) 873 return -ENODEV; 874 875 if (!i10nm_check_hbm_imc(d)) { 876 i10nm_printk(KERN_DEBUG, "No hbm memory\n"); 877 return -ENODEV; 878 } 879 880 if (I10NM_GET_SCK_BAR(d, reg)) { 881 i10nm_printk(KERN_ERR, "Failed to get socket bar\n"); 882 return -ENODEV; 883 } 884 base = I10NM_GET_SCK_MMIO_BASE(reg); 885 886 if (I10NM_GET_HBM_IMC_BAR(d, reg)) { 887 i10nm_printk(KERN_ERR, "Failed to get hbm mc bar\n"); 888 return -ENODEV; 889 } 890 base += I10NM_GET_HBM_IMC_MMIO_OFFSET(reg); 891 892 lmc = res_cfg->ddr_imc_num; 893 894 for (i = 0; i < res_cfg->hbm_imc_num; i++) { 895 mdev = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->hbm_mdev_bdf.bus], 896 res_cfg->hbm_mdev_bdf.dev + i / 4, 897 res_cfg->hbm_mdev_bdf.fun + i % 4); 898 899 if (i == 0 && !mdev) { 900 i10nm_printk(KERN_ERR, "No hbm mc found\n"); 901 return -ENODEV; 902 } 903 if (!mdev) 904 continue; 905 906 d->imc[lmc].mdev = mdev; 907 off = i * I10NM_HBM_IMC_MMIO_SIZE; 908 909 edac_dbg(2, "hbm mc%d mmio base 0x%llx size 0x%x\n", 910 lmc, base + off, I10NM_HBM_IMC_MMIO_SIZE); 911 912 mbase = ioremap(base + off, I10NM_HBM_IMC_MMIO_SIZE); 913 if (!mbase) { 914 pci_dev_put(d->imc[lmc].mdev); 915 d->imc[lmc].mdev = NULL; 916 917 i10nm_printk(KERN_ERR, "Failed to ioremap for hbm mc 0x%llx\n", 918 base + off); 919 return -ENOMEM; 920 } 921 922 d->imc[lmc].mbase = mbase; 923 d->imc[lmc].hbm_mc = true; 924 925 mcmtr = I10NM_GET_MCMTR(&d->imc[lmc], 0); 926 if (!I10NM_IS_HBM_IMC(mcmtr)) { 927 iounmap(d->imc[lmc].mbase); 928 d->imc[lmc].mbase = NULL; 929 d->imc[lmc].hbm_mc = false; 930 pci_dev_put(d->imc[lmc].mdev); 931 d->imc[lmc].mdev = NULL; 932 933 i10nm_printk(KERN_ERR, "This isn't an hbm mc!\n"); 934 return -ENODEV; 935 } 936 937 lmc++; 938 } 939 } 940 941 return 0; 942 } 943 944 static struct res_config i10nm_cfg0 = { 945 .type = I10NM, 946 .decs_did = 0x3452, 947 .busno_cfg_offset = 0xcc, 948 .ddr_imc_num = 4, 949 .ddr_chan_num = 2, 950 .ddr_dimm_num = 2, 951 .ddr_chan_mmio_sz = 0x4000, 952 .sad_all_bdf = {1, 29, 0}, 953 .pcu_cr3_bdf = {1, 30, 3}, 954 .util_all_bdf = {1, 29, 1}, 955 .uracu_bdf = {0, 0, 1}, 956 .ddr_mdev_bdf = {0, 12, 0}, 957 .hbm_mdev_bdf = {0, 12, 1}, 958 .sad_all_offset = 0x108, 959 .reg_rrl_ddr = &icx_reg_rrl_ddr, 960 }; 961 962 static struct res_config i10nm_cfg1 = { 963 .type = I10NM, 964 .decs_did = 0x3452, 965 .busno_cfg_offset = 0xd0, 966 .ddr_imc_num = 4, 967 .ddr_chan_num = 2, 968 .ddr_dimm_num = 2, 969 .ddr_chan_mmio_sz = 0x4000, 970 .sad_all_bdf = {1, 29, 0}, 971 .pcu_cr3_bdf = {1, 30, 3}, 972 .util_all_bdf = {1, 29, 1}, 973 .uracu_bdf = {0, 0, 1}, 974 .ddr_mdev_bdf = {0, 12, 0}, 975 .hbm_mdev_bdf = {0, 12, 1}, 976 .sad_all_offset = 0x108, 977 .reg_rrl_ddr = &icx_reg_rrl_ddr, 978 }; 979 980 static struct res_config spr_cfg = { 981 .type = SPR, 982 .decs_did = 0x3252, 983 .busno_cfg_offset = 0xd0, 984 .ddr_imc_num = 4, 985 .ddr_chan_num = 2, 986 .ddr_dimm_num = 2, 987 .hbm_imc_num = 16, 988 .hbm_chan_num = 2, 989 .hbm_dimm_num = 1, 990 .ddr_chan_mmio_sz = 0x8000, 991 .hbm_chan_mmio_sz = 0x4000, 992 .support_ddr5 = true, 993 .sad_all_bdf = {1, 10, 0}, 994 .pcu_cr3_bdf = {1, 30, 3}, 995 .util_all_bdf = {1, 29, 1}, 996 .uracu_bdf = {0, 0, 1}, 997 .ddr_mdev_bdf = {0, 12, 0}, 998 .hbm_mdev_bdf = {0, 12, 1}, 999 .sad_all_offset = 0x300, 1000 .reg_rrl_ddr = &spr_reg_rrl_ddr, 1001 .reg_rrl_hbm[0] = &spr_reg_rrl_hbm_pch0, 1002 .reg_rrl_hbm[1] = &spr_reg_rrl_hbm_pch1, 1003 }; 1004 1005 static struct res_config gnr_cfg = { 1006 .type = GNR, 1007 .decs_did = 0x3252, 1008 .busno_cfg_offset = 0xd0, 1009 .ddr_imc_num = 12, 1010 .ddr_chan_num = 1, 1011 .ddr_dimm_num = 2, 1012 .ddr_chan_mmio_sz = 0x4000, 1013 .support_ddr5 = true, 1014 .sad_all_bdf = {0, 13, 0}, 1015 .pcu_cr3_bdf = {0, 5, 0}, 1016 .util_all_bdf = {0, 13, 1}, 1017 .uracu_bdf = {0, 0, 1}, 1018 .ddr_mdev_bdf = {0, 5, 1}, 1019 .sad_all_offset = 0x300, 1020 .reg_rrl_ddr = &gnr_reg_rrl_ddr, 1021 }; 1022 1023 static const struct x86_cpu_id i10nm_cpuids[] = { 1024 X86_MATCH_VFM_STEPS(INTEL_ATOM_TREMONT_D, X86_STEP_MIN, 0x3, &i10nm_cfg0), 1025 X86_MATCH_VFM_STEPS(INTEL_ATOM_TREMONT_D, 0x4, X86_STEP_MAX, &i10nm_cfg1), 1026 X86_MATCH_VFM_STEPS(INTEL_ICELAKE_X, X86_STEP_MIN, 0x3, &i10nm_cfg0), 1027 X86_MATCH_VFM_STEPS(INTEL_ICELAKE_X, 0x4, X86_STEP_MAX, &i10nm_cfg1), 1028 X86_MATCH_VFM( INTEL_ICELAKE_D, &i10nm_cfg1), 1029 1030 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &spr_cfg), 1031 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &spr_cfg), 1032 X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, &gnr_cfg), 1033 X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X, &gnr_cfg), 1034 X86_MATCH_VFM(INTEL_ATOM_CRESTMONT, &gnr_cfg), 1035 X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X, &gnr_cfg), 1036 {} 1037 }; 1038 MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids); 1039 1040 static bool i10nm_check_ecc(struct skx_imc *imc, int chan) 1041 { 1042 u32 mcmtr; 1043 1044 mcmtr = I10NM_GET_MCMTR(imc, chan); 1045 edac_dbg(1, "ch%d mcmtr reg %x\n", chan, mcmtr); 1046 1047 return !!GET_BITFIELD(mcmtr, 2, 2); 1048 } 1049 1050 static int i10nm_get_dimm_config(struct mem_ctl_info *mci, 1051 struct res_config *cfg) 1052 { 1053 struct skx_pvt *pvt = mci->pvt_info; 1054 struct skx_imc *imc = pvt->imc; 1055 u32 mtr, mcddrtcfg = 0; 1056 struct dimm_info *dimm; 1057 int i, j, ndimms; 1058 1059 for (i = 0; i < imc->num_channels; i++) { 1060 if (!imc->mbase) 1061 continue; 1062 1063 ndimms = 0; 1064 1065 if (res_cfg->type != GNR) 1066 mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i); 1067 1068 for (j = 0; j < imc->num_dimms; j++) { 1069 dimm = edac_get_dimm(mci, i, j, 0); 1070 mtr = I10NM_GET_DIMMMTR(imc, i, j); 1071 edac_dbg(1, "dimmmtr 0x%x mcddrtcfg 0x%x (mc%d ch%d dimm%d)\n", 1072 mtr, mcddrtcfg, imc->mc, i, j); 1073 1074 if (IS_DIMM_PRESENT(mtr)) 1075 ndimms += skx_get_dimm_info(mtr, 0, 0, dimm, 1076 imc, i, j, cfg); 1077 else if (IS_NVDIMM_PRESENT(mcddrtcfg, j)) 1078 ndimms += skx_get_nvdimm_info(dimm, imc, i, j, 1079 EDAC_MOD_STR); 1080 } 1081 if (ndimms && !i10nm_check_ecc(imc, i)) { 1082 i10nm_printk(KERN_ERR, "ECC is disabled on imc %d channel %d\n", 1083 imc->mc, i); 1084 return -ENODEV; 1085 } 1086 } 1087 1088 return 0; 1089 } 1090 1091 static struct notifier_block i10nm_mce_dec = { 1092 .notifier_call = skx_mce_check_error, 1093 .priority = MCE_PRIO_EDAC, 1094 }; 1095 1096 static int __init i10nm_init(void) 1097 { 1098 u8 mc = 0, src_id = 0; 1099 const struct x86_cpu_id *id; 1100 struct res_config *cfg; 1101 const char *owner; 1102 struct skx_dev *d; 1103 int rc, i, off[3] = {0xd0, 0xc8, 0xcc}; 1104 u64 tolm, tohm; 1105 int imc_num; 1106 1107 edac_dbg(2, "\n"); 1108 1109 if (ghes_get_devices()) 1110 return -EBUSY; 1111 1112 owner = edac_get_owner(); 1113 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) 1114 return -EBUSY; 1115 1116 if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) 1117 return -ENODEV; 1118 1119 id = x86_match_cpu(i10nm_cpuids); 1120 if (!id) 1121 return -ENODEV; 1122 1123 cfg = (struct res_config *)id->driver_data; 1124 skx_set_res_cfg(cfg); 1125 res_cfg = cfg; 1126 1127 rc = skx_get_hi_lo(0x09a2, off, &tolm, &tohm); 1128 if (rc) 1129 return rc; 1130 1131 rc = skx_get_all_bus_mappings(cfg, &i10nm_edac_list); 1132 if (rc < 0) 1133 goto fail; 1134 if (rc == 0) { 1135 i10nm_printk(KERN_ERR, "No memory controllers found\n"); 1136 return -ENODEV; 1137 } 1138 1139 rc = i10nm_get_imc_num(cfg); 1140 if (rc < 0) 1141 goto fail; 1142 1143 mem_cfg_2lm = i10nm_check_2lm(cfg); 1144 skx_set_mem_cfg(mem_cfg_2lm); 1145 1146 rc = i10nm_get_ddr_munits(); 1147 1148 if (i10nm_get_hbm_munits() && rc) 1149 goto fail; 1150 1151 imc_num = res_cfg->ddr_imc_num + res_cfg->hbm_imc_num; 1152 1153 list_for_each_entry(d, i10nm_edac_list, list) { 1154 rc = skx_get_src_id(d, 0xf8, &src_id); 1155 if (rc < 0) 1156 goto fail; 1157 1158 edac_dbg(2, "src_id = %d\n", src_id); 1159 for (i = 0; i < imc_num; i++) { 1160 if (!d->imc[i].mdev) 1161 continue; 1162 1163 d->imc[i].mc = mc++; 1164 d->imc[i].lmc = i; 1165 d->imc[i].src_id = src_id; 1166 if (d->imc[i].hbm_mc) { 1167 d->imc[i].chan_mmio_sz = cfg->hbm_chan_mmio_sz; 1168 d->imc[i].num_channels = cfg->hbm_chan_num; 1169 d->imc[i].num_dimms = cfg->hbm_dimm_num; 1170 } else { 1171 d->imc[i].chan_mmio_sz = cfg->ddr_chan_mmio_sz; 1172 d->imc[i].num_channels = cfg->ddr_chan_num; 1173 d->imc[i].num_dimms = cfg->ddr_dimm_num; 1174 } 1175 1176 rc = skx_register_mci(&d->imc[i], d->imc[i].mdev, 1177 "Intel_10nm Socket", EDAC_MOD_STR, 1178 i10nm_get_dimm_config, cfg); 1179 if (rc < 0) 1180 goto fail; 1181 } 1182 } 1183 1184 rc = skx_adxl_get(); 1185 if (rc) 1186 goto fail; 1187 1188 opstate_init(); 1189 mce_register_decode_chain(&i10nm_mce_dec); 1190 skx_setup_debug("i10nm_test"); 1191 1192 if (retry_rd_err_log && res_cfg->reg_rrl_ddr) { 1193 skx_set_decode(i10nm_mc_decode, show_retry_rd_err_log); 1194 if (retry_rd_err_log == 2) 1195 enable_retry_rd_err_log(true); 1196 } else { 1197 skx_set_decode(i10nm_mc_decode, NULL); 1198 } 1199 1200 i10nm_printk(KERN_INFO, "%s\n", I10NM_REVISION); 1201 1202 return 0; 1203 fail: 1204 skx_remove(); 1205 return rc; 1206 } 1207 1208 static void __exit i10nm_exit(void) 1209 { 1210 edac_dbg(2, "\n"); 1211 1212 if (retry_rd_err_log && res_cfg->reg_rrl_ddr) { 1213 skx_set_decode(NULL, NULL); 1214 if (retry_rd_err_log == 2) 1215 enable_retry_rd_err_log(false); 1216 } 1217 1218 skx_teardown_debug(); 1219 mce_unregister_decode_chain(&i10nm_mce_dec); 1220 skx_adxl_put(); 1221 skx_remove(); 1222 } 1223 1224 module_init(i10nm_init); 1225 module_exit(i10nm_exit); 1226 1227 static int set_decoding_via_mca(const char *buf, const struct kernel_param *kp) 1228 { 1229 unsigned long val; 1230 int ret; 1231 1232 ret = kstrtoul(buf, 0, &val); 1233 1234 if (ret || val > 1) 1235 return -EINVAL; 1236 1237 if (val && mem_cfg_2lm) { 1238 i10nm_printk(KERN_NOTICE, "Decoding errors via MCA banks for 2LM isn't supported yet\n"); 1239 return -EIO; 1240 } 1241 1242 ret = param_set_int(buf, kp); 1243 1244 return ret; 1245 } 1246 1247 static const struct kernel_param_ops decoding_via_mca_param_ops = { 1248 .set = set_decoding_via_mca, 1249 .get = param_get_int, 1250 }; 1251 1252 module_param_cb(decoding_via_mca, &decoding_via_mca_param_ops, &decoding_via_mca, 0644); 1253 MODULE_PARM_DESC(decoding_via_mca, "decoding_via_mca: 0=off(default), 1=enable"); 1254 1255 module_param(retry_rd_err_log, int, 0444); 1256 MODULE_PARM_DESC(retry_rd_err_log, "retry_rd_err_log: 0=off(default), 1=bios(Linux doesn't reset any control bits, but just reports values.), 2=linux(Linux tries to take control and resets mode bits, clear valid/UC bits after reading.)"); 1257 1258 MODULE_LICENSE("GPL v2"); 1259 MODULE_DESCRIPTION("MC Driver for Intel 10nm server processors"); 1260