1 /* 2 * Applied Micro X-Gene SoC DMA engine Driver 3 * 4 * Copyright (c) 2015, Applied Micro Circuits Corporation 5 * Authors: Rameshwar Prasad Sahu <rsahu@apm.com> 6 * Loc Ho <lho@apm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 * 21 * NOTE: PM support is currently not available. 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/clk.h> 26 #include <linux/delay.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmaengine.h> 29 #include <linux/dmapool.h> 30 #include <linux/interrupt.h> 31 #include <linux/io.h> 32 #include <linux/irq.h> 33 #include <linux/module.h> 34 #include <linux/of_device.h> 35 36 #include "dmaengine.h" 37 38 /* X-Gene DMA ring csr registers and bit definations */ 39 #define XGENE_DMA_RING_CONFIG 0x04 40 #define XGENE_DMA_RING_ENABLE BIT(31) 41 #define XGENE_DMA_RING_ID 0x08 42 #define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31)) 43 #define XGENE_DMA_RING_ID_BUF 0x0C 44 #define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21)) 45 #define XGENE_DMA_RING_THRESLD0_SET1 0x30 46 #define XGENE_DMA_RING_THRESLD0_SET1_VAL 0X64 47 #define XGENE_DMA_RING_THRESLD1_SET1 0x34 48 #define XGENE_DMA_RING_THRESLD1_SET1_VAL 0xC8 49 #define XGENE_DMA_RING_HYSTERESIS 0x68 50 #define XGENE_DMA_RING_HYSTERESIS_VAL 0xFFFFFFFF 51 #define XGENE_DMA_RING_STATE 0x6C 52 #define XGENE_DMA_RING_STATE_WR_BASE 0x70 53 #define XGENE_DMA_RING_NE_INT_MODE 0x017C 54 #define XGENE_DMA_RING_NE_INT_MODE_SET(m, v) \ 55 ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v))) 56 #define XGENE_DMA_RING_NE_INT_MODE_RESET(m, v) \ 57 ((m) &= (~BIT(31 - (v)))) 58 #define XGENE_DMA_RING_CLKEN 0xC208 59 #define XGENE_DMA_RING_SRST 0xC200 60 #define XGENE_DMA_RING_MEM_RAM_SHUTDOWN 0xD070 61 #define XGENE_DMA_RING_BLK_MEM_RDY 0xD074 62 #define XGENE_DMA_RING_BLK_MEM_RDY_VAL 0xFFFFFFFF 63 #define XGENE_DMA_RING_ID_GET(owner, num) (((owner) << 6) | (num)) 64 #define XGENE_DMA_RING_DST_ID(v) ((1 << 10) | (v)) 65 #define XGENE_DMA_RING_CMD_OFFSET 0x2C 66 #define XGENE_DMA_RING_CMD_BASE_OFFSET(v) ((v) << 6) 67 #define XGENE_DMA_RING_COHERENT_SET(m) \ 68 (((u32 *)(m))[2] |= BIT(4)) 69 #define XGENE_DMA_RING_ADDRL_SET(m, v) \ 70 (((u32 *)(m))[2] |= (((v) >> 8) << 5)) 71 #define XGENE_DMA_RING_ADDRH_SET(m, v) \ 72 (((u32 *)(m))[3] |= ((v) >> 35)) 73 #define XGENE_DMA_RING_ACCEPTLERR_SET(m) \ 74 (((u32 *)(m))[3] |= BIT(19)) 75 #define XGENE_DMA_RING_SIZE_SET(m, v) \ 76 (((u32 *)(m))[3] |= ((v) << 23)) 77 #define XGENE_DMA_RING_RECOMBBUF_SET(m) \ 78 (((u32 *)(m))[3] |= BIT(27)) 79 #define XGENE_DMA_RING_RECOMTIMEOUTL_SET(m) \ 80 (((u32 *)(m))[3] |= (0x7 << 28)) 81 #define XGENE_DMA_RING_RECOMTIMEOUTH_SET(m) \ 82 (((u32 *)(m))[4] |= 0x3) 83 #define XGENE_DMA_RING_SELTHRSH_SET(m) \ 84 (((u32 *)(m))[4] |= BIT(3)) 85 #define XGENE_DMA_RING_TYPE_SET(m, v) \ 86 (((u32 *)(m))[4] |= ((v) << 19)) 87 88 /* X-Gene DMA device csr registers and bit definitions */ 89 #define XGENE_DMA_IPBRR 0x0 90 #define XGENE_DMA_DEV_ID_RD(v) ((v) & 0x00000FFF) 91 #define XGENE_DMA_BUS_ID_RD(v) (((v) >> 12) & 3) 92 #define XGENE_DMA_REV_NO_RD(v) (((v) >> 14) & 3) 93 #define XGENE_DMA_GCR 0x10 94 #define XGENE_DMA_CH_SETUP(v) \ 95 ((v) = ((v) & ~0x000FFFFF) | 0x000AAFFF) 96 #define XGENE_DMA_ENABLE(v) ((v) |= BIT(31)) 97 #define XGENE_DMA_DISABLE(v) ((v) &= ~BIT(31)) 98 #define XGENE_DMA_RAID6_CONT 0x14 99 #define XGENE_DMA_RAID6_MULTI_CTRL(v) ((v) << 24) 100 #define XGENE_DMA_INT 0x70 101 #define XGENE_DMA_INT_MASK 0x74 102 #define XGENE_DMA_INT_ALL_MASK 0xFFFFFFFF 103 #define XGENE_DMA_INT_ALL_UNMASK 0x0 104 #define XGENE_DMA_INT_MASK_SHIFT 0x14 105 #define XGENE_DMA_RING_INT0_MASK 0x90A0 106 #define XGENE_DMA_RING_INT1_MASK 0x90A8 107 #define XGENE_DMA_RING_INT2_MASK 0x90B0 108 #define XGENE_DMA_RING_INT3_MASK 0x90B8 109 #define XGENE_DMA_RING_INT4_MASK 0x90C0 110 #define XGENE_DMA_CFG_RING_WQ_ASSOC 0x90E0 111 #define XGENE_DMA_ASSOC_RING_MNGR1 0xFFFFFFFF 112 #define XGENE_DMA_MEM_RAM_SHUTDOWN 0xD070 113 #define XGENE_DMA_BLK_MEM_RDY 0xD074 114 #define XGENE_DMA_BLK_MEM_RDY_VAL 0xFFFFFFFF 115 #define XGENE_DMA_RING_CMD_SM_OFFSET 0x8000 116 117 /* X-Gene SoC EFUSE csr register and bit defination */ 118 #define XGENE_SOC_JTAG1_SHADOW 0x18 119 #define XGENE_DMA_PQ_DISABLE_MASK BIT(13) 120 121 /* X-Gene DMA Descriptor format */ 122 #define XGENE_DMA_DESC_NV_BIT BIT_ULL(50) 123 #define XGENE_DMA_DESC_IN_BIT BIT_ULL(55) 124 #define XGENE_DMA_DESC_C_BIT BIT_ULL(63) 125 #define XGENE_DMA_DESC_DR_BIT BIT_ULL(61) 126 #define XGENE_DMA_DESC_ELERR_POS 46 127 #define XGENE_DMA_DESC_RTYPE_POS 56 128 #define XGENE_DMA_DESC_LERR_POS 60 129 #define XGENE_DMA_DESC_BUFLEN_POS 48 130 #define XGENE_DMA_DESC_HOENQ_NUM_POS 48 131 #define XGENE_DMA_DESC_ELERR_RD(m) \ 132 (((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3) 133 #define XGENE_DMA_DESC_LERR_RD(m) \ 134 (((m) >> XGENE_DMA_DESC_LERR_POS) & 0x7) 135 #define XGENE_DMA_DESC_STATUS(elerr, lerr) \ 136 (((elerr) << 4) | (lerr)) 137 138 /* X-Gene DMA descriptor empty s/w signature */ 139 #define XGENE_DMA_DESC_EMPTY_SIGNATURE ~0ULL 140 141 /* X-Gene DMA configurable parameters defines */ 142 #define XGENE_DMA_RING_NUM 512 143 #define XGENE_DMA_BUFNUM 0x0 144 #define XGENE_DMA_CPU_BUFNUM 0x18 145 #define XGENE_DMA_RING_OWNER_DMA 0x03 146 #define XGENE_DMA_RING_OWNER_CPU 0x0F 147 #define XGENE_DMA_RING_TYPE_REGULAR 0x01 148 #define XGENE_DMA_RING_WQ_DESC_SIZE 32 /* 32 Bytes */ 149 #define XGENE_DMA_RING_NUM_CONFIG 5 150 #define XGENE_DMA_MAX_CHANNEL 4 151 #define XGENE_DMA_XOR_CHANNEL 0 152 #define XGENE_DMA_PQ_CHANNEL 1 153 #define XGENE_DMA_MAX_BYTE_CNT 0x4000 /* 16 KB */ 154 #define XGENE_DMA_MAX_64B_DESC_BYTE_CNT 0x14000 /* 80 KB */ 155 #define XGENE_DMA_MAX_XOR_SRC 5 156 #define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0 157 #define XGENE_DMA_INVALID_LEN_CODE 0x7800000000000000ULL 158 159 /* X-Gene DMA descriptor error codes */ 160 #define ERR_DESC_AXI 0x01 161 #define ERR_BAD_DESC 0x02 162 #define ERR_READ_DATA_AXI 0x03 163 #define ERR_WRITE_DATA_AXI 0x04 164 #define ERR_FBP_TIMEOUT 0x05 165 #define ERR_ECC 0x06 166 #define ERR_DIFF_SIZE 0x08 167 #define ERR_SCT_GAT_LEN 0x09 168 #define ERR_CRC_ERR 0x11 169 #define ERR_CHKSUM 0x12 170 #define ERR_DIF 0x13 171 172 /* X-Gene DMA error interrupt codes */ 173 #define ERR_DIF_SIZE_INT 0x0 174 #define ERR_GS_ERR_INT 0x1 175 #define ERR_FPB_TIMEO_INT 0x2 176 #define ERR_WFIFO_OVF_INT 0x3 177 #define ERR_RFIFO_OVF_INT 0x4 178 #define ERR_WR_TIMEO_INT 0x5 179 #define ERR_RD_TIMEO_INT 0x6 180 #define ERR_WR_ERR_INT 0x7 181 #define ERR_RD_ERR_INT 0x8 182 #define ERR_BAD_DESC_INT 0x9 183 #define ERR_DESC_DST_INT 0xA 184 #define ERR_DESC_SRC_INT 0xB 185 186 /* X-Gene DMA flyby operation code */ 187 #define FLYBY_2SRC_XOR 0x80 188 #define FLYBY_3SRC_XOR 0x90 189 #define FLYBY_4SRC_XOR 0xA0 190 #define FLYBY_5SRC_XOR 0xB0 191 192 /* X-Gene DMA SW descriptor flags */ 193 #define XGENE_DMA_FLAG_64B_DESC BIT(0) 194 195 /* Define to dump X-Gene DMA descriptor */ 196 #define XGENE_DMA_DESC_DUMP(desc, m) \ 197 print_hex_dump(KERN_ERR, (m), \ 198 DUMP_PREFIX_ADDRESS, 16, 8, (desc), 32, 0) 199 200 #define to_dma_desc_sw(tx) \ 201 container_of(tx, struct xgene_dma_desc_sw, tx) 202 #define to_dma_chan(dchan) \ 203 container_of(dchan, struct xgene_dma_chan, dma_chan) 204 205 #define chan_dbg(chan, fmt, arg...) \ 206 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg) 207 #define chan_err(chan, fmt, arg...) \ 208 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg) 209 210 struct xgene_dma_desc_hw { 211 __le64 m0; 212 __le64 m1; 213 __le64 m2; 214 __le64 m3; 215 }; 216 217 enum xgene_dma_ring_cfgsize { 218 XGENE_DMA_RING_CFG_SIZE_512B, 219 XGENE_DMA_RING_CFG_SIZE_2KB, 220 XGENE_DMA_RING_CFG_SIZE_16KB, 221 XGENE_DMA_RING_CFG_SIZE_64KB, 222 XGENE_DMA_RING_CFG_SIZE_512KB, 223 XGENE_DMA_RING_CFG_SIZE_INVALID 224 }; 225 226 struct xgene_dma_ring { 227 struct xgene_dma *pdma; 228 u8 buf_num; 229 u16 id; 230 u16 num; 231 u16 head; 232 u16 owner; 233 u16 slots; 234 u16 dst_ring_num; 235 u32 size; 236 void __iomem *cmd; 237 void __iomem *cmd_base; 238 dma_addr_t desc_paddr; 239 u32 state[XGENE_DMA_RING_NUM_CONFIG]; 240 enum xgene_dma_ring_cfgsize cfgsize; 241 union { 242 void *desc_vaddr; 243 struct xgene_dma_desc_hw *desc_hw; 244 }; 245 }; 246 247 struct xgene_dma_desc_sw { 248 struct xgene_dma_desc_hw desc1; 249 struct xgene_dma_desc_hw desc2; 250 u32 flags; 251 struct list_head node; 252 struct list_head tx_list; 253 struct dma_async_tx_descriptor tx; 254 }; 255 256 /** 257 * struct xgene_dma_chan - internal representation of an X-Gene DMA channel 258 * @dma_chan: dmaengine channel object member 259 * @pdma: X-Gene DMA device structure reference 260 * @dev: struct device reference for dma mapping api 261 * @id: raw id of this channel 262 * @rx_irq: channel IRQ 263 * @name: name of X-Gene DMA channel 264 * @lock: serializes enqueue/dequeue operations to the descriptor pool 265 * @pending: number of transaction request pushed to DMA controller for 266 * execution, but still waiting for completion, 267 * @max_outstanding: max number of outstanding request we can push to channel 268 * @ld_pending: descriptors which are queued to run, but have not yet been 269 * submitted to the hardware for execution 270 * @ld_running: descriptors which are currently being executing by the hardware 271 * @ld_completed: descriptors which have finished execution by the hardware. 272 * These descriptors have already had their cleanup actions run. They 273 * are waiting for the ACK bit to be set by the async tx API. 274 * @desc_pool: descriptor pool for DMA operations 275 * @tasklet: bottom half where all completed descriptors cleans 276 * @tx_ring: transmit ring descriptor that we use to prepare actual 277 * descriptors for further executions 278 * @rx_ring: receive ring descriptor that we use to get completed DMA 279 * descriptors during cleanup time 280 */ 281 struct xgene_dma_chan { 282 struct dma_chan dma_chan; 283 struct xgene_dma *pdma; 284 struct device *dev; 285 int id; 286 int rx_irq; 287 char name[10]; 288 spinlock_t lock; 289 int pending; 290 int max_outstanding; 291 struct list_head ld_pending; 292 struct list_head ld_running; 293 struct list_head ld_completed; 294 struct dma_pool *desc_pool; 295 struct tasklet_struct tasklet; 296 struct xgene_dma_ring tx_ring; 297 struct xgene_dma_ring rx_ring; 298 }; 299 300 /** 301 * struct xgene_dma - internal representation of an X-Gene DMA device 302 * @err_irq: DMA error irq number 303 * @ring_num: start id number for DMA ring 304 * @csr_dma: base for DMA register access 305 * @csr_ring: base for DMA ring register access 306 * @csr_ring_cmd: base for DMA ring command register access 307 * @csr_efuse: base for efuse register access 308 * @dma_dev: embedded struct dma_device 309 * @chan: reference to X-Gene DMA channels 310 */ 311 struct xgene_dma { 312 struct device *dev; 313 struct clk *clk; 314 int err_irq; 315 int ring_num; 316 void __iomem *csr_dma; 317 void __iomem *csr_ring; 318 void __iomem *csr_ring_cmd; 319 void __iomem *csr_efuse; 320 struct dma_device dma_dev[XGENE_DMA_MAX_CHANNEL]; 321 struct xgene_dma_chan chan[XGENE_DMA_MAX_CHANNEL]; 322 }; 323 324 static const char * const xgene_dma_desc_err[] = { 325 [ERR_DESC_AXI] = "AXI error when reading src/dst link list", 326 [ERR_BAD_DESC] = "ERR or El_ERR fields not set to zero in desc", 327 [ERR_READ_DATA_AXI] = "AXI error when reading data", 328 [ERR_WRITE_DATA_AXI] = "AXI error when writing data", 329 [ERR_FBP_TIMEOUT] = "Timeout on bufpool fetch", 330 [ERR_ECC] = "ECC double bit error", 331 [ERR_DIFF_SIZE] = "Bufpool too small to hold all the DIF result", 332 [ERR_SCT_GAT_LEN] = "Gather and scatter data length not same", 333 [ERR_CRC_ERR] = "CRC error", 334 [ERR_CHKSUM] = "Checksum error", 335 [ERR_DIF] = "DIF error", 336 }; 337 338 static const char * const xgene_dma_err[] = { 339 [ERR_DIF_SIZE_INT] = "DIF size error", 340 [ERR_GS_ERR_INT] = "Gather scatter not same size error", 341 [ERR_FPB_TIMEO_INT] = "Free pool time out error", 342 [ERR_WFIFO_OVF_INT] = "Write FIFO over flow error", 343 [ERR_RFIFO_OVF_INT] = "Read FIFO over flow error", 344 [ERR_WR_TIMEO_INT] = "Write time out error", 345 [ERR_RD_TIMEO_INT] = "Read time out error", 346 [ERR_WR_ERR_INT] = "HBF bus write error", 347 [ERR_RD_ERR_INT] = "HBF bus read error", 348 [ERR_BAD_DESC_INT] = "Ring descriptor HE0 not set error", 349 [ERR_DESC_DST_INT] = "HFB reading dst link address error", 350 [ERR_DESC_SRC_INT] = "HFB reading src link address error", 351 }; 352 353 static bool is_pq_enabled(struct xgene_dma *pdma) 354 { 355 u32 val; 356 357 val = ioread32(pdma->csr_efuse + XGENE_SOC_JTAG1_SHADOW); 358 return !(val & XGENE_DMA_PQ_DISABLE_MASK); 359 } 360 361 static u64 xgene_dma_encode_len(size_t len) 362 { 363 return (len < XGENE_DMA_MAX_BYTE_CNT) ? 364 ((u64)len << XGENE_DMA_DESC_BUFLEN_POS) : 365 XGENE_DMA_16K_BUFFER_LEN_CODE; 366 } 367 368 static u8 xgene_dma_encode_xor_flyby(u32 src_cnt) 369 { 370 static u8 flyby_type[] = { 371 FLYBY_2SRC_XOR, /* Dummy */ 372 FLYBY_2SRC_XOR, /* Dummy */ 373 FLYBY_2SRC_XOR, 374 FLYBY_3SRC_XOR, 375 FLYBY_4SRC_XOR, 376 FLYBY_5SRC_XOR 377 }; 378 379 return flyby_type[src_cnt]; 380 } 381 382 static void xgene_dma_set_src_buffer(__le64 *ext8, size_t *len, 383 dma_addr_t *paddr) 384 { 385 size_t nbytes = (*len < XGENE_DMA_MAX_BYTE_CNT) ? 386 *len : XGENE_DMA_MAX_BYTE_CNT; 387 388 *ext8 |= cpu_to_le64(*paddr); 389 *ext8 |= cpu_to_le64(xgene_dma_encode_len(nbytes)); 390 *len -= nbytes; 391 *paddr += nbytes; 392 } 393 394 static void xgene_dma_invalidate_buffer(__le64 *ext8) 395 { 396 *ext8 |= cpu_to_le64(XGENE_DMA_INVALID_LEN_CODE); 397 } 398 399 static __le64 *xgene_dma_lookup_ext8(struct xgene_dma_desc_hw *desc, int idx) 400 { 401 switch (idx) { 402 case 0: 403 return &desc->m1; 404 case 1: 405 return &desc->m0; 406 case 2: 407 return &desc->m3; 408 case 3: 409 return &desc->m2; 410 default: 411 pr_err("Invalid dma descriptor index\n"); 412 } 413 414 return NULL; 415 } 416 417 static void xgene_dma_init_desc(struct xgene_dma_desc_hw *desc, 418 u16 dst_ring_num) 419 { 420 desc->m0 |= cpu_to_le64(XGENE_DMA_DESC_IN_BIT); 421 desc->m0 |= cpu_to_le64((u64)XGENE_DMA_RING_OWNER_DMA << 422 XGENE_DMA_DESC_RTYPE_POS); 423 desc->m1 |= cpu_to_le64(XGENE_DMA_DESC_C_BIT); 424 desc->m3 |= cpu_to_le64((u64)dst_ring_num << 425 XGENE_DMA_DESC_HOENQ_NUM_POS); 426 } 427 428 static void xgene_dma_prep_cpy_desc(struct xgene_dma_chan *chan, 429 struct xgene_dma_desc_sw *desc_sw, 430 dma_addr_t dst, dma_addr_t src, 431 size_t len) 432 { 433 struct xgene_dma_desc_hw *desc1, *desc2; 434 int i; 435 436 /* Get 1st descriptor */ 437 desc1 = &desc_sw->desc1; 438 xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num); 439 440 /* Set destination address */ 441 desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT); 442 desc1->m3 |= cpu_to_le64(dst); 443 444 /* Set 1st source address */ 445 xgene_dma_set_src_buffer(&desc1->m1, &len, &src); 446 447 if (!len) 448 return; 449 450 /* 451 * We need to split this source buffer, 452 * and need to use 2nd descriptor 453 */ 454 desc2 = &desc_sw->desc2; 455 desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT); 456 457 /* Set 2nd to 5th source address */ 458 for (i = 0; i < 4 && len; i++) 459 xgene_dma_set_src_buffer(xgene_dma_lookup_ext8(desc2, i), 460 &len, &src); 461 462 /* Invalidate unused source address field */ 463 for (; i < 4; i++) 464 xgene_dma_invalidate_buffer(xgene_dma_lookup_ext8(desc2, i)); 465 466 /* Updated flag that we have prepared 64B descriptor */ 467 desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC; 468 } 469 470 static void xgene_dma_prep_xor_desc(struct xgene_dma_chan *chan, 471 struct xgene_dma_desc_sw *desc_sw, 472 dma_addr_t *dst, dma_addr_t *src, 473 u32 src_cnt, size_t *nbytes, 474 const u8 *scf) 475 { 476 struct xgene_dma_desc_hw *desc1, *desc2; 477 size_t len = *nbytes; 478 int i; 479 480 desc1 = &desc_sw->desc1; 481 desc2 = &desc_sw->desc2; 482 483 /* Initialize DMA descriptor */ 484 xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num); 485 486 /* Set destination address */ 487 desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT); 488 desc1->m3 |= cpu_to_le64(*dst); 489 490 /* We have multiple source addresses, so need to set NV bit*/ 491 desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT); 492 493 /* Set flyby opcode */ 494 desc1->m2 |= cpu_to_le64(xgene_dma_encode_xor_flyby(src_cnt)); 495 496 /* Set 1st to 5th source addresses */ 497 for (i = 0; i < src_cnt; i++) { 498 len = *nbytes; 499 xgene_dma_set_src_buffer((i == 0) ? &desc1->m1 : 500 xgene_dma_lookup_ext8(desc2, i - 1), 501 &len, &src[i]); 502 desc1->m2 |= cpu_to_le64((scf[i] << ((i + 1) * 8))); 503 } 504 505 /* Update meta data */ 506 *nbytes = len; 507 *dst += XGENE_DMA_MAX_BYTE_CNT; 508 509 /* We need always 64B descriptor to perform xor or pq operations */ 510 desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC; 511 } 512 513 static dma_cookie_t xgene_dma_tx_submit(struct dma_async_tx_descriptor *tx) 514 { 515 struct xgene_dma_desc_sw *desc; 516 struct xgene_dma_chan *chan; 517 dma_cookie_t cookie; 518 519 if (unlikely(!tx)) 520 return -EINVAL; 521 522 chan = to_dma_chan(tx->chan); 523 desc = to_dma_desc_sw(tx); 524 525 spin_lock_bh(&chan->lock); 526 527 cookie = dma_cookie_assign(tx); 528 529 /* Add this transaction list onto the tail of the pending queue */ 530 list_splice_tail_init(&desc->tx_list, &chan->ld_pending); 531 532 spin_unlock_bh(&chan->lock); 533 534 return cookie; 535 } 536 537 static void xgene_dma_clean_descriptor(struct xgene_dma_chan *chan, 538 struct xgene_dma_desc_sw *desc) 539 { 540 list_del(&desc->node); 541 chan_dbg(chan, "LD %p free\n", desc); 542 dma_pool_free(chan->desc_pool, desc, desc->tx.phys); 543 } 544 545 static struct xgene_dma_desc_sw *xgene_dma_alloc_descriptor( 546 struct xgene_dma_chan *chan) 547 { 548 struct xgene_dma_desc_sw *desc; 549 dma_addr_t phys; 550 551 desc = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys); 552 if (!desc) { 553 chan_err(chan, "Failed to allocate LDs\n"); 554 return NULL; 555 } 556 557 INIT_LIST_HEAD(&desc->tx_list); 558 desc->tx.phys = phys; 559 desc->tx.tx_submit = xgene_dma_tx_submit; 560 dma_async_tx_descriptor_init(&desc->tx, &chan->dma_chan); 561 562 chan_dbg(chan, "LD %p allocated\n", desc); 563 564 return desc; 565 } 566 567 /** 568 * xgene_dma_clean_completed_descriptor - free all descriptors which 569 * has been completed and acked 570 * @chan: X-Gene DMA channel 571 * 572 * This function is used on all completed and acked descriptors. 573 */ 574 static void xgene_dma_clean_completed_descriptor(struct xgene_dma_chan *chan) 575 { 576 struct xgene_dma_desc_sw *desc, *_desc; 577 578 /* Run the callback for each descriptor, in order */ 579 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) { 580 if (async_tx_test_ack(&desc->tx)) 581 xgene_dma_clean_descriptor(chan, desc); 582 } 583 } 584 585 /** 586 * xgene_dma_run_tx_complete_actions - cleanup a single link descriptor 587 * @chan: X-Gene DMA channel 588 * @desc: descriptor to cleanup and free 589 * 590 * This function is used on a descriptor which has been executed by the DMA 591 * controller. It will run any callbacks, submit any dependencies. 592 */ 593 static void xgene_dma_run_tx_complete_actions(struct xgene_dma_chan *chan, 594 struct xgene_dma_desc_sw *desc) 595 { 596 struct dma_async_tx_descriptor *tx = &desc->tx; 597 598 /* 599 * If this is not the last transaction in the group, 600 * then no need to complete cookie and run any callback as 601 * this is not the tx_descriptor which had been sent to caller 602 * of this DMA request 603 */ 604 605 if (tx->cookie == 0) 606 return; 607 608 dma_cookie_complete(tx); 609 610 /* Run the link descriptor callback function */ 611 dmaengine_desc_get_callback_invoke(tx, NULL); 612 613 dma_descriptor_unmap(tx); 614 615 /* Run any dependencies */ 616 dma_run_dependencies(tx); 617 } 618 619 /** 620 * xgene_dma_clean_running_descriptor - move the completed descriptor from 621 * ld_running to ld_completed 622 * @chan: X-Gene DMA channel 623 * @desc: the descriptor which is completed 624 * 625 * Free the descriptor directly if acked by async_tx api, 626 * else move it to queue ld_completed. 627 */ 628 static void xgene_dma_clean_running_descriptor(struct xgene_dma_chan *chan, 629 struct xgene_dma_desc_sw *desc) 630 { 631 /* Remove from the list of running transactions */ 632 list_del(&desc->node); 633 634 /* 635 * the client is allowed to attach dependent operations 636 * until 'ack' is set 637 */ 638 if (!async_tx_test_ack(&desc->tx)) { 639 /* 640 * Move this descriptor to the list of descriptors which is 641 * completed, but still awaiting the 'ack' bit to be set. 642 */ 643 list_add_tail(&desc->node, &chan->ld_completed); 644 return; 645 } 646 647 chan_dbg(chan, "LD %p free\n", desc); 648 dma_pool_free(chan->desc_pool, desc, desc->tx.phys); 649 } 650 651 static void xgene_chan_xfer_request(struct xgene_dma_chan *chan, 652 struct xgene_dma_desc_sw *desc_sw) 653 { 654 struct xgene_dma_ring *ring = &chan->tx_ring; 655 struct xgene_dma_desc_hw *desc_hw; 656 657 /* Get hw descriptor from DMA tx ring */ 658 desc_hw = &ring->desc_hw[ring->head]; 659 660 /* 661 * Increment the head count to point next 662 * descriptor for next time 663 */ 664 if (++ring->head == ring->slots) 665 ring->head = 0; 666 667 /* Copy prepared sw descriptor data to hw descriptor */ 668 memcpy(desc_hw, &desc_sw->desc1, sizeof(*desc_hw)); 669 670 /* 671 * Check if we have prepared 64B descriptor, 672 * in this case we need one more hw descriptor 673 */ 674 if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) { 675 desc_hw = &ring->desc_hw[ring->head]; 676 677 if (++ring->head == ring->slots) 678 ring->head = 0; 679 680 memcpy(desc_hw, &desc_sw->desc2, sizeof(*desc_hw)); 681 } 682 683 /* Increment the pending transaction count */ 684 chan->pending += ((desc_sw->flags & 685 XGENE_DMA_FLAG_64B_DESC) ? 2 : 1); 686 687 /* Notify the hw that we have descriptor ready for execution */ 688 iowrite32((desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) ? 689 2 : 1, ring->cmd); 690 } 691 692 /** 693 * xgene_chan_xfer_ld_pending - push any pending transactions to hw 694 * @chan : X-Gene DMA channel 695 * 696 * LOCKING: must hold chan->lock 697 */ 698 static void xgene_chan_xfer_ld_pending(struct xgene_dma_chan *chan) 699 { 700 struct xgene_dma_desc_sw *desc_sw, *_desc_sw; 701 702 /* 703 * If the list of pending descriptors is empty, then we 704 * don't need to do any work at all 705 */ 706 if (list_empty(&chan->ld_pending)) { 707 chan_dbg(chan, "No pending LDs\n"); 708 return; 709 } 710 711 /* 712 * Move elements from the queue of pending transactions onto the list 713 * of running transactions and push it to hw for further executions 714 */ 715 list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_pending, node) { 716 /* 717 * Check if have pushed max number of transactions to hw 718 * as capable, so let's stop here and will push remaining 719 * elements from pening ld queue after completing some 720 * descriptors that we have already pushed 721 */ 722 if (chan->pending >= chan->max_outstanding) 723 return; 724 725 xgene_chan_xfer_request(chan, desc_sw); 726 727 /* 728 * Delete this element from ld pending queue and append it to 729 * ld running queue 730 */ 731 list_move_tail(&desc_sw->node, &chan->ld_running); 732 } 733 } 734 735 /** 736 * xgene_dma_cleanup_descriptors - cleanup link descriptors which are completed 737 * and move them to ld_completed to free until flag 'ack' is set 738 * @chan: X-Gene DMA channel 739 * 740 * This function is used on descriptors which have been executed by the DMA 741 * controller. It will run any callbacks, submit any dependencies, then 742 * free these descriptors if flag 'ack' is set. 743 */ 744 static void xgene_dma_cleanup_descriptors(struct xgene_dma_chan *chan) 745 { 746 struct xgene_dma_ring *ring = &chan->rx_ring; 747 struct xgene_dma_desc_sw *desc_sw, *_desc_sw; 748 struct xgene_dma_desc_hw *desc_hw; 749 struct list_head ld_completed; 750 u8 status; 751 752 INIT_LIST_HEAD(&ld_completed); 753 754 spin_lock_bh(&chan->lock); 755 756 /* Clean already completed and acked descriptors */ 757 xgene_dma_clean_completed_descriptor(chan); 758 759 /* Move all completed descriptors to ld completed queue, in order */ 760 list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_running, node) { 761 /* Get subsequent hw descriptor from DMA rx ring */ 762 desc_hw = &ring->desc_hw[ring->head]; 763 764 /* Check if this descriptor has been completed */ 765 if (unlikely(le64_to_cpu(desc_hw->m0) == 766 XGENE_DMA_DESC_EMPTY_SIGNATURE)) 767 break; 768 769 if (++ring->head == ring->slots) 770 ring->head = 0; 771 772 /* Check if we have any error with DMA transactions */ 773 status = XGENE_DMA_DESC_STATUS( 774 XGENE_DMA_DESC_ELERR_RD(le64_to_cpu( 775 desc_hw->m0)), 776 XGENE_DMA_DESC_LERR_RD(le64_to_cpu( 777 desc_hw->m0))); 778 if (status) { 779 /* Print the DMA error type */ 780 chan_err(chan, "%s\n", xgene_dma_desc_err[status]); 781 782 /* 783 * We have DMA transactions error here. Dump DMA Tx 784 * and Rx descriptors for this request */ 785 XGENE_DMA_DESC_DUMP(&desc_sw->desc1, 786 "X-Gene DMA TX DESC1: "); 787 788 if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) 789 XGENE_DMA_DESC_DUMP(&desc_sw->desc2, 790 "X-Gene DMA TX DESC2: "); 791 792 XGENE_DMA_DESC_DUMP(desc_hw, 793 "X-Gene DMA RX ERR DESC: "); 794 } 795 796 /* Notify the hw about this completed descriptor */ 797 iowrite32(-1, ring->cmd); 798 799 /* Mark this hw descriptor as processed */ 800 desc_hw->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE); 801 802 /* 803 * Decrement the pending transaction count 804 * as we have processed one 805 */ 806 chan->pending -= ((desc_sw->flags & 807 XGENE_DMA_FLAG_64B_DESC) ? 2 : 1); 808 809 /* 810 * Delete this node from ld running queue and append it to 811 * ld completed queue for further processing 812 */ 813 list_move_tail(&desc_sw->node, &ld_completed); 814 } 815 816 /* 817 * Start any pending transactions automatically 818 * In the ideal case, we keep the DMA controller busy while we go 819 * ahead and free the descriptors below. 820 */ 821 xgene_chan_xfer_ld_pending(chan); 822 823 spin_unlock_bh(&chan->lock); 824 825 /* Run the callback for each descriptor, in order */ 826 list_for_each_entry_safe(desc_sw, _desc_sw, &ld_completed, node) { 827 xgene_dma_run_tx_complete_actions(chan, desc_sw); 828 xgene_dma_clean_running_descriptor(chan, desc_sw); 829 } 830 } 831 832 static int xgene_dma_alloc_chan_resources(struct dma_chan *dchan) 833 { 834 struct xgene_dma_chan *chan = to_dma_chan(dchan); 835 836 /* Has this channel already been allocated? */ 837 if (chan->desc_pool) 838 return 1; 839 840 chan->desc_pool = dma_pool_create(chan->name, chan->dev, 841 sizeof(struct xgene_dma_desc_sw), 842 0, 0); 843 if (!chan->desc_pool) { 844 chan_err(chan, "Failed to allocate descriptor pool\n"); 845 return -ENOMEM; 846 } 847 848 chan_dbg(chan, "Allocate descripto pool\n"); 849 850 return 1; 851 } 852 853 /** 854 * xgene_dma_free_desc_list - Free all descriptors in a queue 855 * @chan: X-Gene DMA channel 856 * @list: the list to free 857 * 858 * LOCKING: must hold chan->lock 859 */ 860 static void xgene_dma_free_desc_list(struct xgene_dma_chan *chan, 861 struct list_head *list) 862 { 863 struct xgene_dma_desc_sw *desc, *_desc; 864 865 list_for_each_entry_safe(desc, _desc, list, node) 866 xgene_dma_clean_descriptor(chan, desc); 867 } 868 869 static void xgene_dma_free_chan_resources(struct dma_chan *dchan) 870 { 871 struct xgene_dma_chan *chan = to_dma_chan(dchan); 872 873 chan_dbg(chan, "Free all resources\n"); 874 875 if (!chan->desc_pool) 876 return; 877 878 /* Process all running descriptor */ 879 xgene_dma_cleanup_descriptors(chan); 880 881 spin_lock_bh(&chan->lock); 882 883 /* Clean all link descriptor queues */ 884 xgene_dma_free_desc_list(chan, &chan->ld_pending); 885 xgene_dma_free_desc_list(chan, &chan->ld_running); 886 xgene_dma_free_desc_list(chan, &chan->ld_completed); 887 888 spin_unlock_bh(&chan->lock); 889 890 /* Delete this channel DMA pool */ 891 dma_pool_destroy(chan->desc_pool); 892 chan->desc_pool = NULL; 893 } 894 895 static struct dma_async_tx_descriptor *xgene_dma_prep_sg( 896 struct dma_chan *dchan, struct scatterlist *dst_sg, 897 u32 dst_nents, struct scatterlist *src_sg, 898 u32 src_nents, unsigned long flags) 899 { 900 struct xgene_dma_desc_sw *first = NULL, *new = NULL; 901 struct xgene_dma_chan *chan; 902 size_t dst_avail, src_avail; 903 dma_addr_t dst, src; 904 size_t len; 905 906 if (unlikely(!dchan)) 907 return NULL; 908 909 if (unlikely(!dst_nents || !src_nents)) 910 return NULL; 911 912 if (unlikely(!dst_sg || !src_sg)) 913 return NULL; 914 915 chan = to_dma_chan(dchan); 916 917 /* Get prepared for the loop */ 918 dst_avail = sg_dma_len(dst_sg); 919 src_avail = sg_dma_len(src_sg); 920 dst_nents--; 921 src_nents--; 922 923 /* Run until we are out of scatterlist entries */ 924 while (true) { 925 /* Create the largest transaction possible */ 926 len = min_t(size_t, src_avail, dst_avail); 927 len = min_t(size_t, len, XGENE_DMA_MAX_64B_DESC_BYTE_CNT); 928 if (len == 0) 929 goto fetch; 930 931 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail; 932 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail; 933 934 /* Allocate the link descriptor from DMA pool */ 935 new = xgene_dma_alloc_descriptor(chan); 936 if (!new) 937 goto fail; 938 939 /* Prepare DMA descriptor */ 940 xgene_dma_prep_cpy_desc(chan, new, dst, src, len); 941 942 if (!first) 943 first = new; 944 945 new->tx.cookie = 0; 946 async_tx_ack(&new->tx); 947 948 /* update metadata */ 949 dst_avail -= len; 950 src_avail -= len; 951 952 /* Insert the link descriptor to the LD ring */ 953 list_add_tail(&new->node, &first->tx_list); 954 955 fetch: 956 /* fetch the next dst scatterlist entry */ 957 if (dst_avail == 0) { 958 /* no more entries: we're done */ 959 if (dst_nents == 0) 960 break; 961 962 /* fetch the next entry: if there are no more: done */ 963 dst_sg = sg_next(dst_sg); 964 if (!dst_sg) 965 break; 966 967 dst_nents--; 968 dst_avail = sg_dma_len(dst_sg); 969 } 970 971 /* fetch the next src scatterlist entry */ 972 if (src_avail == 0) { 973 /* no more entries: we're done */ 974 if (src_nents == 0) 975 break; 976 977 /* fetch the next entry: if there are no more: done */ 978 src_sg = sg_next(src_sg); 979 if (!src_sg) 980 break; 981 982 src_nents--; 983 src_avail = sg_dma_len(src_sg); 984 } 985 } 986 987 if (!new) 988 return NULL; 989 990 new->tx.flags = flags; /* client is in control of this ack */ 991 new->tx.cookie = -EBUSY; 992 list_splice(&first->tx_list, &new->tx_list); 993 994 return &new->tx; 995 fail: 996 if (!first) 997 return NULL; 998 999 xgene_dma_free_desc_list(chan, &first->tx_list); 1000 return NULL; 1001 } 1002 1003 static struct dma_async_tx_descriptor *xgene_dma_prep_xor( 1004 struct dma_chan *dchan, dma_addr_t dst, dma_addr_t *src, 1005 u32 src_cnt, size_t len, unsigned long flags) 1006 { 1007 struct xgene_dma_desc_sw *first = NULL, *new; 1008 struct xgene_dma_chan *chan; 1009 static u8 multi[XGENE_DMA_MAX_XOR_SRC] = { 1010 0x01, 0x01, 0x01, 0x01, 0x01}; 1011 1012 if (unlikely(!dchan || !len)) 1013 return NULL; 1014 1015 chan = to_dma_chan(dchan); 1016 1017 do { 1018 /* Allocate the link descriptor from DMA pool */ 1019 new = xgene_dma_alloc_descriptor(chan); 1020 if (!new) 1021 goto fail; 1022 1023 /* Prepare xor DMA descriptor */ 1024 xgene_dma_prep_xor_desc(chan, new, &dst, src, 1025 src_cnt, &len, multi); 1026 1027 if (!first) 1028 first = new; 1029 1030 new->tx.cookie = 0; 1031 async_tx_ack(&new->tx); 1032 1033 /* Insert the link descriptor to the LD ring */ 1034 list_add_tail(&new->node, &first->tx_list); 1035 } while (len); 1036 1037 new->tx.flags = flags; /* client is in control of this ack */ 1038 new->tx.cookie = -EBUSY; 1039 list_splice(&first->tx_list, &new->tx_list); 1040 1041 return &new->tx; 1042 1043 fail: 1044 if (!first) 1045 return NULL; 1046 1047 xgene_dma_free_desc_list(chan, &first->tx_list); 1048 return NULL; 1049 } 1050 1051 static struct dma_async_tx_descriptor *xgene_dma_prep_pq( 1052 struct dma_chan *dchan, dma_addr_t *dst, dma_addr_t *src, 1053 u32 src_cnt, const u8 *scf, size_t len, unsigned long flags) 1054 { 1055 struct xgene_dma_desc_sw *first = NULL, *new; 1056 struct xgene_dma_chan *chan; 1057 size_t _len = len; 1058 dma_addr_t _src[XGENE_DMA_MAX_XOR_SRC]; 1059 static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {0x01, 0x01, 0x01, 0x01, 0x01}; 1060 1061 if (unlikely(!dchan || !len)) 1062 return NULL; 1063 1064 chan = to_dma_chan(dchan); 1065 1066 /* 1067 * Save source addresses on local variable, may be we have to 1068 * prepare two descriptor to generate P and Q if both enabled 1069 * in the flags by client 1070 */ 1071 memcpy(_src, src, sizeof(*src) * src_cnt); 1072 1073 if (flags & DMA_PREP_PQ_DISABLE_P) 1074 len = 0; 1075 1076 if (flags & DMA_PREP_PQ_DISABLE_Q) 1077 _len = 0; 1078 1079 do { 1080 /* Allocate the link descriptor from DMA pool */ 1081 new = xgene_dma_alloc_descriptor(chan); 1082 if (!new) 1083 goto fail; 1084 1085 if (!first) 1086 first = new; 1087 1088 new->tx.cookie = 0; 1089 async_tx_ack(&new->tx); 1090 1091 /* Insert the link descriptor to the LD ring */ 1092 list_add_tail(&new->node, &first->tx_list); 1093 1094 /* 1095 * Prepare DMA descriptor to generate P, 1096 * if DMA_PREP_PQ_DISABLE_P flag is not set 1097 */ 1098 if (len) { 1099 xgene_dma_prep_xor_desc(chan, new, &dst[0], src, 1100 src_cnt, &len, multi); 1101 continue; 1102 } 1103 1104 /* 1105 * Prepare DMA descriptor to generate Q, 1106 * if DMA_PREP_PQ_DISABLE_Q flag is not set 1107 */ 1108 if (_len) { 1109 xgene_dma_prep_xor_desc(chan, new, &dst[1], _src, 1110 src_cnt, &_len, scf); 1111 } 1112 } while (len || _len); 1113 1114 new->tx.flags = flags; /* client is in control of this ack */ 1115 new->tx.cookie = -EBUSY; 1116 list_splice(&first->tx_list, &new->tx_list); 1117 1118 return &new->tx; 1119 1120 fail: 1121 if (!first) 1122 return NULL; 1123 1124 xgene_dma_free_desc_list(chan, &first->tx_list); 1125 return NULL; 1126 } 1127 1128 static void xgene_dma_issue_pending(struct dma_chan *dchan) 1129 { 1130 struct xgene_dma_chan *chan = to_dma_chan(dchan); 1131 1132 spin_lock_bh(&chan->lock); 1133 xgene_chan_xfer_ld_pending(chan); 1134 spin_unlock_bh(&chan->lock); 1135 } 1136 1137 static enum dma_status xgene_dma_tx_status(struct dma_chan *dchan, 1138 dma_cookie_t cookie, 1139 struct dma_tx_state *txstate) 1140 { 1141 return dma_cookie_status(dchan, cookie, txstate); 1142 } 1143 1144 static void xgene_dma_tasklet_cb(unsigned long data) 1145 { 1146 struct xgene_dma_chan *chan = (struct xgene_dma_chan *)data; 1147 1148 /* Run all cleanup for descriptors which have been completed */ 1149 xgene_dma_cleanup_descriptors(chan); 1150 1151 /* Re-enable DMA channel IRQ */ 1152 enable_irq(chan->rx_irq); 1153 } 1154 1155 static irqreturn_t xgene_dma_chan_ring_isr(int irq, void *id) 1156 { 1157 struct xgene_dma_chan *chan = (struct xgene_dma_chan *)id; 1158 1159 BUG_ON(!chan); 1160 1161 /* 1162 * Disable DMA channel IRQ until we process completed 1163 * descriptors 1164 */ 1165 disable_irq_nosync(chan->rx_irq); 1166 1167 /* 1168 * Schedule the tasklet to handle all cleanup of the current 1169 * transaction. It will start a new transaction if there is 1170 * one pending. 1171 */ 1172 tasklet_schedule(&chan->tasklet); 1173 1174 return IRQ_HANDLED; 1175 } 1176 1177 static irqreturn_t xgene_dma_err_isr(int irq, void *id) 1178 { 1179 struct xgene_dma *pdma = (struct xgene_dma *)id; 1180 unsigned long int_mask; 1181 u32 val, i; 1182 1183 val = ioread32(pdma->csr_dma + XGENE_DMA_INT); 1184 1185 /* Clear DMA interrupts */ 1186 iowrite32(val, pdma->csr_dma + XGENE_DMA_INT); 1187 1188 /* Print DMA error info */ 1189 int_mask = val >> XGENE_DMA_INT_MASK_SHIFT; 1190 for_each_set_bit(i, &int_mask, ARRAY_SIZE(xgene_dma_err)) 1191 dev_err(pdma->dev, 1192 "Interrupt status 0x%08X %s\n", val, xgene_dma_err[i]); 1193 1194 return IRQ_HANDLED; 1195 } 1196 1197 static void xgene_dma_wr_ring_state(struct xgene_dma_ring *ring) 1198 { 1199 int i; 1200 1201 iowrite32(ring->num, ring->pdma->csr_ring + XGENE_DMA_RING_STATE); 1202 1203 for (i = 0; i < XGENE_DMA_RING_NUM_CONFIG; i++) 1204 iowrite32(ring->state[i], ring->pdma->csr_ring + 1205 XGENE_DMA_RING_STATE_WR_BASE + (i * 4)); 1206 } 1207 1208 static void xgene_dma_clr_ring_state(struct xgene_dma_ring *ring) 1209 { 1210 memset(ring->state, 0, sizeof(u32) * XGENE_DMA_RING_NUM_CONFIG); 1211 xgene_dma_wr_ring_state(ring); 1212 } 1213 1214 static void xgene_dma_setup_ring(struct xgene_dma_ring *ring) 1215 { 1216 void *ring_cfg = ring->state; 1217 u64 addr = ring->desc_paddr; 1218 u32 i, val; 1219 1220 ring->slots = ring->size / XGENE_DMA_RING_WQ_DESC_SIZE; 1221 1222 /* Clear DMA ring state */ 1223 xgene_dma_clr_ring_state(ring); 1224 1225 /* Set DMA ring type */ 1226 XGENE_DMA_RING_TYPE_SET(ring_cfg, XGENE_DMA_RING_TYPE_REGULAR); 1227 1228 if (ring->owner == XGENE_DMA_RING_OWNER_DMA) { 1229 /* Set recombination buffer and timeout */ 1230 XGENE_DMA_RING_RECOMBBUF_SET(ring_cfg); 1231 XGENE_DMA_RING_RECOMTIMEOUTL_SET(ring_cfg); 1232 XGENE_DMA_RING_RECOMTIMEOUTH_SET(ring_cfg); 1233 } 1234 1235 /* Initialize DMA ring state */ 1236 XGENE_DMA_RING_SELTHRSH_SET(ring_cfg); 1237 XGENE_DMA_RING_ACCEPTLERR_SET(ring_cfg); 1238 XGENE_DMA_RING_COHERENT_SET(ring_cfg); 1239 XGENE_DMA_RING_ADDRL_SET(ring_cfg, addr); 1240 XGENE_DMA_RING_ADDRH_SET(ring_cfg, addr); 1241 XGENE_DMA_RING_SIZE_SET(ring_cfg, ring->cfgsize); 1242 1243 /* Write DMA ring configurations */ 1244 xgene_dma_wr_ring_state(ring); 1245 1246 /* Set DMA ring id */ 1247 iowrite32(XGENE_DMA_RING_ID_SETUP(ring->id), 1248 ring->pdma->csr_ring + XGENE_DMA_RING_ID); 1249 1250 /* Set DMA ring buffer */ 1251 iowrite32(XGENE_DMA_RING_ID_BUF_SETUP(ring->num), 1252 ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF); 1253 1254 if (ring->owner != XGENE_DMA_RING_OWNER_CPU) 1255 return; 1256 1257 /* Set empty signature to DMA Rx ring descriptors */ 1258 for (i = 0; i < ring->slots; i++) { 1259 struct xgene_dma_desc_hw *desc; 1260 1261 desc = &ring->desc_hw[i]; 1262 desc->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE); 1263 } 1264 1265 /* Enable DMA Rx ring interrupt */ 1266 val = ioread32(ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE); 1267 XGENE_DMA_RING_NE_INT_MODE_SET(val, ring->buf_num); 1268 iowrite32(val, ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE); 1269 } 1270 1271 static void xgene_dma_clear_ring(struct xgene_dma_ring *ring) 1272 { 1273 u32 ring_id, val; 1274 1275 if (ring->owner == XGENE_DMA_RING_OWNER_CPU) { 1276 /* Disable DMA Rx ring interrupt */ 1277 val = ioread32(ring->pdma->csr_ring + 1278 XGENE_DMA_RING_NE_INT_MODE); 1279 XGENE_DMA_RING_NE_INT_MODE_RESET(val, ring->buf_num); 1280 iowrite32(val, ring->pdma->csr_ring + 1281 XGENE_DMA_RING_NE_INT_MODE); 1282 } 1283 1284 /* Clear DMA ring state */ 1285 ring_id = XGENE_DMA_RING_ID_SETUP(ring->id); 1286 iowrite32(ring_id, ring->pdma->csr_ring + XGENE_DMA_RING_ID); 1287 1288 iowrite32(0, ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF); 1289 xgene_dma_clr_ring_state(ring); 1290 } 1291 1292 static void xgene_dma_set_ring_cmd(struct xgene_dma_ring *ring) 1293 { 1294 ring->cmd_base = ring->pdma->csr_ring_cmd + 1295 XGENE_DMA_RING_CMD_BASE_OFFSET((ring->num - 1296 XGENE_DMA_RING_NUM)); 1297 1298 ring->cmd = ring->cmd_base + XGENE_DMA_RING_CMD_OFFSET; 1299 } 1300 1301 static int xgene_dma_get_ring_size(struct xgene_dma_chan *chan, 1302 enum xgene_dma_ring_cfgsize cfgsize) 1303 { 1304 int size; 1305 1306 switch (cfgsize) { 1307 case XGENE_DMA_RING_CFG_SIZE_512B: 1308 size = 0x200; 1309 break; 1310 case XGENE_DMA_RING_CFG_SIZE_2KB: 1311 size = 0x800; 1312 break; 1313 case XGENE_DMA_RING_CFG_SIZE_16KB: 1314 size = 0x4000; 1315 break; 1316 case XGENE_DMA_RING_CFG_SIZE_64KB: 1317 size = 0x10000; 1318 break; 1319 case XGENE_DMA_RING_CFG_SIZE_512KB: 1320 size = 0x80000; 1321 break; 1322 default: 1323 chan_err(chan, "Unsupported cfg ring size %d\n", cfgsize); 1324 return -EINVAL; 1325 } 1326 1327 return size; 1328 } 1329 1330 static void xgene_dma_delete_ring_one(struct xgene_dma_ring *ring) 1331 { 1332 /* Clear DMA ring configurations */ 1333 xgene_dma_clear_ring(ring); 1334 1335 /* De-allocate DMA ring descriptor */ 1336 if (ring->desc_vaddr) { 1337 dma_free_coherent(ring->pdma->dev, ring->size, 1338 ring->desc_vaddr, ring->desc_paddr); 1339 ring->desc_vaddr = NULL; 1340 } 1341 } 1342 1343 static void xgene_dma_delete_chan_rings(struct xgene_dma_chan *chan) 1344 { 1345 xgene_dma_delete_ring_one(&chan->rx_ring); 1346 xgene_dma_delete_ring_one(&chan->tx_ring); 1347 } 1348 1349 static int xgene_dma_create_ring_one(struct xgene_dma_chan *chan, 1350 struct xgene_dma_ring *ring, 1351 enum xgene_dma_ring_cfgsize cfgsize) 1352 { 1353 int ret; 1354 1355 /* Setup DMA ring descriptor variables */ 1356 ring->pdma = chan->pdma; 1357 ring->cfgsize = cfgsize; 1358 ring->num = chan->pdma->ring_num++; 1359 ring->id = XGENE_DMA_RING_ID_GET(ring->owner, ring->buf_num); 1360 1361 ret = xgene_dma_get_ring_size(chan, cfgsize); 1362 if (ret <= 0) 1363 return ret; 1364 ring->size = ret; 1365 1366 /* Allocate memory for DMA ring descriptor */ 1367 ring->desc_vaddr = dma_zalloc_coherent(chan->dev, ring->size, 1368 &ring->desc_paddr, GFP_KERNEL); 1369 if (!ring->desc_vaddr) { 1370 chan_err(chan, "Failed to allocate ring desc\n"); 1371 return -ENOMEM; 1372 } 1373 1374 /* Configure and enable DMA ring */ 1375 xgene_dma_set_ring_cmd(ring); 1376 xgene_dma_setup_ring(ring); 1377 1378 return 0; 1379 } 1380 1381 static int xgene_dma_create_chan_rings(struct xgene_dma_chan *chan) 1382 { 1383 struct xgene_dma_ring *rx_ring = &chan->rx_ring; 1384 struct xgene_dma_ring *tx_ring = &chan->tx_ring; 1385 int ret; 1386 1387 /* Create DMA Rx ring descriptor */ 1388 rx_ring->owner = XGENE_DMA_RING_OWNER_CPU; 1389 rx_ring->buf_num = XGENE_DMA_CPU_BUFNUM + chan->id; 1390 1391 ret = xgene_dma_create_ring_one(chan, rx_ring, 1392 XGENE_DMA_RING_CFG_SIZE_64KB); 1393 if (ret) 1394 return ret; 1395 1396 chan_dbg(chan, "Rx ring id 0x%X num %d desc 0x%p\n", 1397 rx_ring->id, rx_ring->num, rx_ring->desc_vaddr); 1398 1399 /* Create DMA Tx ring descriptor */ 1400 tx_ring->owner = XGENE_DMA_RING_OWNER_DMA; 1401 tx_ring->buf_num = XGENE_DMA_BUFNUM + chan->id; 1402 1403 ret = xgene_dma_create_ring_one(chan, tx_ring, 1404 XGENE_DMA_RING_CFG_SIZE_64KB); 1405 if (ret) { 1406 xgene_dma_delete_ring_one(rx_ring); 1407 return ret; 1408 } 1409 1410 tx_ring->dst_ring_num = XGENE_DMA_RING_DST_ID(rx_ring->num); 1411 1412 chan_dbg(chan, 1413 "Tx ring id 0x%X num %d desc 0x%p\n", 1414 tx_ring->id, tx_ring->num, tx_ring->desc_vaddr); 1415 1416 /* Set the max outstanding request possible to this channel */ 1417 chan->max_outstanding = tx_ring->slots; 1418 1419 return ret; 1420 } 1421 1422 static int xgene_dma_init_rings(struct xgene_dma *pdma) 1423 { 1424 int ret, i, j; 1425 1426 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) { 1427 ret = xgene_dma_create_chan_rings(&pdma->chan[i]); 1428 if (ret) { 1429 for (j = 0; j < i; j++) 1430 xgene_dma_delete_chan_rings(&pdma->chan[j]); 1431 return ret; 1432 } 1433 } 1434 1435 return ret; 1436 } 1437 1438 static void xgene_dma_enable(struct xgene_dma *pdma) 1439 { 1440 u32 val; 1441 1442 /* Configure and enable DMA engine */ 1443 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR); 1444 XGENE_DMA_CH_SETUP(val); 1445 XGENE_DMA_ENABLE(val); 1446 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR); 1447 } 1448 1449 static void xgene_dma_disable(struct xgene_dma *pdma) 1450 { 1451 u32 val; 1452 1453 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR); 1454 XGENE_DMA_DISABLE(val); 1455 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR); 1456 } 1457 1458 static void xgene_dma_mask_interrupts(struct xgene_dma *pdma) 1459 { 1460 /* 1461 * Mask DMA ring overflow, underflow and 1462 * AXI write/read error interrupts 1463 */ 1464 iowrite32(XGENE_DMA_INT_ALL_MASK, 1465 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK); 1466 iowrite32(XGENE_DMA_INT_ALL_MASK, 1467 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK); 1468 iowrite32(XGENE_DMA_INT_ALL_MASK, 1469 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK); 1470 iowrite32(XGENE_DMA_INT_ALL_MASK, 1471 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK); 1472 iowrite32(XGENE_DMA_INT_ALL_MASK, 1473 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK); 1474 1475 /* Mask DMA error interrupts */ 1476 iowrite32(XGENE_DMA_INT_ALL_MASK, pdma->csr_dma + XGENE_DMA_INT_MASK); 1477 } 1478 1479 static void xgene_dma_unmask_interrupts(struct xgene_dma *pdma) 1480 { 1481 /* 1482 * Unmask DMA ring overflow, underflow and 1483 * AXI write/read error interrupts 1484 */ 1485 iowrite32(XGENE_DMA_INT_ALL_UNMASK, 1486 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK); 1487 iowrite32(XGENE_DMA_INT_ALL_UNMASK, 1488 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK); 1489 iowrite32(XGENE_DMA_INT_ALL_UNMASK, 1490 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK); 1491 iowrite32(XGENE_DMA_INT_ALL_UNMASK, 1492 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK); 1493 iowrite32(XGENE_DMA_INT_ALL_UNMASK, 1494 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK); 1495 1496 /* Unmask DMA error interrupts */ 1497 iowrite32(XGENE_DMA_INT_ALL_UNMASK, 1498 pdma->csr_dma + XGENE_DMA_INT_MASK); 1499 } 1500 1501 static void xgene_dma_init_hw(struct xgene_dma *pdma) 1502 { 1503 u32 val; 1504 1505 /* Associate DMA ring to corresponding ring HW */ 1506 iowrite32(XGENE_DMA_ASSOC_RING_MNGR1, 1507 pdma->csr_dma + XGENE_DMA_CFG_RING_WQ_ASSOC); 1508 1509 /* Configure RAID6 polynomial control setting */ 1510 if (is_pq_enabled(pdma)) 1511 iowrite32(XGENE_DMA_RAID6_MULTI_CTRL(0x1D), 1512 pdma->csr_dma + XGENE_DMA_RAID6_CONT); 1513 else 1514 dev_info(pdma->dev, "PQ is disabled in HW\n"); 1515 1516 xgene_dma_enable(pdma); 1517 xgene_dma_unmask_interrupts(pdma); 1518 1519 /* Get DMA id and version info */ 1520 val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR); 1521 1522 /* DMA device info */ 1523 dev_info(pdma->dev, 1524 "X-Gene DMA v%d.%02d.%02d driver registered %d channels", 1525 XGENE_DMA_REV_NO_RD(val), XGENE_DMA_BUS_ID_RD(val), 1526 XGENE_DMA_DEV_ID_RD(val), XGENE_DMA_MAX_CHANNEL); 1527 } 1528 1529 static int xgene_dma_init_ring_mngr(struct xgene_dma *pdma) 1530 { 1531 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_CLKEN) && 1532 (!ioread32(pdma->csr_ring + XGENE_DMA_RING_SRST))) 1533 return 0; 1534 1535 iowrite32(0x3, pdma->csr_ring + XGENE_DMA_RING_CLKEN); 1536 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_SRST); 1537 1538 /* Bring up memory */ 1539 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN); 1540 1541 /* Force a barrier */ 1542 ioread32(pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN); 1543 1544 /* reset may take up to 1ms */ 1545 usleep_range(1000, 1100); 1546 1547 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_BLK_MEM_RDY) 1548 != XGENE_DMA_RING_BLK_MEM_RDY_VAL) { 1549 dev_err(pdma->dev, 1550 "Failed to release ring mngr memory from shutdown\n"); 1551 return -ENODEV; 1552 } 1553 1554 /* program threshold set 1 and all hysteresis */ 1555 iowrite32(XGENE_DMA_RING_THRESLD0_SET1_VAL, 1556 pdma->csr_ring + XGENE_DMA_RING_THRESLD0_SET1); 1557 iowrite32(XGENE_DMA_RING_THRESLD1_SET1_VAL, 1558 pdma->csr_ring + XGENE_DMA_RING_THRESLD1_SET1); 1559 iowrite32(XGENE_DMA_RING_HYSTERESIS_VAL, 1560 pdma->csr_ring + XGENE_DMA_RING_HYSTERESIS); 1561 1562 /* Enable QPcore and assign error queue */ 1563 iowrite32(XGENE_DMA_RING_ENABLE, 1564 pdma->csr_ring + XGENE_DMA_RING_CONFIG); 1565 1566 return 0; 1567 } 1568 1569 static int xgene_dma_init_mem(struct xgene_dma *pdma) 1570 { 1571 int ret; 1572 1573 ret = xgene_dma_init_ring_mngr(pdma); 1574 if (ret) 1575 return ret; 1576 1577 /* Bring up memory */ 1578 iowrite32(0x0, pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN); 1579 1580 /* Force a barrier */ 1581 ioread32(pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN); 1582 1583 /* reset may take up to 1ms */ 1584 usleep_range(1000, 1100); 1585 1586 if (ioread32(pdma->csr_dma + XGENE_DMA_BLK_MEM_RDY) 1587 != XGENE_DMA_BLK_MEM_RDY_VAL) { 1588 dev_err(pdma->dev, 1589 "Failed to release DMA memory from shutdown\n"); 1590 return -ENODEV; 1591 } 1592 1593 return 0; 1594 } 1595 1596 static int xgene_dma_request_irqs(struct xgene_dma *pdma) 1597 { 1598 struct xgene_dma_chan *chan; 1599 int ret, i, j; 1600 1601 /* Register DMA error irq */ 1602 ret = devm_request_irq(pdma->dev, pdma->err_irq, xgene_dma_err_isr, 1603 0, "dma_error", pdma); 1604 if (ret) { 1605 dev_err(pdma->dev, 1606 "Failed to register error IRQ %d\n", pdma->err_irq); 1607 return ret; 1608 } 1609 1610 /* Register DMA channel rx irq */ 1611 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) { 1612 chan = &pdma->chan[i]; 1613 irq_set_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY); 1614 ret = devm_request_irq(chan->dev, chan->rx_irq, 1615 xgene_dma_chan_ring_isr, 1616 0, chan->name, chan); 1617 if (ret) { 1618 chan_err(chan, "Failed to register Rx IRQ %d\n", 1619 chan->rx_irq); 1620 devm_free_irq(pdma->dev, pdma->err_irq, pdma); 1621 1622 for (j = 0; j < i; j++) { 1623 chan = &pdma->chan[i]; 1624 irq_clear_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY); 1625 devm_free_irq(chan->dev, chan->rx_irq, chan); 1626 } 1627 1628 return ret; 1629 } 1630 } 1631 1632 return 0; 1633 } 1634 1635 static void xgene_dma_free_irqs(struct xgene_dma *pdma) 1636 { 1637 struct xgene_dma_chan *chan; 1638 int i; 1639 1640 /* Free DMA device error irq */ 1641 devm_free_irq(pdma->dev, pdma->err_irq, pdma); 1642 1643 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) { 1644 chan = &pdma->chan[i]; 1645 irq_clear_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY); 1646 devm_free_irq(chan->dev, chan->rx_irq, chan); 1647 } 1648 } 1649 1650 static void xgene_dma_set_caps(struct xgene_dma_chan *chan, 1651 struct dma_device *dma_dev) 1652 { 1653 /* Initialize DMA device capability mask */ 1654 dma_cap_zero(dma_dev->cap_mask); 1655 1656 /* Set DMA device capability */ 1657 dma_cap_set(DMA_SG, dma_dev->cap_mask); 1658 1659 /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR 1660 * and channel 1 supports XOR, PQ both. First thing here is we have 1661 * mechanism in hw to enable/disable PQ/XOR supports on channel 1, 1662 * we can make sure this by reading SoC Efuse register. 1663 * Second thing, we have hw errata that if we run channel 0 and 1664 * channel 1 simultaneously with executing XOR and PQ request, 1665 * suddenly DMA engine hangs, So here we enable XOR on channel 0 only 1666 * if XOR and PQ supports on channel 1 is disabled. 1667 */ 1668 if ((chan->id == XGENE_DMA_PQ_CHANNEL) && 1669 is_pq_enabled(chan->pdma)) { 1670 dma_cap_set(DMA_PQ, dma_dev->cap_mask); 1671 dma_cap_set(DMA_XOR, dma_dev->cap_mask); 1672 } else if ((chan->id == XGENE_DMA_XOR_CHANNEL) && 1673 !is_pq_enabled(chan->pdma)) { 1674 dma_cap_set(DMA_XOR, dma_dev->cap_mask); 1675 } 1676 1677 /* Set base and prep routines */ 1678 dma_dev->dev = chan->dev; 1679 dma_dev->device_alloc_chan_resources = xgene_dma_alloc_chan_resources; 1680 dma_dev->device_free_chan_resources = xgene_dma_free_chan_resources; 1681 dma_dev->device_issue_pending = xgene_dma_issue_pending; 1682 dma_dev->device_tx_status = xgene_dma_tx_status; 1683 dma_dev->device_prep_dma_sg = xgene_dma_prep_sg; 1684 1685 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { 1686 dma_dev->device_prep_dma_xor = xgene_dma_prep_xor; 1687 dma_dev->max_xor = XGENE_DMA_MAX_XOR_SRC; 1688 dma_dev->xor_align = DMAENGINE_ALIGN_64_BYTES; 1689 } 1690 1691 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { 1692 dma_dev->device_prep_dma_pq = xgene_dma_prep_pq; 1693 dma_dev->max_pq = XGENE_DMA_MAX_XOR_SRC; 1694 dma_dev->pq_align = DMAENGINE_ALIGN_64_BYTES; 1695 } 1696 } 1697 1698 static int xgene_dma_async_register(struct xgene_dma *pdma, int id) 1699 { 1700 struct xgene_dma_chan *chan = &pdma->chan[id]; 1701 struct dma_device *dma_dev = &pdma->dma_dev[id]; 1702 int ret; 1703 1704 chan->dma_chan.device = dma_dev; 1705 1706 spin_lock_init(&chan->lock); 1707 INIT_LIST_HEAD(&chan->ld_pending); 1708 INIT_LIST_HEAD(&chan->ld_running); 1709 INIT_LIST_HEAD(&chan->ld_completed); 1710 tasklet_init(&chan->tasklet, xgene_dma_tasklet_cb, 1711 (unsigned long)chan); 1712 1713 chan->pending = 0; 1714 chan->desc_pool = NULL; 1715 dma_cookie_init(&chan->dma_chan); 1716 1717 /* Setup dma device capabilities and prep routines */ 1718 xgene_dma_set_caps(chan, dma_dev); 1719 1720 /* Initialize DMA device list head */ 1721 INIT_LIST_HEAD(&dma_dev->channels); 1722 list_add_tail(&chan->dma_chan.device_node, &dma_dev->channels); 1723 1724 /* Register with Linux async DMA framework*/ 1725 ret = dma_async_device_register(dma_dev); 1726 if (ret) { 1727 chan_err(chan, "Failed to register async device %d", ret); 1728 tasklet_kill(&chan->tasklet); 1729 1730 return ret; 1731 } 1732 1733 /* DMA capability info */ 1734 dev_info(pdma->dev, 1735 "%s: CAPABILITY ( %s%s%s)\n", dma_chan_name(&chan->dma_chan), 1736 dma_has_cap(DMA_SG, dma_dev->cap_mask) ? "SGCPY " : "", 1737 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "XOR " : "", 1738 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "PQ " : ""); 1739 1740 return 0; 1741 } 1742 1743 static int xgene_dma_init_async(struct xgene_dma *pdma) 1744 { 1745 int ret, i, j; 1746 1747 for (i = 0; i < XGENE_DMA_MAX_CHANNEL ; i++) { 1748 ret = xgene_dma_async_register(pdma, i); 1749 if (ret) { 1750 for (j = 0; j < i; j++) { 1751 dma_async_device_unregister(&pdma->dma_dev[j]); 1752 tasklet_kill(&pdma->chan[j].tasklet); 1753 } 1754 1755 return ret; 1756 } 1757 } 1758 1759 return ret; 1760 } 1761 1762 static void xgene_dma_async_unregister(struct xgene_dma *pdma) 1763 { 1764 int i; 1765 1766 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) 1767 dma_async_device_unregister(&pdma->dma_dev[i]); 1768 } 1769 1770 static void xgene_dma_init_channels(struct xgene_dma *pdma) 1771 { 1772 struct xgene_dma_chan *chan; 1773 int i; 1774 1775 pdma->ring_num = XGENE_DMA_RING_NUM; 1776 1777 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) { 1778 chan = &pdma->chan[i]; 1779 chan->dev = pdma->dev; 1780 chan->pdma = pdma; 1781 chan->id = i; 1782 snprintf(chan->name, sizeof(chan->name), "dmachan%d", chan->id); 1783 } 1784 } 1785 1786 static int xgene_dma_get_resources(struct platform_device *pdev, 1787 struct xgene_dma *pdma) 1788 { 1789 struct resource *res; 1790 int irq, i; 1791 1792 /* Get DMA csr region */ 1793 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1794 if (!res) { 1795 dev_err(&pdev->dev, "Failed to get csr region\n"); 1796 return -ENXIO; 1797 } 1798 1799 pdma->csr_dma = devm_ioremap(&pdev->dev, res->start, 1800 resource_size(res)); 1801 if (!pdma->csr_dma) { 1802 dev_err(&pdev->dev, "Failed to ioremap csr region"); 1803 return -ENOMEM; 1804 } 1805 1806 /* Get DMA ring csr region */ 1807 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1808 if (!res) { 1809 dev_err(&pdev->dev, "Failed to get ring csr region\n"); 1810 return -ENXIO; 1811 } 1812 1813 pdma->csr_ring = devm_ioremap(&pdev->dev, res->start, 1814 resource_size(res)); 1815 if (!pdma->csr_ring) { 1816 dev_err(&pdev->dev, "Failed to ioremap ring csr region"); 1817 return -ENOMEM; 1818 } 1819 1820 /* Get DMA ring cmd csr region */ 1821 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 1822 if (!res) { 1823 dev_err(&pdev->dev, "Failed to get ring cmd csr region\n"); 1824 return -ENXIO; 1825 } 1826 1827 pdma->csr_ring_cmd = devm_ioremap(&pdev->dev, res->start, 1828 resource_size(res)); 1829 if (!pdma->csr_ring_cmd) { 1830 dev_err(&pdev->dev, "Failed to ioremap ring cmd csr region"); 1831 return -ENOMEM; 1832 } 1833 1834 pdma->csr_ring_cmd += XGENE_DMA_RING_CMD_SM_OFFSET; 1835 1836 /* Get efuse csr region */ 1837 res = platform_get_resource(pdev, IORESOURCE_MEM, 3); 1838 if (!res) { 1839 dev_err(&pdev->dev, "Failed to get efuse csr region\n"); 1840 return -ENXIO; 1841 } 1842 1843 pdma->csr_efuse = devm_ioremap(&pdev->dev, res->start, 1844 resource_size(res)); 1845 if (!pdma->csr_efuse) { 1846 dev_err(&pdev->dev, "Failed to ioremap efuse csr region"); 1847 return -ENOMEM; 1848 } 1849 1850 /* Get DMA error interrupt */ 1851 irq = platform_get_irq(pdev, 0); 1852 if (irq <= 0) { 1853 dev_err(&pdev->dev, "Failed to get Error IRQ\n"); 1854 return -ENXIO; 1855 } 1856 1857 pdma->err_irq = irq; 1858 1859 /* Get DMA Rx ring descriptor interrupts for all DMA channels */ 1860 for (i = 1; i <= XGENE_DMA_MAX_CHANNEL; i++) { 1861 irq = platform_get_irq(pdev, i); 1862 if (irq <= 0) { 1863 dev_err(&pdev->dev, "Failed to get Rx IRQ\n"); 1864 return -ENXIO; 1865 } 1866 1867 pdma->chan[i - 1].rx_irq = irq; 1868 } 1869 1870 return 0; 1871 } 1872 1873 static int xgene_dma_probe(struct platform_device *pdev) 1874 { 1875 struct xgene_dma *pdma; 1876 int ret, i; 1877 1878 pdma = devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL); 1879 if (!pdma) 1880 return -ENOMEM; 1881 1882 pdma->dev = &pdev->dev; 1883 platform_set_drvdata(pdev, pdma); 1884 1885 ret = xgene_dma_get_resources(pdev, pdma); 1886 if (ret) 1887 return ret; 1888 1889 pdma->clk = devm_clk_get(&pdev->dev, NULL); 1890 if (IS_ERR(pdma->clk) && !ACPI_COMPANION(&pdev->dev)) { 1891 dev_err(&pdev->dev, "Failed to get clk\n"); 1892 return PTR_ERR(pdma->clk); 1893 } 1894 1895 /* Enable clk before accessing registers */ 1896 if (!IS_ERR(pdma->clk)) { 1897 ret = clk_prepare_enable(pdma->clk); 1898 if (ret) { 1899 dev_err(&pdev->dev, "Failed to enable clk %d\n", ret); 1900 return ret; 1901 } 1902 } 1903 1904 /* Remove DMA RAM out of shutdown */ 1905 ret = xgene_dma_init_mem(pdma); 1906 if (ret) 1907 goto err_clk_enable; 1908 1909 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(42)); 1910 if (ret) { 1911 dev_err(&pdev->dev, "No usable DMA configuration\n"); 1912 goto err_dma_mask; 1913 } 1914 1915 /* Initialize DMA channels software state */ 1916 xgene_dma_init_channels(pdma); 1917 1918 /* Configue DMA rings */ 1919 ret = xgene_dma_init_rings(pdma); 1920 if (ret) 1921 goto err_clk_enable; 1922 1923 ret = xgene_dma_request_irqs(pdma); 1924 if (ret) 1925 goto err_request_irq; 1926 1927 /* Configure and enable DMA engine */ 1928 xgene_dma_init_hw(pdma); 1929 1930 /* Register DMA device with linux async framework */ 1931 ret = xgene_dma_init_async(pdma); 1932 if (ret) 1933 goto err_async_init; 1934 1935 return 0; 1936 1937 err_async_init: 1938 xgene_dma_free_irqs(pdma); 1939 1940 err_request_irq: 1941 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) 1942 xgene_dma_delete_chan_rings(&pdma->chan[i]); 1943 1944 err_dma_mask: 1945 err_clk_enable: 1946 if (!IS_ERR(pdma->clk)) 1947 clk_disable_unprepare(pdma->clk); 1948 1949 return ret; 1950 } 1951 1952 static int xgene_dma_remove(struct platform_device *pdev) 1953 { 1954 struct xgene_dma *pdma = platform_get_drvdata(pdev); 1955 struct xgene_dma_chan *chan; 1956 int i; 1957 1958 xgene_dma_async_unregister(pdma); 1959 1960 /* Mask interrupts and disable DMA engine */ 1961 xgene_dma_mask_interrupts(pdma); 1962 xgene_dma_disable(pdma); 1963 xgene_dma_free_irqs(pdma); 1964 1965 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) { 1966 chan = &pdma->chan[i]; 1967 tasklet_kill(&chan->tasklet); 1968 xgene_dma_delete_chan_rings(chan); 1969 } 1970 1971 if (!IS_ERR(pdma->clk)) 1972 clk_disable_unprepare(pdma->clk); 1973 1974 return 0; 1975 } 1976 1977 #ifdef CONFIG_ACPI 1978 static const struct acpi_device_id xgene_dma_acpi_match_ptr[] = { 1979 {"APMC0D43", 0}, 1980 {}, 1981 }; 1982 MODULE_DEVICE_TABLE(acpi, xgene_dma_acpi_match_ptr); 1983 #endif 1984 1985 static const struct of_device_id xgene_dma_of_match_ptr[] = { 1986 {.compatible = "apm,xgene-storm-dma",}, 1987 {}, 1988 }; 1989 MODULE_DEVICE_TABLE(of, xgene_dma_of_match_ptr); 1990 1991 static struct platform_driver xgene_dma_driver = { 1992 .probe = xgene_dma_probe, 1993 .remove = xgene_dma_remove, 1994 .driver = { 1995 .name = "X-Gene-DMA", 1996 .of_match_table = xgene_dma_of_match_ptr, 1997 .acpi_match_table = ACPI_PTR(xgene_dma_acpi_match_ptr), 1998 }, 1999 }; 2000 2001 module_platform_driver(xgene_dma_driver); 2002 2003 MODULE_DESCRIPTION("APM X-Gene SoC DMA driver"); 2004 MODULE_AUTHOR("Rameshwar Prasad Sahu <rsahu@apm.com>"); 2005 MODULE_AUTHOR("Loc Ho <lho@apm.com>"); 2006 MODULE_LICENSE("GPL"); 2007 MODULE_VERSION("1.0"); 2008