1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADMA driver for Nvidia's Tegra210 ADMA controller. 4 * 5 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_dma.h> 13 #include <linux/of_irq.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/slab.h> 17 18 #include "virt-dma.h" 19 20 #define ADMA_CH_CMD 0x00 21 #define ADMA_CH_STATUS 0x0c 22 #define ADMA_CH_STATUS_XFER_EN BIT(0) 23 #define ADMA_CH_STATUS_XFER_PAUSED BIT(1) 24 25 #define ADMA_CH_INT_STATUS 0x10 26 #define ADMA_CH_INT_STATUS_XFER_DONE BIT(0) 27 28 #define ADMA_CH_INT_CLEAR 0x1c 29 #define ADMA_CH_CTRL 0x24 30 #define ADMA_CH_CTRL_DIR(val, mask, shift) (((val) & (mask)) << (shift)) 31 #define ADMA_CH_CTRL_DIR_AHUB2MEM 2 32 #define ADMA_CH_CTRL_DIR_MEM2AHUB 4 33 #define ADMA_CH_CTRL_MODE_CONTINUOUS(shift) (2 << (shift)) 34 #define ADMA_CH_CTRL_FLOWCTRL_EN BIT(1) 35 #define ADMA_CH_CTRL_XFER_PAUSE_SHIFT 0 36 37 #define ADMA_CH_CONFIG 0x28 38 #define ADMA_CH_CONFIG_SRC_BUF(val) (((val) & 0x7) << 28) 39 #define ADMA_CH_CONFIG_TRG_BUF(val) (((val) & 0x7) << 24) 40 #define ADMA_CH_CONFIG_BURST_SIZE_SHIFT 20 41 #define ADMA_CH_CONFIG_MAX_BURST_SIZE 16 42 #define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0xf) 43 #define ADMA_CH_CONFIG_MAX_BUFS 8 44 #define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs) ((reqs) << 4) 45 46 #define ADMA_GLOBAL_CH_CONFIG 0x400 47 #define ADMA_GLOBAL_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0x7) 48 #define ADMA_GLOBAL_CH_CONFIG_OUTSTANDING_REQS(reqs) ((reqs) << 8) 49 50 #define TEGRA186_ADMA_GLOBAL_PAGE_CHGRP 0x30 51 #define TEGRA186_ADMA_GLOBAL_PAGE_RX_REQ 0x70 52 #define TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ 0x84 53 #define TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_0 0x44 54 #define TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_1 0x48 55 #define TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_0 0x100 56 #define TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_1 0x104 57 #define TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_0 0x180 58 #define TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_1 0x184 59 #define TEGRA264_ADMA_GLOBAL_PAGE_OFFSET 0x8 60 61 #define ADMA_CH_FIFO_CTRL 0x2c 62 #define ADMA_CH_TX_FIFO_SIZE_SHIFT 8 63 #define ADMA_CH_RX_FIFO_SIZE_SHIFT 0 64 #define ADMA_GLOBAL_CH_FIFO_CTRL 0x300 65 66 #define ADMA_CH_LOWER_SRC_ADDR 0x34 67 #define ADMA_CH_LOWER_TRG_ADDR 0x3c 68 #define ADMA_CH_TC 0x44 69 #define ADMA_CH_TC_COUNT_MASK 0x3ffffffc 70 71 #define ADMA_CH_XFER_STATUS 0x54 72 #define ADMA_CH_XFER_STATUS_COUNT_MASK 0xffff 73 74 #define ADMA_GLOBAL_CMD 0x00 75 #define ADMA_GLOBAL_SOFT_RESET 0x04 76 77 #define TEGRA_ADMA_BURST_COMPLETE_TIME 20 78 79 #define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift) 80 81 struct tegra_adma; 82 83 /* 84 * struct tegra_adma_chip_data - Tegra chip specific data 85 * @adma_get_burst_config: Function callback used to set DMA burst size. 86 * @global_reg_offset: Register offset of DMA global register. 87 * @global_int_clear: Register offset of DMA global interrupt clear. 88 * @global_ch_fifo_base: Global channel fifo ctrl base offset 89 * @global_ch_config_base: Global channel config base offset 90 * @ch_req_tx_shift: Register offset for AHUB transmit channel select. 91 * @ch_req_rx_shift: Register offset for AHUB receive channel select. 92 * @ch_dir_shift: Channel direction bit position. 93 * @ch_mode_shift: Channel mode bit position. 94 * @ch_base_offset: Register offset of DMA channel registers. 95 * @ch_tc_offset_diff: From TC register onwards offset differs for Tegra264 96 * @ch_fifo_ctrl: Default value for channel FIFO CTRL register. 97 * @ch_config: Outstanding and WRR config values 98 * @ch_req_mask: Mask for Tx or Rx channel select. 99 * @ch_dir_mask: Mask for channel direction. 100 * @ch_req_max: Maximum number of Tx or Rx channels available. 101 * @ch_reg_size: Size of DMA channel register space. 102 * @nr_channels: Number of DMA channels available. 103 * @ch_fifo_size_mask: Mask for FIFO size field. 104 * @sreq_index_offset: Slave channel index offset. 105 * @max_page: Maximum ADMA Channel Page. 106 * @set_global_pg_config: Global page programming. 107 */ 108 struct tegra_adma_chip_data { 109 unsigned int (*adma_get_burst_config)(unsigned int burst_size); 110 unsigned int global_reg_offset; 111 unsigned int global_int_clear; 112 unsigned int global_ch_fifo_base; 113 unsigned int global_ch_config_base; 114 unsigned int ch_req_tx_shift; 115 unsigned int ch_req_rx_shift; 116 unsigned int ch_dir_shift; 117 unsigned int ch_mode_shift; 118 unsigned int ch_base_offset; 119 unsigned int ch_tc_offset_diff; 120 unsigned int ch_fifo_ctrl; 121 unsigned int ch_config; 122 unsigned int ch_req_mask; 123 unsigned int ch_dir_mask; 124 unsigned int ch_req_max; 125 unsigned int ch_reg_size; 126 unsigned int nr_channels; 127 unsigned int ch_fifo_size_mask; 128 unsigned int sreq_index_offset; 129 unsigned int max_page; 130 void (*set_global_pg_config)(struct tegra_adma *tdma); 131 }; 132 133 /* 134 * struct tegra_adma_chan_regs - Tegra ADMA channel registers 135 */ 136 struct tegra_adma_chan_regs { 137 unsigned int ctrl; 138 unsigned int config; 139 unsigned int global_config; 140 unsigned int src_addr; 141 unsigned int trg_addr; 142 unsigned int fifo_ctrl; 143 unsigned int cmd; 144 unsigned int tc; 145 }; 146 147 /* 148 * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests. 149 */ 150 struct tegra_adma_desc { 151 struct virt_dma_desc vd; 152 struct tegra_adma_chan_regs ch_regs; 153 size_t buf_len; 154 size_t period_len; 155 size_t num_periods; 156 }; 157 158 /* 159 * struct tegra_adma_chan - Tegra ADMA channel information 160 */ 161 struct tegra_adma_chan { 162 struct virt_dma_chan vc; 163 struct tegra_adma_desc *desc; 164 struct tegra_adma *tdma; 165 int irq; 166 void __iomem *chan_addr; 167 168 /* Slave channel configuration info */ 169 struct dma_slave_config sconfig; 170 enum dma_transfer_direction sreq_dir; 171 unsigned int sreq_index; 172 bool sreq_reserved; 173 struct tegra_adma_chan_regs ch_regs; 174 175 /* Transfer count and position info */ 176 unsigned int tx_buf_count; 177 unsigned int tx_buf_pos; 178 179 unsigned int global_ch_fifo_offset; 180 unsigned int global_ch_config_offset; 181 }; 182 183 /* 184 * struct tegra_adma - Tegra ADMA controller information 185 */ 186 struct tegra_adma { 187 struct dma_device dma_dev; 188 struct device *dev; 189 void __iomem *base_addr; 190 void __iomem *ch_base_addr; 191 struct clk *ahub_clk; 192 unsigned int nr_channels; 193 unsigned long *dma_chan_mask; 194 unsigned long rx_requests_reserved; 195 unsigned long tx_requests_reserved; 196 197 /* Used to store global command register state when suspending */ 198 unsigned int global_cmd; 199 unsigned int ch_page_no; 200 201 const struct tegra_adma_chip_data *cdata; 202 203 /* Last member of the structure */ 204 struct tegra_adma_chan channels[] __counted_by(nr_channels); 205 }; 206 207 static inline void tdma_write(struct tegra_adma *tdma, u32 reg, u32 val) 208 { 209 writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg); 210 } 211 212 static inline u32 tdma_read(struct tegra_adma *tdma, u32 reg) 213 { 214 return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg); 215 } 216 217 static inline void tdma_ch_global_write(struct tegra_adma *tdma, u32 reg, u32 val) 218 { 219 writel(val, tdma->ch_base_addr + tdma->cdata->global_reg_offset + reg); 220 } 221 222 static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val) 223 { 224 writel(val, tdc->chan_addr + reg); 225 } 226 227 static inline u32 tdma_ch_read(struct tegra_adma_chan *tdc, u32 reg) 228 { 229 return readl(tdc->chan_addr + reg); 230 } 231 232 static inline struct tegra_adma_chan *to_tegra_adma_chan(struct dma_chan *dc) 233 { 234 return container_of(dc, struct tegra_adma_chan, vc.chan); 235 } 236 237 static inline struct tegra_adma_desc *to_tegra_adma_desc( 238 struct dma_async_tx_descriptor *td) 239 { 240 return container_of(td, struct tegra_adma_desc, vd.tx); 241 } 242 243 static inline struct device *tdc2dev(struct tegra_adma_chan *tdc) 244 { 245 return tdc->tdma->dev; 246 } 247 248 static void tegra_adma_desc_free(struct virt_dma_desc *vd) 249 { 250 kfree(container_of(vd, struct tegra_adma_desc, vd)); 251 } 252 253 static int tegra_adma_slave_config(struct dma_chan *dc, 254 struct dma_slave_config *sconfig) 255 { 256 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 257 258 memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig)); 259 260 return 0; 261 } 262 263 static void tegra186_adma_global_page_config(struct tegra_adma *tdma) 264 { 265 /* 266 * Clear the default page1 channel group configs and program 267 * the global registers based on the actual page usage 268 */ 269 tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_CHGRP, 0); 270 tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_RX_REQ, 0); 271 tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ, 0); 272 tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_CHGRP + (tdma->ch_page_no * 0x4), 0xff); 273 tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_RX_REQ + (tdma->ch_page_no * 0x4), 0x1ffffff); 274 tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ + (tdma->ch_page_no * 0x4), 0xffffff); 275 } 276 277 static void tegra264_adma_global_page_config(struct tegra_adma *tdma) 278 { 279 u32 global_page_offset = tdma->ch_page_no * TEGRA264_ADMA_GLOBAL_PAGE_OFFSET; 280 281 /* If the default page (page1) is not used, then clear page1 registers */ 282 if (tdma->ch_page_no) { 283 tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_0, 0); 284 tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_1, 0); 285 tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_0, 0); 286 tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_1, 0); 287 tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_0, 0); 288 tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_1, 0); 289 } 290 291 /* Program global registers for selected page */ 292 tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_0 + global_page_offset, 0xffffffff); 293 tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_1 + global_page_offset, 0xffffffff); 294 tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_0 + global_page_offset, 0xffffffff); 295 tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_1 + global_page_offset, 0x1); 296 tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_0 + global_page_offset, 0xffffffff); 297 tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_1 + global_page_offset, 0x1); 298 } 299 300 static int tegra_adma_init(struct tegra_adma *tdma) 301 { 302 u32 status; 303 int ret; 304 305 /* Clear any channels group global interrupts */ 306 tdma_ch_global_write(tdma, tdma->cdata->global_int_clear, 0x1); 307 308 if (!tdma->base_addr) 309 return 0; 310 311 /* Assert soft reset */ 312 tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1); 313 314 /* Wait for reset to clear */ 315 ret = readx_poll_timeout(readl, 316 tdma->base_addr + 317 tdma->cdata->global_reg_offset + 318 ADMA_GLOBAL_SOFT_RESET, 319 status, status == 0, 20, 10000); 320 if (ret) 321 return ret; 322 323 if (tdma->cdata->set_global_pg_config) 324 tdma->cdata->set_global_pg_config(tdma); 325 326 /* Enable global ADMA registers */ 327 tdma_write(tdma, ADMA_GLOBAL_CMD, 1); 328 329 return 0; 330 } 331 332 static int tegra_adma_request_alloc(struct tegra_adma_chan *tdc, 333 enum dma_transfer_direction direction) 334 { 335 struct tegra_adma *tdma = tdc->tdma; 336 unsigned int sreq_index = tdc->sreq_index; 337 338 if (tdc->sreq_reserved) 339 return tdc->sreq_dir == direction ? 0 : -EINVAL; 340 341 if (sreq_index > tdma->cdata->ch_req_max) { 342 dev_err(tdma->dev, "invalid DMA request\n"); 343 return -EINVAL; 344 } 345 346 switch (direction) { 347 case DMA_MEM_TO_DEV: 348 if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) { 349 dev_err(tdma->dev, "DMA request reserved\n"); 350 return -EINVAL; 351 } 352 break; 353 354 case DMA_DEV_TO_MEM: 355 if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) { 356 dev_err(tdma->dev, "DMA request reserved\n"); 357 return -EINVAL; 358 } 359 break; 360 361 default: 362 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", 363 dma_chan_name(&tdc->vc.chan)); 364 return -EINVAL; 365 } 366 367 tdc->sreq_dir = direction; 368 tdc->sreq_reserved = true; 369 370 return 0; 371 } 372 373 static void tegra_adma_request_free(struct tegra_adma_chan *tdc) 374 { 375 struct tegra_adma *tdma = tdc->tdma; 376 377 if (!tdc->sreq_reserved) 378 return; 379 380 switch (tdc->sreq_dir) { 381 case DMA_MEM_TO_DEV: 382 clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved); 383 break; 384 385 case DMA_DEV_TO_MEM: 386 clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved); 387 break; 388 389 default: 390 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", 391 dma_chan_name(&tdc->vc.chan)); 392 return; 393 } 394 395 tdc->sreq_reserved = false; 396 } 397 398 static u32 tegra_adma_irq_status(struct tegra_adma_chan *tdc) 399 { 400 u32 status = tdma_ch_read(tdc, ADMA_CH_INT_STATUS); 401 402 return status & ADMA_CH_INT_STATUS_XFER_DONE; 403 } 404 405 static u32 tegra_adma_irq_clear(struct tegra_adma_chan *tdc) 406 { 407 u32 status = tegra_adma_irq_status(tdc); 408 409 if (status) 410 tdma_ch_write(tdc, ADMA_CH_INT_CLEAR, status); 411 412 return status; 413 } 414 415 static void tegra_adma_stop(struct tegra_adma_chan *tdc) 416 { 417 unsigned int status; 418 419 /* Disable ADMA */ 420 tdma_ch_write(tdc, ADMA_CH_CMD, 0); 421 422 /* Clear interrupt status */ 423 tegra_adma_irq_clear(tdc); 424 425 if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS, 426 status, !(status & ADMA_CH_STATUS_XFER_EN), 427 20, 10000)) { 428 dev_err(tdc2dev(tdc), "unable to stop DMA channel\n"); 429 return; 430 } 431 432 kfree(tdc->desc); 433 tdc->desc = NULL; 434 } 435 436 static void tegra_adma_start(struct tegra_adma_chan *tdc) 437 { 438 struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc); 439 struct tegra_adma_chan_regs *ch_regs; 440 struct tegra_adma_desc *desc; 441 442 if (!vd) 443 return; 444 445 list_del(&vd->node); 446 447 desc = to_tegra_adma_desc(&vd->tx); 448 449 if (!desc) { 450 dev_warn(tdc2dev(tdc), "unable to start DMA, no descriptor\n"); 451 return; 452 } 453 454 ch_regs = &desc->ch_regs; 455 456 tdc->tx_buf_pos = 0; 457 tdc->tx_buf_count = 0; 458 tdma_ch_write(tdc, ADMA_CH_TC - tdc->tdma->cdata->ch_tc_offset_diff, ch_regs->tc); 459 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); 460 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR - tdc->tdma->cdata->ch_tc_offset_diff, 461 ch_regs->src_addr); 462 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR - tdc->tdma->cdata->ch_tc_offset_diff, 463 ch_regs->trg_addr); 464 465 if (!tdc->tdma->cdata->global_ch_fifo_base) 466 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl); 467 else if (tdc->global_ch_fifo_offset) 468 tdma_write(tdc->tdma, tdc->global_ch_fifo_offset, ch_regs->fifo_ctrl); 469 470 if (tdc->global_ch_config_offset) 471 tdma_write(tdc->tdma, tdc->global_ch_config_offset, ch_regs->global_config); 472 473 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config); 474 475 /* Start ADMA */ 476 tdma_ch_write(tdc, ADMA_CH_CMD, 1); 477 478 tdc->desc = desc; 479 } 480 481 static unsigned int tegra_adma_get_residue(struct tegra_adma_chan *tdc) 482 { 483 struct tegra_adma_desc *desc = tdc->desc; 484 unsigned int max = ADMA_CH_XFER_STATUS_COUNT_MASK + 1; 485 unsigned int pos = tdma_ch_read(tdc, ADMA_CH_XFER_STATUS - 486 tdc->tdma->cdata->ch_tc_offset_diff); 487 unsigned int periods_remaining; 488 489 /* 490 * Handle wrap around of buffer count register 491 */ 492 if (pos < tdc->tx_buf_pos) 493 tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos); 494 else 495 tdc->tx_buf_count += pos - tdc->tx_buf_pos; 496 497 periods_remaining = tdc->tx_buf_count % desc->num_periods; 498 tdc->tx_buf_pos = pos; 499 500 return desc->buf_len - (periods_remaining * desc->period_len); 501 } 502 503 static irqreturn_t tegra_adma_isr(int irq, void *dev_id) 504 { 505 struct tegra_adma_chan *tdc = dev_id; 506 unsigned long status; 507 508 spin_lock(&tdc->vc.lock); 509 510 status = tegra_adma_irq_clear(tdc); 511 if (status == 0 || !tdc->desc) { 512 spin_unlock(&tdc->vc.lock); 513 return IRQ_NONE; 514 } 515 516 vchan_cyclic_callback(&tdc->desc->vd); 517 518 spin_unlock(&tdc->vc.lock); 519 520 return IRQ_HANDLED; 521 } 522 523 static void tegra_adma_issue_pending(struct dma_chan *dc) 524 { 525 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 526 unsigned long flags; 527 528 spin_lock_irqsave(&tdc->vc.lock, flags); 529 530 if (vchan_issue_pending(&tdc->vc)) { 531 if (!tdc->desc) 532 tegra_adma_start(tdc); 533 } 534 535 spin_unlock_irqrestore(&tdc->vc.lock, flags); 536 } 537 538 static bool tegra_adma_is_paused(struct tegra_adma_chan *tdc) 539 { 540 u32 csts; 541 542 csts = tdma_ch_read(tdc, ADMA_CH_STATUS); 543 csts &= ADMA_CH_STATUS_XFER_PAUSED; 544 545 return csts ? true : false; 546 } 547 548 static int tegra_adma_pause(struct dma_chan *dc) 549 { 550 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 551 struct tegra_adma_desc *desc = tdc->desc; 552 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; 553 int dcnt = 10; 554 555 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); 556 ch_regs->ctrl |= (1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT); 557 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); 558 559 while (dcnt-- && !tegra_adma_is_paused(tdc)) 560 udelay(TEGRA_ADMA_BURST_COMPLETE_TIME); 561 562 if (dcnt < 0) { 563 dev_err(tdc2dev(tdc), "unable to pause DMA channel\n"); 564 return -EBUSY; 565 } 566 567 return 0; 568 } 569 570 static int tegra_adma_resume(struct dma_chan *dc) 571 { 572 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 573 struct tegra_adma_desc *desc = tdc->desc; 574 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; 575 576 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); 577 ch_regs->ctrl &= ~(1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT); 578 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); 579 580 return 0; 581 } 582 583 static int tegra_adma_terminate_all(struct dma_chan *dc) 584 { 585 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 586 unsigned long flags; 587 LIST_HEAD(head); 588 589 spin_lock_irqsave(&tdc->vc.lock, flags); 590 591 if (tdc->desc) 592 tegra_adma_stop(tdc); 593 594 tegra_adma_request_free(tdc); 595 vchan_get_all_descriptors(&tdc->vc, &head); 596 spin_unlock_irqrestore(&tdc->vc.lock, flags); 597 vchan_dma_desc_free_list(&tdc->vc, &head); 598 599 return 0; 600 } 601 602 static enum dma_status tegra_adma_tx_status(struct dma_chan *dc, 603 dma_cookie_t cookie, 604 struct dma_tx_state *txstate) 605 { 606 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 607 struct tegra_adma_desc *desc; 608 struct virt_dma_desc *vd; 609 enum dma_status ret; 610 unsigned long flags; 611 unsigned int residual; 612 613 ret = dma_cookie_status(dc, cookie, txstate); 614 if (ret == DMA_COMPLETE || !txstate) 615 return ret; 616 617 spin_lock_irqsave(&tdc->vc.lock, flags); 618 619 vd = vchan_find_desc(&tdc->vc, cookie); 620 if (vd) { 621 desc = to_tegra_adma_desc(&vd->tx); 622 residual = desc->ch_regs.tc; 623 } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) { 624 residual = tegra_adma_get_residue(tdc); 625 } else { 626 residual = 0; 627 } 628 629 spin_unlock_irqrestore(&tdc->vc.lock, flags); 630 631 dma_set_residue(txstate, residual); 632 633 return ret; 634 } 635 636 static unsigned int tegra210_adma_get_burst_config(unsigned int burst_size) 637 { 638 if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE) 639 burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE; 640 641 return fls(burst_size) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT; 642 } 643 644 static unsigned int tegra186_adma_get_burst_config(unsigned int burst_size) 645 { 646 if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE) 647 burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE; 648 649 return (burst_size - 1) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT; 650 } 651 652 static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc, 653 struct tegra_adma_desc *desc, 654 dma_addr_t buf_addr, 655 enum dma_transfer_direction direction) 656 { 657 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; 658 const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata; 659 unsigned int burst_size, adma_dir, fifo_size_shift; 660 661 if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS) 662 return -EINVAL; 663 664 switch (direction) { 665 case DMA_MEM_TO_DEV: 666 fifo_size_shift = ADMA_CH_TX_FIFO_SIZE_SHIFT; 667 adma_dir = ADMA_CH_CTRL_DIR_MEM2AHUB; 668 burst_size = tdc->sconfig.dst_maxburst; 669 ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1); 670 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index, 671 cdata->ch_req_mask, 672 cdata->ch_req_tx_shift); 673 ch_regs->src_addr = buf_addr; 674 break; 675 676 case DMA_DEV_TO_MEM: 677 fifo_size_shift = ADMA_CH_RX_FIFO_SIZE_SHIFT; 678 adma_dir = ADMA_CH_CTRL_DIR_AHUB2MEM; 679 burst_size = tdc->sconfig.src_maxburst; 680 ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1); 681 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index, 682 cdata->ch_req_mask, 683 cdata->ch_req_rx_shift); 684 ch_regs->trg_addr = buf_addr; 685 break; 686 687 default: 688 dev_err(tdc2dev(tdc), "DMA direction is not supported\n"); 689 return -EINVAL; 690 } 691 692 ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir, cdata->ch_dir_mask, 693 cdata->ch_dir_shift) | 694 ADMA_CH_CTRL_MODE_CONTINUOUS(cdata->ch_mode_shift) | 695 ADMA_CH_CTRL_FLOWCTRL_EN; 696 ch_regs->config |= cdata->adma_get_burst_config(burst_size); 697 698 if (cdata->global_ch_config_base) 699 ch_regs->global_config |= cdata->ch_config; 700 else 701 ch_regs->config |= cdata->ch_config; 702 703 /* 704 * 'sreq_index' represents the current ADMAIF channel number and as per 705 * HW recommendation its FIFO size should match with the corresponding 706 * ADMA channel. 707 * 708 * ADMA FIFO size is set as per below (based on default ADMAIF channel 709 * FIFO sizes): 710 * fifo_size = 0x2 (sreq_index > sreq_index_offset) 711 * fifo_size = 0x3 (sreq_index <= sreq_index_offset) 712 * 713 */ 714 if (tdc->sreq_index > cdata->sreq_index_offset) 715 ch_regs->fifo_ctrl = 716 ADMA_CH_REG_FIELD_VAL(2, cdata->ch_fifo_size_mask, 717 fifo_size_shift); 718 else 719 ch_regs->fifo_ctrl = 720 ADMA_CH_REG_FIELD_VAL(3, cdata->ch_fifo_size_mask, 721 fifo_size_shift); 722 723 ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK; 724 725 return tegra_adma_request_alloc(tdc, direction); 726 } 727 728 static struct dma_async_tx_descriptor *tegra_adma_prep_dma_cyclic( 729 struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len, 730 size_t period_len, enum dma_transfer_direction direction, 731 unsigned long flags) 732 { 733 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 734 struct tegra_adma_desc *desc = NULL; 735 736 if (!buf_len || !period_len || period_len > ADMA_CH_TC_COUNT_MASK) { 737 dev_err(tdc2dev(tdc), "invalid buffer/period len\n"); 738 return NULL; 739 } 740 741 if (buf_len % period_len) { 742 dev_err(tdc2dev(tdc), "buf_len not a multiple of period_len\n"); 743 return NULL; 744 } 745 746 if (!IS_ALIGNED(buf_addr, 4)) { 747 dev_err(tdc2dev(tdc), "invalid buffer alignment\n"); 748 return NULL; 749 } 750 751 desc = kzalloc(sizeof(*desc), GFP_NOWAIT); 752 if (!desc) 753 return NULL; 754 755 desc->buf_len = buf_len; 756 desc->period_len = period_len; 757 desc->num_periods = buf_len / period_len; 758 759 if (tegra_adma_set_xfer_params(tdc, desc, buf_addr, direction)) { 760 kfree(desc); 761 return NULL; 762 } 763 764 return vchan_tx_prep(&tdc->vc, &desc->vd, flags); 765 } 766 767 static int tegra_adma_alloc_chan_resources(struct dma_chan *dc) 768 { 769 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 770 int ret; 771 772 ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc); 773 if (ret) { 774 dev_err(tdc2dev(tdc), "failed to get interrupt for %s\n", 775 dma_chan_name(dc)); 776 return ret; 777 } 778 779 ret = pm_runtime_resume_and_get(tdc2dev(tdc)); 780 if (ret < 0) { 781 free_irq(tdc->irq, tdc); 782 return ret; 783 } 784 785 dma_cookie_init(&tdc->vc.chan); 786 787 return 0; 788 } 789 790 static void tegra_adma_free_chan_resources(struct dma_chan *dc) 791 { 792 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 793 794 tegra_adma_terminate_all(dc); 795 vchan_free_chan_resources(&tdc->vc); 796 tasklet_kill(&tdc->vc.task); 797 free_irq(tdc->irq, tdc); 798 pm_runtime_put(tdc2dev(tdc)); 799 800 tdc->sreq_index = 0; 801 tdc->sreq_dir = DMA_TRANS_NONE; 802 } 803 804 static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec, 805 struct of_dma *ofdma) 806 { 807 struct tegra_adma *tdma = ofdma->of_dma_data; 808 struct tegra_adma_chan *tdc; 809 struct dma_chan *chan; 810 unsigned int sreq_index; 811 812 if (dma_spec->args_count != 1) 813 return NULL; 814 815 sreq_index = dma_spec->args[0]; 816 817 if (sreq_index == 0) { 818 dev_err(tdma->dev, "DMA request must not be 0\n"); 819 return NULL; 820 } 821 822 chan = dma_get_any_slave_channel(&tdma->dma_dev); 823 if (!chan) 824 return NULL; 825 826 tdc = to_tegra_adma_chan(chan); 827 tdc->sreq_index = sreq_index; 828 829 return chan; 830 } 831 832 static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev) 833 { 834 struct tegra_adma *tdma = dev_get_drvdata(dev); 835 struct tegra_adma_chan_regs *ch_reg; 836 struct tegra_adma_chan *tdc; 837 int i; 838 839 if (tdma->base_addr) 840 tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); 841 842 if (!tdma->global_cmd) 843 goto clk_disable; 844 845 for (i = 0; i < tdma->nr_channels; i++) { 846 tdc = &tdma->channels[i]; 847 /* skip for reserved channels */ 848 if (!tdc->tdma) 849 continue; 850 851 ch_reg = &tdc->ch_regs; 852 ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD); 853 /* skip if channel is not active */ 854 if (!ch_reg->cmd) 855 continue; 856 ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC - tdma->cdata->ch_tc_offset_diff); 857 ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR - 858 tdma->cdata->ch_tc_offset_diff); 859 ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR - 860 tdma->cdata->ch_tc_offset_diff); 861 ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); 862 863 if (tdc->global_ch_config_offset) 864 ch_reg->global_config = tdma_read(tdc->tdma, tdc->global_ch_config_offset); 865 866 if (!tdc->tdma->cdata->global_ch_fifo_base) 867 ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL); 868 else if (tdc->global_ch_fifo_offset) 869 ch_reg->fifo_ctrl = tdma_read(tdc->tdma, tdc->global_ch_fifo_offset); 870 871 ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG); 872 873 } 874 875 clk_disable: 876 clk_disable_unprepare(tdma->ahub_clk); 877 878 return 0; 879 } 880 881 static int __maybe_unused tegra_adma_runtime_resume(struct device *dev) 882 { 883 struct tegra_adma *tdma = dev_get_drvdata(dev); 884 struct tegra_adma_chan_regs *ch_reg; 885 struct tegra_adma_chan *tdc; 886 int ret, i; 887 888 ret = clk_prepare_enable(tdma->ahub_clk); 889 if (ret) { 890 dev_err(dev, "ahub clk_enable failed: %d\n", ret); 891 return ret; 892 } 893 if (tdma->base_addr) { 894 tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); 895 if (tdma->cdata->set_global_pg_config) 896 tdma->cdata->set_global_pg_config(tdma); 897 } 898 899 if (!tdma->global_cmd) 900 return 0; 901 902 for (i = 0; i < tdma->nr_channels; i++) { 903 tdc = &tdma->channels[i]; 904 /* skip for reserved channels */ 905 if (!tdc->tdma) 906 continue; 907 ch_reg = &tdc->ch_regs; 908 /* skip if channel was not active earlier */ 909 if (!ch_reg->cmd) 910 continue; 911 tdma_ch_write(tdc, ADMA_CH_TC - tdma->cdata->ch_tc_offset_diff, ch_reg->tc); 912 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR - tdma->cdata->ch_tc_offset_diff, 913 ch_reg->src_addr); 914 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR - tdma->cdata->ch_tc_offset_diff, 915 ch_reg->trg_addr); 916 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl); 917 918 if (!tdc->tdma->cdata->global_ch_fifo_base) 919 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl); 920 else if (tdc->global_ch_fifo_offset) 921 tdma_write(tdc->tdma, tdc->global_ch_fifo_offset, ch_reg->fifo_ctrl); 922 923 if (tdc->global_ch_config_offset) 924 tdma_write(tdc->tdma, tdc->global_ch_config_offset, ch_reg->global_config); 925 926 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config); 927 928 tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd); 929 } 930 931 return 0; 932 } 933 934 static const struct tegra_adma_chip_data tegra210_chip_data = { 935 .adma_get_burst_config = tegra210_adma_get_burst_config, 936 .global_reg_offset = 0xc00, 937 .global_int_clear = 0x20, 938 .global_ch_fifo_base = 0, 939 .global_ch_config_base = 0, 940 .ch_req_tx_shift = 28, 941 .ch_req_rx_shift = 24, 942 .ch_dir_shift = 12, 943 .ch_mode_shift = 8, 944 .ch_base_offset = 0, 945 .ch_tc_offset_diff = 0, 946 .ch_config = ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1), 947 .ch_req_mask = 0xf, 948 .ch_dir_mask = 0xf, 949 .ch_req_max = 10, 950 .ch_reg_size = 0x80, 951 .nr_channels = 22, 952 .ch_fifo_size_mask = 0xf, 953 .sreq_index_offset = 2, 954 .max_page = 0, 955 .set_global_pg_config = NULL, 956 }; 957 958 static const struct tegra_adma_chip_data tegra186_chip_data = { 959 .adma_get_burst_config = tegra186_adma_get_burst_config, 960 .global_reg_offset = 0, 961 .global_int_clear = 0x402c, 962 .global_ch_fifo_base = 0, 963 .global_ch_config_base = 0, 964 .ch_req_tx_shift = 27, 965 .ch_req_rx_shift = 22, 966 .ch_dir_shift = 12, 967 .ch_mode_shift = 8, 968 .ch_base_offset = 0x10000, 969 .ch_tc_offset_diff = 0, 970 .ch_config = ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1) | 971 TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8), 972 .ch_req_mask = 0x1f, 973 .ch_dir_mask = 0xf, 974 .ch_req_max = 20, 975 .ch_reg_size = 0x100, 976 .nr_channels = 32, 977 .ch_fifo_size_mask = 0x1f, 978 .sreq_index_offset = 4, 979 .max_page = 4, 980 .set_global_pg_config = tegra186_adma_global_page_config, 981 }; 982 983 static const struct tegra_adma_chip_data tegra264_chip_data = { 984 .adma_get_burst_config = tegra186_adma_get_burst_config, 985 .global_reg_offset = 0, 986 .global_int_clear = 0x800c, 987 .global_ch_fifo_base = ADMA_GLOBAL_CH_FIFO_CTRL, 988 .global_ch_config_base = ADMA_GLOBAL_CH_CONFIG, 989 .ch_req_tx_shift = 26, 990 .ch_req_rx_shift = 20, 991 .ch_dir_shift = 10, 992 .ch_mode_shift = 7, 993 .ch_base_offset = 0x10000, 994 .ch_tc_offset_diff = 4, 995 .ch_config = ADMA_GLOBAL_CH_CONFIG_WEIGHT_FOR_WRR(1) | 996 ADMA_GLOBAL_CH_CONFIG_OUTSTANDING_REQS(8), 997 .ch_req_mask = 0x3f, 998 .ch_dir_mask = 7, 999 .ch_req_max = 32, 1000 .ch_reg_size = 0x100, 1001 .nr_channels = 64, 1002 .ch_fifo_size_mask = 0x7f, 1003 .sreq_index_offset = 0, 1004 .max_page = 10, 1005 .set_global_pg_config = tegra264_adma_global_page_config, 1006 }; 1007 1008 static const struct of_device_id tegra_adma_of_match[] = { 1009 { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data }, 1010 { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data }, 1011 { .compatible = "nvidia,tegra264-adma", .data = &tegra264_chip_data }, 1012 { }, 1013 }; 1014 MODULE_DEVICE_TABLE(of, tegra_adma_of_match); 1015 1016 static int tegra_adma_probe(struct platform_device *pdev) 1017 { 1018 const struct tegra_adma_chip_data *cdata; 1019 struct tegra_adma *tdma; 1020 struct resource *res_page, *res_base; 1021 int ret, i; 1022 1023 cdata = of_device_get_match_data(&pdev->dev); 1024 if (!cdata) { 1025 dev_err(&pdev->dev, "device match data not found\n"); 1026 return -ENODEV; 1027 } 1028 1029 tdma = devm_kzalloc(&pdev->dev, 1030 struct_size(tdma, channels, cdata->nr_channels), 1031 GFP_KERNEL); 1032 if (!tdma) 1033 return -ENOMEM; 1034 1035 tdma->dev = &pdev->dev; 1036 tdma->cdata = cdata; 1037 tdma->nr_channels = cdata->nr_channels; 1038 platform_set_drvdata(pdev, tdma); 1039 1040 res_page = platform_get_resource_byname(pdev, IORESOURCE_MEM, "page"); 1041 if (res_page) { 1042 tdma->ch_base_addr = devm_ioremap_resource(&pdev->dev, res_page); 1043 if (IS_ERR(tdma->ch_base_addr)) 1044 return PTR_ERR(tdma->ch_base_addr); 1045 1046 res_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "global"); 1047 if (res_base) { 1048 resource_size_t page_offset, page_no; 1049 unsigned int ch_base_offset; 1050 1051 if (res_page->start < res_base->start) 1052 return -EINVAL; 1053 page_offset = res_page->start - res_base->start; 1054 ch_base_offset = cdata->ch_base_offset; 1055 if (!ch_base_offset) 1056 return -EINVAL; 1057 1058 page_no = div_u64(page_offset, ch_base_offset); 1059 if (!page_no || page_no > INT_MAX) 1060 return -EINVAL; 1061 1062 tdma->ch_page_no = page_no - 1; 1063 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res_base); 1064 if (IS_ERR(tdma->base_addr)) 1065 return PTR_ERR(tdma->base_addr); 1066 } 1067 } else { 1068 /* If no 'page' property found, then reg DT binding would be legacy */ 1069 res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1070 if (res_base) { 1071 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res_base); 1072 if (IS_ERR(tdma->base_addr)) 1073 return PTR_ERR(tdma->base_addr); 1074 } else { 1075 return -ENODEV; 1076 } 1077 1078 tdma->ch_base_addr = tdma->base_addr + cdata->ch_base_offset; 1079 } 1080 1081 tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio"); 1082 if (IS_ERR(tdma->ahub_clk)) { 1083 dev_err(&pdev->dev, "Error: Missing ahub controller clock\n"); 1084 return PTR_ERR(tdma->ahub_clk); 1085 } 1086 1087 tdma->dma_chan_mask = devm_kzalloc(&pdev->dev, 1088 BITS_TO_LONGS(tdma->nr_channels) * sizeof(unsigned long), 1089 GFP_KERNEL); 1090 if (!tdma->dma_chan_mask) 1091 return -ENOMEM; 1092 1093 /* Enable all channels by default */ 1094 bitmap_fill(tdma->dma_chan_mask, tdma->nr_channels); 1095 1096 ret = of_property_read_u32_array(pdev->dev.of_node, "dma-channel-mask", 1097 (u32 *)tdma->dma_chan_mask, 1098 BITS_TO_U32(tdma->nr_channels)); 1099 if (ret < 0 && (ret != -EINVAL)) { 1100 dev_err(&pdev->dev, "dma-channel-mask is not complete.\n"); 1101 return ret; 1102 } 1103 1104 INIT_LIST_HEAD(&tdma->dma_dev.channels); 1105 for (i = 0; i < tdma->nr_channels; i++) { 1106 struct tegra_adma_chan *tdc = &tdma->channels[i]; 1107 1108 /* skip for reserved channels */ 1109 if (!test_bit(i, tdma->dma_chan_mask)) 1110 continue; 1111 1112 tdc->chan_addr = tdma->ch_base_addr + (cdata->ch_reg_size * i); 1113 1114 if (tdma->base_addr) { 1115 if (cdata->global_ch_fifo_base) 1116 tdc->global_ch_fifo_offset = cdata->global_ch_fifo_base + (4 * i); 1117 1118 if (cdata->global_ch_config_base) 1119 tdc->global_ch_config_offset = 1120 cdata->global_ch_config_base + (4 * i); 1121 } 1122 1123 tdc->irq = of_irq_get(pdev->dev.of_node, i); 1124 if (tdc->irq <= 0) { 1125 ret = tdc->irq ?: -ENXIO; 1126 goto irq_dispose; 1127 } 1128 1129 vchan_init(&tdc->vc, &tdma->dma_dev); 1130 tdc->vc.desc_free = tegra_adma_desc_free; 1131 tdc->tdma = tdma; 1132 } 1133 1134 pm_runtime_enable(&pdev->dev); 1135 1136 ret = pm_runtime_resume_and_get(&pdev->dev); 1137 if (ret < 0) 1138 goto rpm_disable; 1139 1140 ret = tegra_adma_init(tdma); 1141 if (ret) 1142 goto rpm_put; 1143 1144 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); 1145 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); 1146 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); 1147 1148 tdma->dma_dev.dev = &pdev->dev; 1149 tdma->dma_dev.device_alloc_chan_resources = 1150 tegra_adma_alloc_chan_resources; 1151 tdma->dma_dev.device_free_chan_resources = 1152 tegra_adma_free_chan_resources; 1153 tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending; 1154 tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic; 1155 tdma->dma_dev.device_config = tegra_adma_slave_config; 1156 tdma->dma_dev.device_tx_status = tegra_adma_tx_status; 1157 tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all; 1158 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1159 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1160 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 1161 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 1162 tdma->dma_dev.device_pause = tegra_adma_pause; 1163 tdma->dma_dev.device_resume = tegra_adma_resume; 1164 1165 ret = dma_async_device_register(&tdma->dma_dev); 1166 if (ret < 0) { 1167 dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret); 1168 goto rpm_put; 1169 } 1170 1171 ret = of_dma_controller_register(pdev->dev.of_node, 1172 tegra_dma_of_xlate, tdma); 1173 if (ret < 0) { 1174 dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret); 1175 goto dma_remove; 1176 } 1177 1178 pm_runtime_put(&pdev->dev); 1179 1180 dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n", 1181 tdma->nr_channels); 1182 1183 return 0; 1184 1185 dma_remove: 1186 dma_async_device_unregister(&tdma->dma_dev); 1187 rpm_put: 1188 pm_runtime_put_sync(&pdev->dev); 1189 rpm_disable: 1190 pm_runtime_disable(&pdev->dev); 1191 irq_dispose: 1192 while (--i >= 0) 1193 irq_dispose_mapping(tdma->channels[i].irq); 1194 1195 return ret; 1196 } 1197 1198 static void tegra_adma_remove(struct platform_device *pdev) 1199 { 1200 struct tegra_adma *tdma = platform_get_drvdata(pdev); 1201 int i; 1202 1203 of_dma_controller_free(pdev->dev.of_node); 1204 dma_async_device_unregister(&tdma->dma_dev); 1205 1206 for (i = 0; i < tdma->nr_channels; ++i) { 1207 if (tdma->channels[i].irq) 1208 irq_dispose_mapping(tdma->channels[i].irq); 1209 } 1210 1211 pm_runtime_disable(&pdev->dev); 1212 } 1213 1214 static const struct dev_pm_ops tegra_adma_dev_pm_ops = { 1215 SET_RUNTIME_PM_OPS(tegra_adma_runtime_suspend, 1216 tegra_adma_runtime_resume, NULL) 1217 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1218 pm_runtime_force_resume) 1219 }; 1220 1221 static struct platform_driver tegra_admac_driver = { 1222 .driver = { 1223 .name = "tegra-adma", 1224 .pm = &tegra_adma_dev_pm_ops, 1225 .of_match_table = tegra_adma_of_match, 1226 }, 1227 .probe = tegra_adma_probe, 1228 .remove = tegra_adma_remove, 1229 }; 1230 1231 module_platform_driver(tegra_admac_driver); 1232 1233 MODULE_ALIAS("platform:tegra210-adma"); 1234 MODULE_DESCRIPTION("NVIDIA Tegra ADMA driver"); 1235 MODULE_AUTHOR("Dara Ramesh <dramesh@nvidia.com>"); 1236 MODULE_AUTHOR("Jon Hunter <jonathanh@nvidia.com>"); 1237 MODULE_LICENSE("GPL v2"); 1238