1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright(c) 2020-2021 Intel Corporation. */ 3 #ifndef __CXL_MEM_H__ 4 #define __CXL_MEM_H__ 5 #include <uapi/linux/cxl_mem.h> 6 #include <linux/pci.h> 7 #include <linux/cdev.h> 8 #include <linux/uuid.h> 9 #include <linux/node.h> 10 #include <cxl/event.h> 11 #include <cxl/mailbox.h> 12 #include "cxl.h" 13 14 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ 15 #define CXLMDEV_STATUS_OFFSET 0x0 16 #define CXLMDEV_DEV_FATAL BIT(0) 17 #define CXLMDEV_FW_HALT BIT(1) 18 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2) 19 #define CXLMDEV_MS_NOT_READY 0 20 #define CXLMDEV_MS_READY 1 21 #define CXLMDEV_MS_ERROR 2 22 #define CXLMDEV_MS_DISABLED 3 23 #define CXLMDEV_READY(status) \ 24 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \ 25 CXLMDEV_MS_READY) 26 #define CXLMDEV_MBOX_IF_READY BIT(4) 27 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5) 28 #define CXLMDEV_RESET_NEEDED_NOT 0 29 #define CXLMDEV_RESET_NEEDED_COLD 1 30 #define CXLMDEV_RESET_NEEDED_WARM 2 31 #define CXLMDEV_RESET_NEEDED_HOT 3 32 #define CXLMDEV_RESET_NEEDED_CXL 4 33 #define CXLMDEV_RESET_NEEDED(status) \ 34 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \ 35 CXLMDEV_RESET_NEEDED_NOT) 36 37 /** 38 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device 39 * @dev: driver core device object 40 * @cdev: char dev core object for ioctl operations 41 * @cxlds: The device state backing this device 42 * @detach_work: active memdev lost a port in its ancestry 43 * @cxl_nvb: coordinate removal of @cxl_nvd if present 44 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem 45 * @endpoint: connection to the CXL port topology for this memory device 46 * @id: id number of this memdev instance. 47 * @depth: endpoint port depth 48 */ 49 struct cxl_memdev { 50 struct device dev; 51 struct cdev cdev; 52 struct cxl_dev_state *cxlds; 53 struct work_struct detach_work; 54 struct cxl_nvdimm_bridge *cxl_nvb; 55 struct cxl_nvdimm *cxl_nvd; 56 struct cxl_port *endpoint; 57 int id; 58 int depth; 59 }; 60 61 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev) 62 { 63 return container_of(dev, struct cxl_memdev, dev); 64 } 65 66 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled) 67 { 68 return to_cxl_port(cxled->cxld.dev.parent); 69 } 70 71 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd) 72 { 73 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent); 74 } 75 76 static inline struct cxl_memdev * 77 cxled_to_memdev(struct cxl_endpoint_decoder *cxled) 78 { 79 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); 80 81 return to_cxl_memdev(port->uport_dev); 82 } 83 84 bool is_cxl_memdev(const struct device *dev); 85 static inline bool is_cxl_endpoint(struct cxl_port *port) 86 { 87 return is_cxl_memdev(port->uport_dev); 88 } 89 90 struct cxl_memdev *devm_cxl_add_memdev(struct device *host, 91 struct cxl_dev_state *cxlds); 92 int devm_cxl_sanitize_setup_notifier(struct device *host, 93 struct cxl_memdev *cxlmd); 94 struct cxl_memdev_state; 95 int devm_cxl_setup_fw_upload(struct device *host, struct cxl_memdev_state *mds); 96 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, 97 resource_size_t base, resource_size_t len, 98 resource_size_t skipped); 99 100 #define CXL_NR_PARTITIONS_MAX 2 101 102 struct cxl_dpa_info { 103 u64 size; 104 struct cxl_dpa_part_info { 105 struct range range; 106 enum cxl_partition_mode mode; 107 } part[CXL_NR_PARTITIONS_MAX]; 108 int nr_partitions; 109 }; 110 111 int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info); 112 113 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, 114 struct cxl_memdev *cxlmd) 115 { 116 if (!port) 117 return NULL; 118 119 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); 120 } 121 122 /* 123 * Per CXL 3.0 Section 8.2.8.4.5.1 124 */ 125 #define CMD_CMD_RC_TABLE \ 126 C(SUCCESS, 0, NULL), \ 127 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \ 128 C(INPUT, -ENXIO, "cmd input was invalid"), \ 129 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \ 130 C(INTERNAL, -ENXIO, "internal device error"), \ 131 C(RETRY, -ENXIO, "temporary error, retry once"), \ 132 C(BUSY, -ENXIO, "ongoing background operation"), \ 133 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \ 134 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \ 135 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \ 136 C(FWAUTH, -ENXIO, "FW package authentication failed"), \ 137 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \ 138 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \ 139 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \ 140 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \ 141 C(PADDR, -EFAULT, "physical address specified is invalid"), \ 142 C(POISONLMT, -EBUSY, "poison injection limit has been reached"), \ 143 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \ 144 C(ABORT, -ENXIO, "background cmd was aborted by device"), \ 145 C(SECURITY, -ENXIO, "not valid in the current security state"), \ 146 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \ 147 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\ 148 C(PAYLOADLEN, -ENXIO, "invalid payload length"), \ 149 C(LOG, -ENXIO, "invalid or unsupported log page"), \ 150 C(INTERRUPTED, -ENXIO, "asynchronous event occured"), \ 151 C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \ 152 C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \ 153 C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \ 154 C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \ 155 C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \ 156 C(EXTLIST, -ENXIO, "invalid Extent List"), \ 157 158 #undef C 159 #define C(a, b, c) CXL_MBOX_CMD_RC_##a 160 enum { CMD_CMD_RC_TABLE }; 161 #undef C 162 #define C(a, b, c) { b, c } 163 struct cxl_mbox_cmd_rc { 164 int err; 165 const char *desc; 166 }; 167 168 static const 169 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE }; 170 #undef C 171 172 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd) 173 { 174 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc; 175 } 176 177 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd) 178 { 179 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err; 180 } 181 182 /* 183 * CXL 2.0 - Memory capacity multiplier 184 * See Section 8.2.9.5 185 * 186 * Volatile, Persistent, and Partition capacities are specified to be in 187 * multiples of 256MB - define a multiplier to convert to/from bytes. 188 */ 189 #define CXL_CAPACITY_MULTIPLIER SZ_256M 190 191 /* 192 * Event Interrupt Policy 193 * 194 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52 195 */ 196 enum cxl_event_int_mode { 197 CXL_INT_NONE = 0x00, 198 CXL_INT_MSI_MSIX = 0x01, 199 CXL_INT_FW = 0x02 200 }; 201 struct cxl_event_interrupt_policy { 202 u8 info_settings; 203 u8 warn_settings; 204 u8 failure_settings; 205 u8 fatal_settings; 206 } __packed; 207 208 /** 209 * struct cxl_event_state - Event log driver state 210 * 211 * @buf: Buffer to receive event data 212 * @log_lock: Serialize event_buf and log use 213 */ 214 struct cxl_event_state { 215 struct cxl_get_event_payload *buf; 216 struct mutex log_lock; 217 }; 218 219 /* Device enabled poison commands */ 220 enum poison_cmd_enabled_bits { 221 CXL_POISON_ENABLED_LIST, 222 CXL_POISON_ENABLED_INJECT, 223 CXL_POISON_ENABLED_CLEAR, 224 CXL_POISON_ENABLED_SCAN_CAPS, 225 CXL_POISON_ENABLED_SCAN_MEDIA, 226 CXL_POISON_ENABLED_SCAN_RESULTS, 227 CXL_POISON_ENABLED_MAX 228 }; 229 230 /* Device enabled security commands */ 231 enum security_cmd_enabled_bits { 232 CXL_SEC_ENABLED_SANITIZE, 233 CXL_SEC_ENABLED_SECURE_ERASE, 234 CXL_SEC_ENABLED_GET_SECURITY_STATE, 235 CXL_SEC_ENABLED_SET_PASSPHRASE, 236 CXL_SEC_ENABLED_DISABLE_PASSPHRASE, 237 CXL_SEC_ENABLED_UNLOCK, 238 CXL_SEC_ENABLED_FREEZE_SECURITY, 239 CXL_SEC_ENABLED_PASSPHRASE_SECURE_ERASE, 240 CXL_SEC_ENABLED_MAX 241 }; 242 243 /** 244 * struct cxl_poison_state - Driver poison state info 245 * 246 * @max_errors: Maximum media error records held in device cache 247 * @enabled_cmds: All poison commands enabled in the CEL 248 * @list_out: The poison list payload returned by device 249 * @lock: Protect reads of the poison list 250 * 251 * Reads of the poison list are synchronized to ensure that a reader 252 * does not get an incomplete list because their request overlapped 253 * (was interrupted or preceded by) another read request of the same 254 * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1 255 */ 256 struct cxl_poison_state { 257 u32 max_errors; 258 DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX); 259 struct cxl_mbox_poison_out *list_out; 260 struct mutex lock; /* Protect reads of poison list */ 261 }; 262 263 /* 264 * Get FW Info 265 * CXL rev 3.0 section 8.2.9.3.1; Table 8-56 266 */ 267 struct cxl_mbox_get_fw_info { 268 u8 num_slots; 269 u8 slot_info; 270 u8 activation_cap; 271 u8 reserved[13]; 272 char slot_1_revision[16]; 273 char slot_2_revision[16]; 274 char slot_3_revision[16]; 275 char slot_4_revision[16]; 276 } __packed; 277 278 #define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2, 0) 279 #define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5, 3) 280 #define CXL_FW_INFO_SLOT_INFO_NEXT_SHIFT 3 281 #define CXL_FW_INFO_ACTIVATION_CAP_HAS_LIVE_ACTIVATE BIT(0) 282 283 /* 284 * Transfer FW Input Payload 285 * CXL rev 3.0 section 8.2.9.3.2; Table 8-57 286 */ 287 struct cxl_mbox_transfer_fw { 288 u8 action; 289 u8 slot; 290 u8 reserved[2]; 291 __le32 offset; 292 u8 reserved2[0x78]; 293 u8 data[]; 294 } __packed; 295 296 #define CXL_FW_TRANSFER_ACTION_FULL 0x0 297 #define CXL_FW_TRANSFER_ACTION_INITIATE 0x1 298 #define CXL_FW_TRANSFER_ACTION_CONTINUE 0x2 299 #define CXL_FW_TRANSFER_ACTION_END 0x3 300 #define CXL_FW_TRANSFER_ACTION_ABORT 0x4 301 302 /* 303 * CXL rev 3.0 section 8.2.9.3.2 mandates 128-byte alignment for FW packages 304 * and for each part transferred in a Transfer FW command. 305 */ 306 #define CXL_FW_TRANSFER_ALIGNMENT 128 307 308 /* 309 * Activate FW Input Payload 310 * CXL rev 3.0 section 8.2.9.3.3; Table 8-58 311 */ 312 struct cxl_mbox_activate_fw { 313 u8 action; 314 u8 slot; 315 } __packed; 316 317 #define CXL_FW_ACTIVATE_ONLINE 0x0 318 #define CXL_FW_ACTIVATE_OFFLINE 0x1 319 320 /* FW state bits */ 321 #define CXL_FW_STATE_BITS 32 322 #define CXL_FW_CANCEL 0 323 324 /** 325 * struct cxl_fw_state - Firmware upload / activation state 326 * 327 * @state: fw_uploader state bitmask 328 * @oneshot: whether the fw upload fits in a single transfer 329 * @num_slots: Number of FW slots available 330 * @cur_slot: Slot number currently active 331 * @next_slot: Slot number for the new firmware 332 */ 333 struct cxl_fw_state { 334 DECLARE_BITMAP(state, CXL_FW_STATE_BITS); 335 bool oneshot; 336 int num_slots; 337 int cur_slot; 338 int next_slot; 339 }; 340 341 /** 342 * struct cxl_security_state - Device security state 343 * 344 * @state: state of last security operation 345 * @enabled_cmds: All security commands enabled in the CEL 346 * @poll_tmo_secs: polling timeout 347 * @sanitize_active: sanitize completion pending 348 * @poll_dwork: polling work item 349 * @sanitize_node: sanitation sysfs file to notify 350 */ 351 struct cxl_security_state { 352 unsigned long state; 353 DECLARE_BITMAP(enabled_cmds, CXL_SEC_ENABLED_MAX); 354 int poll_tmo_secs; 355 bool sanitize_active; 356 struct delayed_work poll_dwork; 357 struct kernfs_node *sanitize_node; 358 }; 359 360 /* 361 * enum cxl_devtype - delineate type-2 from a generic type-3 device 362 * @CXL_DEVTYPE_DEVMEM - Vendor specific CXL Type-2 device implementing HDM-D or 363 * HDM-DB, no requirement that this device implements a 364 * mailbox, or other memory-device-standard manageability 365 * flows. 366 * @CXL_DEVTYPE_CLASSMEM - Common class definition of a CXL Type-3 device with 367 * HDM-H and class-mandatory memory device registers 368 */ 369 enum cxl_devtype { 370 CXL_DEVTYPE_DEVMEM, 371 CXL_DEVTYPE_CLASSMEM, 372 }; 373 374 /** 375 * struct cxl_dpa_perf - DPA performance property entry 376 * @dpa_range: range for DPA address 377 * @coord: QoS performance data (i.e. latency, bandwidth) 378 * @cdat_coord: raw QoS performance data from CDAT 379 * @qos_class: QoS Class cookies 380 */ 381 struct cxl_dpa_perf { 382 struct range dpa_range; 383 struct access_coordinate coord[ACCESS_COORDINATE_MAX]; 384 struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX]; 385 int qos_class; 386 }; 387 388 /** 389 * struct cxl_dpa_partition - DPA partition descriptor 390 * @res: shortcut to the partition in the DPA resource tree (cxlds->dpa_res) 391 * @perf: performance attributes of the partition from CDAT 392 * @mode: operation mode for the DPA capacity, e.g. ram, pmem, dynamic... 393 */ 394 struct cxl_dpa_partition { 395 struct resource res; 396 struct cxl_dpa_perf perf; 397 enum cxl_partition_mode mode; 398 }; 399 400 /** 401 * struct cxl_dev_state - The driver device state 402 * 403 * cxl_dev_state represents the CXL driver/device state. It provides an 404 * interface to mailbox commands as well as some cached data about the device. 405 * Currently only memory devices are represented. 406 * 407 * @dev: The device associated with this CXL state 408 * @cxlmd: The device representing the CXL.mem capabilities of @dev 409 * @reg_map: component and ras register mapping parameters 410 * @regs: Parsed register blocks 411 * @cxl_dvsec: Offset to the PCIe device DVSEC 412 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) 413 * @media_ready: Indicate whether the device media is usable 414 * @dpa_res: Overall DPA resource tree for the device 415 * @part: DPA partition array 416 * @nr_partitions: Number of DPA partitions 417 * @serial: PCIe Device Serial Number 418 * @type: Generic Memory Class device or Vendor Specific Memory device 419 * @cxl_mbox: CXL mailbox context 420 * @cxlfs: CXL features context 421 */ 422 struct cxl_dev_state { 423 struct device *dev; 424 struct cxl_memdev *cxlmd; 425 struct cxl_register_map reg_map; 426 struct cxl_regs regs; 427 int cxl_dvsec; 428 bool rcd; 429 bool media_ready; 430 struct resource dpa_res; 431 struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX]; 432 unsigned int nr_partitions; 433 u64 serial; 434 enum cxl_devtype type; 435 struct cxl_mailbox cxl_mbox; 436 #ifdef CONFIG_CXL_FEATURES 437 struct cxl_features_state *cxlfs; 438 #endif 439 }; 440 441 static inline resource_size_t cxl_pmem_size(struct cxl_dev_state *cxlds) 442 { 443 /* 444 * Static PMEM may be at partition index 0 when there is no static RAM 445 * capacity. 446 */ 447 for (int i = 0; i < cxlds->nr_partitions; i++) 448 if (cxlds->part[i].mode == CXL_PARTMODE_PMEM) 449 return resource_size(&cxlds->part[i].res); 450 return 0; 451 } 452 453 static inline struct cxl_dev_state *mbox_to_cxlds(struct cxl_mailbox *cxl_mbox) 454 { 455 return dev_get_drvdata(cxl_mbox->host); 456 } 457 458 /** 459 * struct cxl_memdev_state - Generic Type-3 Memory Device Class driver data 460 * 461 * CXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines 462 * common memory device functionality like the presence of a mailbox and 463 * the functionality related to that like Identify Memory Device and Get 464 * Partition Info 465 * @cxlds: Core driver state common across Type-2 and Type-3 devices 466 * @lsa_size: Size of Label Storage Area 467 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device) 468 * @firmware_version: Firmware version for the memory device. 469 * @total_bytes: sum of all possible capacities 470 * @volatile_only_bytes: hard volatile capacity 471 * @persistent_only_bytes: hard persistent capacity 472 * @partition_align_bytes: alignment size for partition-able capacity 473 * @active_volatile_bytes: sum of hard + soft volatile 474 * @active_persistent_bytes: sum of hard + soft persistent 475 * @event: event log driver state 476 * @poison: poison driver state info 477 * @security: security driver state info 478 * @fw: firmware upload / activation state 479 * @mce_notifier: MCE notifier 480 * 481 * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for 482 * details on capacity parameters. 483 */ 484 struct cxl_memdev_state { 485 struct cxl_dev_state cxlds; 486 size_t lsa_size; 487 char firmware_version[0x10]; 488 u64 total_bytes; 489 u64 volatile_only_bytes; 490 u64 persistent_only_bytes; 491 u64 partition_align_bytes; 492 u64 active_volatile_bytes; 493 u64 active_persistent_bytes; 494 495 struct cxl_event_state event; 496 struct cxl_poison_state poison; 497 struct cxl_security_state security; 498 struct cxl_fw_state fw; 499 struct notifier_block mce_notifier; 500 }; 501 502 static inline struct cxl_memdev_state * 503 to_cxl_memdev_state(struct cxl_dev_state *cxlds) 504 { 505 if (cxlds->type != CXL_DEVTYPE_CLASSMEM) 506 return NULL; 507 return container_of(cxlds, struct cxl_memdev_state, cxlds); 508 } 509 510 enum cxl_opcode { 511 CXL_MBOX_OP_INVALID = 0x0000, 512 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID, 513 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100, 514 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101, 515 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102, 516 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103, 517 CXL_MBOX_OP_GET_FW_INFO = 0x0200, 518 CXL_MBOX_OP_TRANSFER_FW = 0x0201, 519 CXL_MBOX_OP_ACTIVATE_FW = 0x0202, 520 CXL_MBOX_OP_GET_TIMESTAMP = 0x0300, 521 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301, 522 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400, 523 CXL_MBOX_OP_GET_LOG = 0x0401, 524 CXL_MBOX_OP_GET_LOG_CAPS = 0x0402, 525 CXL_MBOX_OP_CLEAR_LOG = 0x0403, 526 CXL_MBOX_OP_GET_SUP_LOG_SUBLIST = 0x0405, 527 CXL_MBOX_OP_GET_SUPPORTED_FEATURES = 0x0500, 528 CXL_MBOX_OP_GET_FEATURE = 0x0501, 529 CXL_MBOX_OP_SET_FEATURE = 0x0502, 530 CXL_MBOX_OP_IDENTIFY = 0x4000, 531 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, 532 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, 533 CXL_MBOX_OP_GET_LSA = 0x4102, 534 CXL_MBOX_OP_SET_LSA = 0x4103, 535 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200, 536 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201, 537 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202, 538 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203, 539 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204, 540 CXL_MBOX_OP_GET_POISON = 0x4300, 541 CXL_MBOX_OP_INJECT_POISON = 0x4301, 542 CXL_MBOX_OP_CLEAR_POISON = 0x4302, 543 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303, 544 CXL_MBOX_OP_SCAN_MEDIA = 0x4304, 545 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305, 546 CXL_MBOX_OP_SANITIZE = 0x4400, 547 CXL_MBOX_OP_SECURE_ERASE = 0x4401, 548 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500, 549 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501, 550 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502, 551 CXL_MBOX_OP_UNLOCK = 0x4503, 552 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504, 553 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505, 554 CXL_MBOX_OP_MAX = 0x10000 555 }; 556 557 #define DEFINE_CXL_CEL_UUID \ 558 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \ 559 0x3b, 0x3f, 0x17) 560 561 #define DEFINE_CXL_VENDOR_DEBUG_UUID \ 562 UUID_INIT(0x5e1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \ 563 0x40, 0x3d, 0x86) 564 565 struct cxl_mbox_get_supported_logs { 566 __le16 entries; 567 u8 rsvd[6]; 568 struct cxl_gsl_entry { 569 uuid_t uuid; 570 __le32 size; 571 } __packed entry[]; 572 } __packed; 573 574 struct cxl_cel_entry { 575 __le16 opcode; 576 __le16 effect; 577 } __packed; 578 579 struct cxl_mbox_get_log { 580 uuid_t uuid; 581 __le32 offset; 582 __le32 length; 583 } __packed; 584 585 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */ 586 struct cxl_mbox_identify { 587 char fw_revision[0x10]; 588 __le64 total_capacity; 589 __le64 volatile_capacity; 590 __le64 persistent_capacity; 591 __le64 partition_align; 592 __le16 info_event_log_size; 593 __le16 warning_event_log_size; 594 __le16 failure_event_log_size; 595 __le16 fatal_event_log_size; 596 __le32 lsa_size; 597 u8 poison_list_max_mer[3]; 598 __le16 inject_poison_limit; 599 u8 poison_caps; 600 u8 qos_telemetry_caps; 601 } __packed; 602 603 /* 604 * General Media Event Record UUID 605 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43 606 */ 607 #define CXL_EVENT_GEN_MEDIA_UUID \ 608 UUID_INIT(0xfbcd0a77, 0xc260, 0x417f, 0x85, 0xa9, 0x08, 0x8b, 0x16, \ 609 0x21, 0xeb, 0xa6) 610 611 /* 612 * DRAM Event Record UUID 613 * CXL rev 3.0 section 8.2.9.2.1.2; Table 8-44 614 */ 615 #define CXL_EVENT_DRAM_UUID \ 616 UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab, 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, \ 617 0x5c, 0x96, 0x24) 618 619 /* 620 * Memory Module Event Record UUID 621 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45 622 */ 623 #define CXL_EVENT_MEM_MODULE_UUID \ 624 UUID_INIT(0xfe927475, 0xdd59, 0x4339, 0xa5, 0x86, 0x79, 0xba, 0xb1, \ 625 0x13, 0xb7, 0x74) 626 627 /* 628 * Get Event Records output payload 629 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50 630 */ 631 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0) 632 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1) 633 struct cxl_get_event_payload { 634 u8 flags; 635 u8 reserved1; 636 __le16 overflow_err_count; 637 __le64 first_overflow_timestamp; 638 __le64 last_overflow_timestamp; 639 __le16 record_count; 640 u8 reserved2[10]; 641 struct cxl_event_record_raw records[]; 642 } __packed; 643 644 /* 645 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49 646 */ 647 enum cxl_event_log_type { 648 CXL_EVENT_TYPE_INFO = 0x00, 649 CXL_EVENT_TYPE_WARN, 650 CXL_EVENT_TYPE_FAIL, 651 CXL_EVENT_TYPE_FATAL, 652 CXL_EVENT_TYPE_MAX 653 }; 654 655 /* 656 * Clear Event Records input payload 657 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51 658 */ 659 struct cxl_mbox_clear_event_payload { 660 u8 event_log; /* enum cxl_event_log_type */ 661 u8 clear_flags; 662 u8 nr_recs; 663 u8 reserved[3]; 664 __le16 handles[]; 665 } __packed; 666 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX 667 668 struct cxl_mbox_get_partition_info { 669 __le64 active_volatile_cap; 670 __le64 active_persistent_cap; 671 __le64 next_volatile_cap; 672 __le64 next_persistent_cap; 673 } __packed; 674 675 struct cxl_mbox_get_lsa { 676 __le32 offset; 677 __le32 length; 678 } __packed; 679 680 struct cxl_mbox_set_lsa { 681 __le32 offset; 682 __le32 reserved; 683 u8 data[]; 684 } __packed; 685 686 struct cxl_mbox_set_partition_info { 687 __le64 volatile_capacity; 688 u8 flags; 689 } __packed; 690 691 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0) 692 693 /* Get Health Info Output Payload CXL 3.2 Spec 8.2.10.9.3.1 Table 8-148 */ 694 struct cxl_mbox_get_health_info_out { 695 u8 health_status; 696 u8 media_status; 697 u8 additional_status; 698 u8 life_used; 699 __le16 device_temperature; 700 __le32 dirty_shutdown_cnt; 701 __le32 corrected_volatile_error_cnt; 702 __le32 corrected_persistent_error_cnt; 703 } __packed; 704 705 /* Set Shutdown State Input Payload CXL 3.2 Spec 8.2.10.9.3.5 Table 8-152 */ 706 struct cxl_mbox_set_shutdown_state_in { 707 u8 state; 708 } __packed; 709 710 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */ 711 struct cxl_mbox_set_timestamp_in { 712 __le64 timestamp; 713 714 } __packed; 715 716 /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */ 717 struct cxl_mbox_poison_in { 718 __le64 offset; 719 __le64 length; 720 } __packed; 721 722 struct cxl_mbox_poison_out { 723 u8 flags; 724 u8 rsvd1; 725 __le64 overflow_ts; 726 __le16 count; 727 u8 rsvd2[20]; 728 struct cxl_poison_record { 729 __le64 address; 730 __le32 length; 731 __le32 rsvd; 732 } __packed record[]; 733 } __packed; 734 735 /* 736 * Get Poison List address field encodes the starting 737 * address of poison, and the source of the poison. 738 */ 739 #define CXL_POISON_START_MASK GENMASK_ULL(63, 6) 740 #define CXL_POISON_SOURCE_MASK GENMASK(2, 0) 741 742 /* Get Poison List record length is in units of 64 bytes */ 743 #define CXL_POISON_LEN_MULT 64 744 745 /* Kernel defined maximum for a list of poison errors */ 746 #define CXL_POISON_LIST_MAX 1024 747 748 /* Get Poison List: Payload out flags */ 749 #define CXL_POISON_FLAG_MORE BIT(0) 750 #define CXL_POISON_FLAG_OVERFLOW BIT(1) 751 #define CXL_POISON_FLAG_SCANNING BIT(2) 752 753 /* Get Poison List: Poison Source */ 754 #define CXL_POISON_SOURCE_UNKNOWN 0 755 #define CXL_POISON_SOURCE_EXTERNAL 1 756 #define CXL_POISON_SOURCE_INTERNAL 2 757 #define CXL_POISON_SOURCE_INJECTED 3 758 #define CXL_POISON_SOURCE_VENDOR 7 759 760 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */ 761 struct cxl_mbox_inject_poison { 762 __le64 address; 763 }; 764 765 /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */ 766 struct cxl_mbox_clear_poison { 767 __le64 address; 768 u8 write_data[CXL_POISON_LEN_MULT]; 769 } __packed; 770 771 /** 772 * struct cxl_mem_command - Driver representation of a memory device command 773 * @info: Command information as it exists for the UAPI 774 * @opcode: The actual bits used for the mailbox protocol 775 * @flags: Set of flags effecting driver behavior. 776 * 777 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag 778 * will be enabled by the driver regardless of what hardware may have 779 * advertised. 780 * 781 * The cxl_mem_command is the driver's internal representation of commands that 782 * are supported by the driver. Some of these commands may not be supported by 783 * the hardware. The driver will use @info to validate the fields passed in by 784 * the user then submit the @opcode to the hardware. 785 * 786 * See struct cxl_command_info. 787 */ 788 struct cxl_mem_command { 789 struct cxl_command_info info; 790 enum cxl_opcode opcode; 791 u32 flags; 792 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0) 793 }; 794 795 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01 796 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02 797 #define CXL_PMEM_SEC_STATE_LOCKED 0x04 798 #define CXL_PMEM_SEC_STATE_FROZEN 0x08 799 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10 800 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20 801 802 /* set passphrase input payload */ 803 struct cxl_set_pass { 804 u8 type; 805 u8 reserved[31]; 806 /* CXL field using NVDIMM define, same length */ 807 u8 old_pass[NVDIMM_PASSPHRASE_LEN]; 808 u8 new_pass[NVDIMM_PASSPHRASE_LEN]; 809 } __packed; 810 811 /* disable passphrase input payload */ 812 struct cxl_disable_pass { 813 u8 type; 814 u8 reserved[31]; 815 u8 pass[NVDIMM_PASSPHRASE_LEN]; 816 } __packed; 817 818 /* passphrase secure erase payload */ 819 struct cxl_pass_erase { 820 u8 type; 821 u8 reserved[31]; 822 u8 pass[NVDIMM_PASSPHRASE_LEN]; 823 } __packed; 824 825 enum { 826 CXL_PMEM_SEC_PASS_MASTER = 0, 827 CXL_PMEM_SEC_PASS_USER, 828 }; 829 830 int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox, 831 struct cxl_mbox_cmd *cmd); 832 int cxl_dev_state_identify(struct cxl_memdev_state *mds); 833 int cxl_await_media_ready(struct cxl_dev_state *cxlds); 834 int cxl_enumerate_cmds(struct cxl_memdev_state *mds); 835 int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info); 836 struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev); 837 void set_exclusive_cxl_commands(struct cxl_memdev_state *mds, 838 unsigned long *cmds); 839 void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds, 840 unsigned long *cmds); 841 void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status); 842 void cxl_event_trace_record(const struct cxl_memdev *cxlmd, 843 enum cxl_event_log_type type, 844 enum cxl_event_type event_type, 845 const uuid_t *uuid, union cxl_event *evt); 846 int cxl_get_dirty_count(struct cxl_memdev_state *mds, u32 *count); 847 int cxl_arm_dirty_shutdown(struct cxl_memdev_state *mds); 848 int cxl_set_timestamp(struct cxl_memdev_state *mds); 849 int cxl_poison_state_init(struct cxl_memdev_state *mds); 850 int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len, 851 struct cxl_region *cxlr); 852 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd); 853 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa); 854 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa); 855 856 #ifdef CONFIG_CXL_SUSPEND 857 void cxl_mem_active_inc(void); 858 void cxl_mem_active_dec(void); 859 #else 860 static inline void cxl_mem_active_inc(void) 861 { 862 } 863 static inline void cxl_mem_active_dec(void) 864 { 865 } 866 #endif 867 868 int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd); 869 870 /** 871 * struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities 872 * @regs: mapped registers, see devm_cxl_setup_hdm() 873 * @decoder_count: number of decoders for this port 874 * @target_count: for switch decoders, max downstream port targets 875 * @interleave_mask: interleave granularity capability, see check_interleave_cap() 876 * @iw_cap_mask: bitmask of supported interleave ways, see check_interleave_cap() 877 * @port: mapped cxl_port, see devm_cxl_setup_hdm() 878 */ 879 struct cxl_hdm { 880 struct cxl_component_regs regs; 881 unsigned int decoder_count; 882 unsigned int target_count; 883 unsigned int interleave_mask; 884 unsigned long iw_cap_mask; 885 struct cxl_port *port; 886 }; 887 888 struct seq_file; 889 struct dentry *cxl_debugfs_create_dir(const char *dir); 890 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); 891 #endif /* __CXL_MEM_H__ */ 892