1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Cryptographic API. 4 // 5 // Support for Samsung S5PV210 and Exynos HW acceleration. 6 // 7 // Copyright (C) 2011 NetUP Inc. All rights reserved. 8 // Copyright (c) 2017 Samsung Electronics Co., Ltd. All rights reserved. 9 // 10 // Hash part based on omap-sham.c driver. 11 12 #include <linux/clk.h> 13 #include <linux/crypto.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/errno.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 #include <linux/scatterlist.h> 25 26 #include <crypto/ctr.h> 27 #include <crypto/aes.h> 28 #include <crypto/algapi.h> 29 #include <crypto/scatterwalk.h> 30 31 #include <crypto/hash.h> 32 #include <crypto/md5.h> 33 #include <crypto/sha1.h> 34 #include <crypto/sha2.h> 35 #include <crypto/internal/hash.h> 36 37 #define _SBF(s, v) ((v) << (s)) 38 39 /* Feed control registers */ 40 #define SSS_REG_FCINTSTAT 0x0000 41 #define SSS_FCINTSTAT_HPARTINT BIT(7) 42 #define SSS_FCINTSTAT_HDONEINT BIT(5) 43 #define SSS_FCINTSTAT_BRDMAINT BIT(3) 44 #define SSS_FCINTSTAT_BTDMAINT BIT(2) 45 #define SSS_FCINTSTAT_HRDMAINT BIT(1) 46 #define SSS_FCINTSTAT_PKDMAINT BIT(0) 47 48 #define SSS_REG_FCINTENSET 0x0004 49 #define SSS_FCINTENSET_HPARTINTENSET BIT(7) 50 #define SSS_FCINTENSET_HDONEINTENSET BIT(5) 51 #define SSS_FCINTENSET_BRDMAINTENSET BIT(3) 52 #define SSS_FCINTENSET_BTDMAINTENSET BIT(2) 53 #define SSS_FCINTENSET_HRDMAINTENSET BIT(1) 54 #define SSS_FCINTENSET_PKDMAINTENSET BIT(0) 55 56 #define SSS_REG_FCINTENCLR 0x0008 57 #define SSS_FCINTENCLR_HPARTINTENCLR BIT(7) 58 #define SSS_FCINTENCLR_HDONEINTENCLR BIT(5) 59 #define SSS_FCINTENCLR_BRDMAINTENCLR BIT(3) 60 #define SSS_FCINTENCLR_BTDMAINTENCLR BIT(2) 61 #define SSS_FCINTENCLR_HRDMAINTENCLR BIT(1) 62 #define SSS_FCINTENCLR_PKDMAINTENCLR BIT(0) 63 64 #define SSS_REG_FCINTPEND 0x000C 65 #define SSS_FCINTPEND_HPARTINTP BIT(7) 66 #define SSS_FCINTPEND_HDONEINTP BIT(5) 67 #define SSS_FCINTPEND_BRDMAINTP BIT(3) 68 #define SSS_FCINTPEND_BTDMAINTP BIT(2) 69 #define SSS_FCINTPEND_HRDMAINTP BIT(1) 70 #define SSS_FCINTPEND_PKDMAINTP BIT(0) 71 72 #define SSS_REG_FCFIFOSTAT 0x0010 73 #define SSS_FCFIFOSTAT_BRFIFOFUL BIT(7) 74 #define SSS_FCFIFOSTAT_BRFIFOEMP BIT(6) 75 #define SSS_FCFIFOSTAT_BTFIFOFUL BIT(5) 76 #define SSS_FCFIFOSTAT_BTFIFOEMP BIT(4) 77 #define SSS_FCFIFOSTAT_HRFIFOFUL BIT(3) 78 #define SSS_FCFIFOSTAT_HRFIFOEMP BIT(2) 79 #define SSS_FCFIFOSTAT_PKFIFOFUL BIT(1) 80 #define SSS_FCFIFOSTAT_PKFIFOEMP BIT(0) 81 82 #define SSS_REG_FCFIFOCTRL 0x0014 83 #define SSS_FCFIFOCTRL_DESSEL BIT(2) 84 #define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00) 85 #define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01) 86 #define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02) 87 #define SSS_HASHIN_MASK _SBF(0, 0x03) 88 89 #define SSS_REG_FCBRDMAS 0x0020 90 #define SSS_REG_FCBRDMAL 0x0024 91 #define SSS_REG_FCBRDMAC 0x0028 92 #define SSS_FCBRDMAC_BYTESWAP BIT(1) 93 #define SSS_FCBRDMAC_FLUSH BIT(0) 94 95 #define SSS_REG_FCBTDMAS 0x0030 96 #define SSS_REG_FCBTDMAL 0x0034 97 #define SSS_REG_FCBTDMAC 0x0038 98 #define SSS_FCBTDMAC_BYTESWAP BIT(1) 99 #define SSS_FCBTDMAC_FLUSH BIT(0) 100 101 #define SSS_REG_FCHRDMAS 0x0040 102 #define SSS_REG_FCHRDMAL 0x0044 103 #define SSS_REG_FCHRDMAC 0x0048 104 #define SSS_FCHRDMAC_BYTESWAP BIT(1) 105 #define SSS_FCHRDMAC_FLUSH BIT(0) 106 107 #define SSS_REG_FCPKDMAS 0x0050 108 #define SSS_REG_FCPKDMAL 0x0054 109 #define SSS_REG_FCPKDMAC 0x0058 110 #define SSS_FCPKDMAC_BYTESWAP BIT(3) 111 #define SSS_FCPKDMAC_DESCEND BIT(2) 112 #define SSS_FCPKDMAC_TRANSMIT BIT(1) 113 #define SSS_FCPKDMAC_FLUSH BIT(0) 114 115 #define SSS_REG_FCPKDMAO 0x005C 116 117 /* AES registers */ 118 #define SSS_REG_AES_CONTROL 0x00 119 #define SSS_AES_BYTESWAP_DI BIT(11) 120 #define SSS_AES_BYTESWAP_DO BIT(10) 121 #define SSS_AES_BYTESWAP_IV BIT(9) 122 #define SSS_AES_BYTESWAP_CNT BIT(8) 123 #define SSS_AES_BYTESWAP_KEY BIT(7) 124 #define SSS_AES_KEY_CHANGE_MODE BIT(6) 125 #define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00) 126 #define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01) 127 #define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02) 128 #define SSS_AES_FIFO_MODE BIT(3) 129 #define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00) 130 #define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01) 131 #define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02) 132 #define SSS_AES_MODE_DECRYPT BIT(0) 133 134 #define SSS_REG_AES_STATUS 0x04 135 #define SSS_AES_BUSY BIT(2) 136 #define SSS_AES_INPUT_READY BIT(1) 137 #define SSS_AES_OUTPUT_READY BIT(0) 138 139 #define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2)) 140 #define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2)) 141 #define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2)) 142 #define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2)) 143 #define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2)) 144 145 #define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg)) 146 #define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg)) 147 #define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg)) 148 149 #define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg) 150 #define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \ 151 SSS_AES_REG(dev, reg)) 152 153 /* HW engine modes */ 154 #define FLAGS_AES_DECRYPT BIT(0) 155 #define FLAGS_AES_MODE_MASK _SBF(1, 0x03) 156 #define FLAGS_AES_CBC _SBF(1, 0x01) 157 #define FLAGS_AES_CTR _SBF(1, 0x02) 158 159 #define AES_KEY_LEN 16 160 #define CRYPTO_QUEUE_LEN 1 161 162 /* HASH registers */ 163 #define SSS_REG_HASH_CTRL 0x00 164 165 #define SSS_HASH_USER_IV_EN BIT(5) 166 #define SSS_HASH_INIT_BIT BIT(4) 167 #define SSS_HASH_ENGINE_SHA1 _SBF(1, 0x00) 168 #define SSS_HASH_ENGINE_MD5 _SBF(1, 0x01) 169 #define SSS_HASH_ENGINE_SHA256 _SBF(1, 0x02) 170 171 #define SSS_HASH_ENGINE_MASK _SBF(1, 0x03) 172 173 #define SSS_REG_HASH_CTRL_PAUSE 0x04 174 175 #define SSS_HASH_PAUSE BIT(0) 176 177 #define SSS_REG_HASH_CTRL_FIFO 0x08 178 179 #define SSS_HASH_FIFO_MODE_DMA BIT(0) 180 #define SSS_HASH_FIFO_MODE_CPU 0 181 182 #define SSS_REG_HASH_CTRL_SWAP 0x0C 183 184 #define SSS_HASH_BYTESWAP_DI BIT(3) 185 #define SSS_HASH_BYTESWAP_DO BIT(2) 186 #define SSS_HASH_BYTESWAP_IV BIT(1) 187 #define SSS_HASH_BYTESWAP_KEY BIT(0) 188 189 #define SSS_REG_HASH_STATUS 0x10 190 191 #define SSS_HASH_STATUS_MSG_DONE BIT(6) 192 #define SSS_HASH_STATUS_PARTIAL_DONE BIT(4) 193 #define SSS_HASH_STATUS_BUFFER_READY BIT(0) 194 195 #define SSS_REG_HASH_MSG_SIZE_LOW 0x20 196 #define SSS_REG_HASH_MSG_SIZE_HIGH 0x24 197 198 #define SSS_REG_HASH_PRE_MSG_SIZE_LOW 0x28 199 #define SSS_REG_HASH_PRE_MSG_SIZE_HIGH 0x2C 200 201 #define SSS_REG_HASH_IV(s) (0xB0 + ((s) << 2)) 202 #define SSS_REG_HASH_OUT(s) (0x100 + ((s) << 2)) 203 204 #define HASH_BLOCK_SIZE 64 205 #define HASH_REG_SIZEOF 4 206 #define HASH_MD5_MAX_REG (MD5_DIGEST_SIZE / HASH_REG_SIZEOF) 207 #define HASH_SHA1_MAX_REG (SHA1_DIGEST_SIZE / HASH_REG_SIZEOF) 208 #define HASH_SHA256_MAX_REG (SHA256_DIGEST_SIZE / HASH_REG_SIZEOF) 209 210 /* 211 * HASH bit numbers, used by device, setting in dev->hash_flags with 212 * functions set_bit(), clear_bit() or tested with test_bit() or BIT(), 213 * to keep HASH state BUSY or FREE, or to signal state from irq_handler 214 * to hash_tasklet. SGS keep track of allocated memory for scatterlist 215 */ 216 #define HASH_FLAGS_BUSY 0 217 #define HASH_FLAGS_FINAL 1 218 #define HASH_FLAGS_DMA_ACTIVE 2 219 #define HASH_FLAGS_OUTPUT_READY 3 220 #define HASH_FLAGS_DMA_READY 4 221 #define HASH_FLAGS_SGS_COPIED 5 222 #define HASH_FLAGS_SGS_ALLOCED 6 223 224 /* HASH HW constants */ 225 #define BUFLEN HASH_BLOCK_SIZE 226 227 #define SSS_HASH_QUEUE_LENGTH 10 228 229 /** 230 * struct samsung_aes_variant - platform specific SSS driver data 231 * @aes_offset: AES register offset from SSS module's base. 232 * @hash_offset: HASH register offset from SSS module's base. 233 * @clk_names: names of clocks needed to run SSS IP 234 * 235 * Specifies platform specific configuration of SSS module. 236 * Note: A structure for driver specific platform data is used for future 237 * expansion of its usage. 238 */ 239 struct samsung_aes_variant { 240 unsigned int aes_offset; 241 unsigned int hash_offset; 242 const char *clk_names[2]; 243 }; 244 245 struct s5p_aes_reqctx { 246 unsigned long mode; 247 }; 248 249 struct s5p_aes_ctx { 250 struct s5p_aes_dev *dev; 251 252 u8 aes_key[AES_MAX_KEY_SIZE]; 253 u8 nonce[CTR_RFC3686_NONCE_SIZE]; 254 int keylen; 255 }; 256 257 /** 258 * struct s5p_aes_dev - Crypto device state container 259 * @dev: Associated device 260 * @clk: Clock for accessing hardware 261 * @pclk: APB bus clock necessary to access the hardware 262 * @ioaddr: Mapped IO memory region 263 * @aes_ioaddr: Per-varian offset for AES block IO memory 264 * @irq_fc: Feed control interrupt line 265 * @req: Crypto request currently handled by the device 266 * @ctx: Configuration for currently handled crypto request 267 * @sg_src: Scatter list with source data for currently handled block 268 * in device. This is DMA-mapped into device. 269 * @sg_dst: Scatter list with destination data for currently handled block 270 * in device. This is DMA-mapped into device. 271 * @sg_src_cpy: In case of unaligned access, copied scatter list 272 * with source data. 273 * @sg_dst_cpy: In case of unaligned access, copied scatter list 274 * with destination data. 275 * @tasklet: New request scheduling jib 276 * @queue: Crypto queue 277 * @busy: Indicates whether the device is currently handling some request 278 * thus it uses some of the fields from this state, like: 279 * req, ctx, sg_src/dst (and copies). This essentially 280 * protects against concurrent access to these fields. 281 * @lock: Lock for protecting both access to device hardware registers 282 * and fields related to current request (including the busy field). 283 * @res: Resources for hash. 284 * @io_hash_base: Per-variant offset for HASH block IO memory. 285 * @hash_lock: Lock for protecting hash_req, hash_queue and hash_flags 286 * variable. 287 * @hash_flags: Flags for current HASH op. 288 * @hash_queue: Async hash queue. 289 * @hash_tasklet: New HASH request scheduling job. 290 * @xmit_buf: Buffer for current HASH request transfer into SSS block. 291 * @hash_req: Current request sending to SSS HASH block. 292 * @hash_sg_iter: Scatterlist transferred through DMA into SSS HASH block. 293 * @hash_sg_cnt: Counter for hash_sg_iter. 294 * 295 * @use_hash: true if HASH algs enabled 296 */ 297 struct s5p_aes_dev { 298 struct device *dev; 299 struct clk *clk; 300 struct clk *pclk; 301 void __iomem *ioaddr; 302 void __iomem *aes_ioaddr; 303 int irq_fc; 304 305 struct skcipher_request *req; 306 struct s5p_aes_ctx *ctx; 307 struct scatterlist *sg_src; 308 struct scatterlist *sg_dst; 309 310 struct scatterlist *sg_src_cpy; 311 struct scatterlist *sg_dst_cpy; 312 313 struct tasklet_struct tasklet; 314 struct crypto_queue queue; 315 bool busy; 316 spinlock_t lock; 317 318 struct resource *res; 319 void __iomem *io_hash_base; 320 321 spinlock_t hash_lock; /* protect hash_ vars */ 322 unsigned long hash_flags; 323 struct crypto_queue hash_queue; 324 struct tasklet_struct hash_tasklet; 325 326 u8 xmit_buf[BUFLEN]; 327 struct ahash_request *hash_req; 328 struct scatterlist *hash_sg_iter; 329 unsigned int hash_sg_cnt; 330 331 bool use_hash; 332 }; 333 334 /** 335 * struct s5p_hash_reqctx - HASH request context 336 * @dd: Associated device 337 * @op_update: Current request operation (OP_UPDATE or OP_FINAL) 338 * @digcnt: Number of bytes processed by HW (without buffer[] ones) 339 * @digest: Digest message or IV for partial result 340 * @nregs: Number of HW registers for digest or IV read/write 341 * @engine: Bits for selecting type of HASH in SSS block 342 * @sg: sg for DMA transfer 343 * @sg_len: Length of sg for DMA transfer 344 * @sgl: sg for joining buffer and req->src scatterlist 345 * @skip: Skip offset in req->src for current op 346 * @total: Total number of bytes for current request 347 * @finup: Keep state for finup or final. 348 * @error: Keep track of error. 349 * @bufcnt: Number of bytes holded in buffer[] 350 * @buffer: For byte(s) from end of req->src in UPDATE op 351 */ 352 struct s5p_hash_reqctx { 353 struct s5p_aes_dev *dd; 354 bool op_update; 355 356 u64 digcnt; 357 u8 digest[SHA256_DIGEST_SIZE]; 358 359 unsigned int nregs; /* digest_size / sizeof(reg) */ 360 u32 engine; 361 362 struct scatterlist *sg; 363 unsigned int sg_len; 364 struct scatterlist sgl[2]; 365 unsigned int skip; 366 unsigned int total; 367 bool finup; 368 bool error; 369 370 u32 bufcnt; 371 u8 buffer[]; 372 }; 373 374 /** 375 * struct s5p_hash_ctx - HASH transformation context 376 * @dd: Associated device 377 * @flags: Bits for algorithm HASH. 378 * @fallback: Software transformation for zero message or size < BUFLEN. 379 */ 380 struct s5p_hash_ctx { 381 struct s5p_aes_dev *dd; 382 unsigned long flags; 383 struct crypto_shash *fallback; 384 }; 385 386 static const struct samsung_aes_variant s5p_aes_data = { 387 .aes_offset = 0x4000, 388 .hash_offset = 0x6000, 389 .clk_names = { "secss", }, 390 }; 391 392 static const struct samsung_aes_variant exynos_aes_data = { 393 .aes_offset = 0x200, 394 .hash_offset = 0x400, 395 .clk_names = { "secss", }, 396 }; 397 398 static const struct samsung_aes_variant exynos5433_slim_aes_data = { 399 .aes_offset = 0x400, 400 .hash_offset = 0x800, 401 .clk_names = { "aclk", "pclk", }, 402 }; 403 404 static const struct of_device_id s5p_sss_dt_match[] = { 405 { 406 .compatible = "samsung,s5pv210-secss", 407 .data = &s5p_aes_data, 408 }, 409 { 410 .compatible = "samsung,exynos4210-secss", 411 .data = &exynos_aes_data, 412 }, 413 { 414 .compatible = "samsung,exynos5433-slim-sss", 415 .data = &exynos5433_slim_aes_data, 416 }, 417 { }, 418 }; 419 MODULE_DEVICE_TABLE(of, s5p_sss_dt_match); 420 421 static inline const struct samsung_aes_variant *find_s5p_sss_version 422 (const struct platform_device *pdev) 423 { 424 if (IS_ENABLED(CONFIG_OF) && (pdev->dev.of_node)) 425 return of_device_get_match_data(&pdev->dev); 426 427 return (const struct samsung_aes_variant *) 428 platform_get_device_id(pdev)->driver_data; 429 } 430 431 static struct s5p_aes_dev *s5p_dev; 432 433 static void s5p_set_dma_indata(struct s5p_aes_dev *dev, 434 const struct scatterlist *sg) 435 { 436 SSS_WRITE(dev, FCBRDMAS, sg_dma_address(sg)); 437 SSS_WRITE(dev, FCBRDMAL, sg_dma_len(sg)); 438 } 439 440 static void s5p_set_dma_outdata(struct s5p_aes_dev *dev, 441 const struct scatterlist *sg) 442 { 443 SSS_WRITE(dev, FCBTDMAS, sg_dma_address(sg)); 444 SSS_WRITE(dev, FCBTDMAL, sg_dma_len(sg)); 445 } 446 447 static void s5p_free_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist **sg) 448 { 449 int len; 450 451 if (!*sg) 452 return; 453 454 len = ALIGN(dev->req->cryptlen, AES_BLOCK_SIZE); 455 free_pages((unsigned long)sg_virt(*sg), get_order(len)); 456 457 kfree(*sg); 458 *sg = NULL; 459 } 460 461 static void s5p_sg_done(struct s5p_aes_dev *dev) 462 { 463 struct skcipher_request *req = dev->req; 464 struct s5p_aes_reqctx *reqctx = skcipher_request_ctx(req); 465 466 if (dev->sg_dst_cpy) { 467 dev_dbg(dev->dev, 468 "Copying %d bytes of output data back to original place\n", 469 dev->req->cryptlen); 470 memcpy_to_sglist(dev->req->dst, 0, sg_virt(dev->sg_dst_cpy), 471 dev->req->cryptlen); 472 } 473 s5p_free_sg_cpy(dev, &dev->sg_src_cpy); 474 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy); 475 if (reqctx->mode & FLAGS_AES_CBC) 476 memcpy_fromio(req->iv, dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), AES_BLOCK_SIZE); 477 478 else if (reqctx->mode & FLAGS_AES_CTR) 479 memcpy_fromio(req->iv, dev->aes_ioaddr + SSS_REG_AES_CNT_DATA(0), AES_BLOCK_SIZE); 480 } 481 482 /* Calls the completion. Cannot be called with dev->lock hold. */ 483 static void s5p_aes_complete(struct skcipher_request *req, int err) 484 { 485 skcipher_request_complete(req, err); 486 } 487 488 static void s5p_unset_outdata(struct s5p_aes_dev *dev) 489 { 490 dma_unmap_sg(dev->dev, dev->sg_dst, 1, DMA_FROM_DEVICE); 491 } 492 493 static void s5p_unset_indata(struct s5p_aes_dev *dev) 494 { 495 dma_unmap_sg(dev->dev, dev->sg_src, 1, DMA_TO_DEVICE); 496 } 497 498 static int s5p_make_sg_cpy(struct s5p_aes_dev *dev, struct scatterlist *src, 499 struct scatterlist **dst) 500 { 501 void *pages; 502 int len; 503 504 *dst = kmalloc(sizeof(**dst), GFP_ATOMIC); 505 if (!*dst) 506 return -ENOMEM; 507 508 len = ALIGN(dev->req->cryptlen, AES_BLOCK_SIZE); 509 pages = (void *)__get_free_pages(GFP_ATOMIC, get_order(len)); 510 if (!pages) { 511 kfree(*dst); 512 *dst = NULL; 513 return -ENOMEM; 514 } 515 516 memcpy_from_sglist(pages, src, 0, dev->req->cryptlen); 517 518 sg_init_table(*dst, 1); 519 sg_set_buf(*dst, pages, len); 520 521 return 0; 522 } 523 524 static int s5p_set_outdata(struct s5p_aes_dev *dev, struct scatterlist *sg) 525 { 526 if (!sg->length) 527 return -EINVAL; 528 529 if (!dma_map_sg(dev->dev, sg, 1, DMA_FROM_DEVICE)) 530 return -ENOMEM; 531 532 dev->sg_dst = sg; 533 534 return 0; 535 } 536 537 static int s5p_set_indata(struct s5p_aes_dev *dev, struct scatterlist *sg) 538 { 539 if (!sg->length) 540 return -EINVAL; 541 542 if (!dma_map_sg(dev->dev, sg, 1, DMA_TO_DEVICE)) 543 return -ENOMEM; 544 545 dev->sg_src = sg; 546 547 return 0; 548 } 549 550 /* 551 * Returns -ERRNO on error (mapping of new data failed). 552 * On success returns: 553 * - 0 if there is no more data, 554 * - 1 if new transmitting (output) data is ready and its address+length 555 * have to be written to device (by calling s5p_set_dma_outdata()). 556 */ 557 static int s5p_aes_tx(struct s5p_aes_dev *dev) 558 { 559 int ret = 0; 560 561 s5p_unset_outdata(dev); 562 563 if (!sg_is_last(dev->sg_dst)) { 564 ret = s5p_set_outdata(dev, sg_next(dev->sg_dst)); 565 if (!ret) 566 ret = 1; 567 } 568 569 return ret; 570 } 571 572 /* 573 * Returns -ERRNO on error (mapping of new data failed). 574 * On success returns: 575 * - 0 if there is no more data, 576 * - 1 if new receiving (input) data is ready and its address+length 577 * have to be written to device (by calling s5p_set_dma_indata()). 578 */ 579 static int s5p_aes_rx(struct s5p_aes_dev *dev/*, bool *set_dma*/) 580 { 581 int ret = 0; 582 583 s5p_unset_indata(dev); 584 585 if (!sg_is_last(dev->sg_src)) { 586 ret = s5p_set_indata(dev, sg_next(dev->sg_src)); 587 if (!ret) 588 ret = 1; 589 } 590 591 return ret; 592 } 593 594 static inline u32 s5p_hash_read(struct s5p_aes_dev *dd, u32 offset) 595 { 596 return __raw_readl(dd->io_hash_base + offset); 597 } 598 599 static inline void s5p_hash_write(struct s5p_aes_dev *dd, 600 u32 offset, u32 value) 601 { 602 __raw_writel(value, dd->io_hash_base + offset); 603 } 604 605 /** 606 * s5p_set_dma_hashdata() - start DMA with sg 607 * @dev: device 608 * @sg: scatterlist ready to DMA transmit 609 */ 610 static void s5p_set_dma_hashdata(struct s5p_aes_dev *dev, 611 const struct scatterlist *sg) 612 { 613 dev->hash_sg_cnt--; 614 SSS_WRITE(dev, FCHRDMAS, sg_dma_address(sg)); 615 SSS_WRITE(dev, FCHRDMAL, sg_dma_len(sg)); /* DMA starts */ 616 } 617 618 /** 619 * s5p_hash_rx() - get next hash_sg_iter 620 * @dev: device 621 * 622 * Return: 623 * 2 if there is no more data and it is UPDATE op 624 * 1 if new receiving (input) data is ready and can be written to device 625 * 0 if there is no more data and it is FINAL op 626 */ 627 static int s5p_hash_rx(struct s5p_aes_dev *dev) 628 { 629 if (dev->hash_sg_cnt > 0) { 630 dev->hash_sg_iter = sg_next(dev->hash_sg_iter); 631 return 1; 632 } 633 634 set_bit(HASH_FLAGS_DMA_READY, &dev->hash_flags); 635 if (test_bit(HASH_FLAGS_FINAL, &dev->hash_flags)) 636 return 0; 637 638 return 2; 639 } 640 641 static irqreturn_t s5p_aes_interrupt(int irq, void *dev_id) 642 { 643 struct platform_device *pdev = dev_id; 644 struct s5p_aes_dev *dev = platform_get_drvdata(pdev); 645 struct skcipher_request *req; 646 int err_dma_tx = 0; 647 int err_dma_rx = 0; 648 int err_dma_hx = 0; 649 bool tx_end = false; 650 bool hx_end = false; 651 unsigned long flags; 652 u32 status, st_bits; 653 int err; 654 655 spin_lock_irqsave(&dev->lock, flags); 656 657 /* 658 * Handle rx or tx interrupt. If there is still data (scatterlist did not 659 * reach end), then map next scatterlist entry. 660 * In case of such mapping error, s5p_aes_complete() should be called. 661 * 662 * If there is no more data in tx scatter list, call s5p_aes_complete() 663 * and schedule new tasklet. 664 * 665 * Handle hx interrupt. If there is still data map next entry. 666 */ 667 status = SSS_READ(dev, FCINTSTAT); 668 if (status & SSS_FCINTSTAT_BRDMAINT) 669 err_dma_rx = s5p_aes_rx(dev); 670 671 if (status & SSS_FCINTSTAT_BTDMAINT) { 672 if (sg_is_last(dev->sg_dst)) 673 tx_end = true; 674 err_dma_tx = s5p_aes_tx(dev); 675 } 676 677 if (status & SSS_FCINTSTAT_HRDMAINT) 678 err_dma_hx = s5p_hash_rx(dev); 679 680 st_bits = status & (SSS_FCINTSTAT_BRDMAINT | SSS_FCINTSTAT_BTDMAINT | 681 SSS_FCINTSTAT_HRDMAINT); 682 /* clear DMA bits */ 683 SSS_WRITE(dev, FCINTPEND, st_bits); 684 685 /* clear HASH irq bits */ 686 if (status & (SSS_FCINTSTAT_HDONEINT | SSS_FCINTSTAT_HPARTINT)) { 687 /* cannot have both HPART and HDONE */ 688 if (status & SSS_FCINTSTAT_HPARTINT) 689 st_bits = SSS_HASH_STATUS_PARTIAL_DONE; 690 691 if (status & SSS_FCINTSTAT_HDONEINT) 692 st_bits = SSS_HASH_STATUS_MSG_DONE; 693 694 set_bit(HASH_FLAGS_OUTPUT_READY, &dev->hash_flags); 695 s5p_hash_write(dev, SSS_REG_HASH_STATUS, st_bits); 696 hx_end = true; 697 /* when DONE or PART, do not handle HASH DMA */ 698 err_dma_hx = 0; 699 } 700 701 if (err_dma_rx < 0) { 702 err = err_dma_rx; 703 goto error; 704 } 705 if (err_dma_tx < 0) { 706 err = err_dma_tx; 707 goto error; 708 } 709 710 if (tx_end) { 711 s5p_sg_done(dev); 712 if (err_dma_hx == 1) 713 s5p_set_dma_hashdata(dev, dev->hash_sg_iter); 714 715 spin_unlock_irqrestore(&dev->lock, flags); 716 717 s5p_aes_complete(dev->req, 0); 718 /* Device is still busy */ 719 tasklet_schedule(&dev->tasklet); 720 } else { 721 /* 722 * Writing length of DMA block (either receiving or 723 * transmitting) will start the operation immediately, so this 724 * should be done at the end (even after clearing pending 725 * interrupts to not miss the interrupt). 726 */ 727 if (err_dma_tx == 1) 728 s5p_set_dma_outdata(dev, dev->sg_dst); 729 if (err_dma_rx == 1) 730 s5p_set_dma_indata(dev, dev->sg_src); 731 if (err_dma_hx == 1) 732 s5p_set_dma_hashdata(dev, dev->hash_sg_iter); 733 734 spin_unlock_irqrestore(&dev->lock, flags); 735 } 736 737 goto hash_irq_end; 738 739 error: 740 s5p_sg_done(dev); 741 dev->busy = false; 742 req = dev->req; 743 if (err_dma_hx == 1) 744 s5p_set_dma_hashdata(dev, dev->hash_sg_iter); 745 746 spin_unlock_irqrestore(&dev->lock, flags); 747 s5p_aes_complete(req, err); 748 749 hash_irq_end: 750 /* 751 * Note about else if: 752 * when hash_sg_iter reaches end and its UPDATE op, 753 * issue SSS_HASH_PAUSE and wait for HPART irq 754 */ 755 if (hx_end) 756 tasklet_schedule(&dev->hash_tasklet); 757 else if (err_dma_hx == 2) 758 s5p_hash_write(dev, SSS_REG_HASH_CTRL_PAUSE, 759 SSS_HASH_PAUSE); 760 761 return IRQ_HANDLED; 762 } 763 764 /** 765 * s5p_hash_read_msg() - read message or IV from HW 766 * @req: AHASH request 767 */ 768 static void s5p_hash_read_msg(struct ahash_request *req) 769 { 770 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 771 struct s5p_aes_dev *dd = ctx->dd; 772 u32 *hash = (u32 *)ctx->digest; 773 unsigned int i; 774 775 for (i = 0; i < ctx->nregs; i++) 776 hash[i] = s5p_hash_read(dd, SSS_REG_HASH_OUT(i)); 777 } 778 779 /** 780 * s5p_hash_write_ctx_iv() - write IV for next partial/finup op. 781 * @dd: device 782 * @ctx: request context 783 */ 784 static void s5p_hash_write_ctx_iv(struct s5p_aes_dev *dd, 785 const struct s5p_hash_reqctx *ctx) 786 { 787 const u32 *hash = (const u32 *)ctx->digest; 788 unsigned int i; 789 790 for (i = 0; i < ctx->nregs; i++) 791 s5p_hash_write(dd, SSS_REG_HASH_IV(i), hash[i]); 792 } 793 794 /** 795 * s5p_hash_write_iv() - write IV for next partial/finup op. 796 * @req: AHASH request 797 */ 798 static void s5p_hash_write_iv(struct ahash_request *req) 799 { 800 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 801 802 s5p_hash_write_ctx_iv(ctx->dd, ctx); 803 } 804 805 /** 806 * s5p_hash_copy_result() - copy digest into req->result 807 * @req: AHASH request 808 */ 809 static void s5p_hash_copy_result(struct ahash_request *req) 810 { 811 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 812 813 if (!req->result) 814 return; 815 816 memcpy(req->result, ctx->digest, ctx->nregs * HASH_REG_SIZEOF); 817 } 818 819 /** 820 * s5p_hash_dma_flush() - flush HASH DMA 821 * @dev: secss device 822 */ 823 static void s5p_hash_dma_flush(struct s5p_aes_dev *dev) 824 { 825 SSS_WRITE(dev, FCHRDMAC, SSS_FCHRDMAC_FLUSH); 826 } 827 828 /** 829 * s5p_hash_dma_enable() - enable DMA mode for HASH 830 * @dev: secss device 831 * 832 * enable DMA mode for HASH 833 */ 834 static void s5p_hash_dma_enable(struct s5p_aes_dev *dev) 835 { 836 s5p_hash_write(dev, SSS_REG_HASH_CTRL_FIFO, SSS_HASH_FIFO_MODE_DMA); 837 } 838 839 /** 840 * s5p_hash_irq_disable() - disable irq HASH signals 841 * @dev: secss device 842 * @flags: bitfield with irq's to be disabled 843 */ 844 static void s5p_hash_irq_disable(struct s5p_aes_dev *dev, u32 flags) 845 { 846 SSS_WRITE(dev, FCINTENCLR, flags); 847 } 848 849 /** 850 * s5p_hash_irq_enable() - enable irq signals 851 * @dev: secss device 852 * @flags: bitfield with irq's to be enabled 853 */ 854 static void s5p_hash_irq_enable(struct s5p_aes_dev *dev, int flags) 855 { 856 SSS_WRITE(dev, FCINTENSET, flags); 857 } 858 859 /** 860 * s5p_hash_set_flow() - set flow inside SecSS AES/DES with/without HASH 861 * @dev: secss device 862 * @hashflow: HASH stream flow with/without crypto AES/DES 863 */ 864 static void s5p_hash_set_flow(struct s5p_aes_dev *dev, u32 hashflow) 865 { 866 unsigned long flags; 867 u32 flow; 868 869 spin_lock_irqsave(&dev->lock, flags); 870 871 flow = SSS_READ(dev, FCFIFOCTRL); 872 flow &= ~SSS_HASHIN_MASK; 873 flow |= hashflow; 874 SSS_WRITE(dev, FCFIFOCTRL, flow); 875 876 spin_unlock_irqrestore(&dev->lock, flags); 877 } 878 879 /** 880 * s5p_ahash_dma_init() - enable DMA and set HASH flow inside SecSS 881 * @dev: secss device 882 * @hashflow: HASH stream flow with/without AES/DES 883 * 884 * flush HASH DMA and enable DMA, set HASH stream flow inside SecSS HW, 885 * enable HASH irq's HRDMA, HDONE, HPART 886 */ 887 static void s5p_ahash_dma_init(struct s5p_aes_dev *dev, u32 hashflow) 888 { 889 s5p_hash_irq_disable(dev, SSS_FCINTENCLR_HRDMAINTENCLR | 890 SSS_FCINTENCLR_HDONEINTENCLR | 891 SSS_FCINTENCLR_HPARTINTENCLR); 892 s5p_hash_dma_flush(dev); 893 894 s5p_hash_dma_enable(dev); 895 s5p_hash_set_flow(dev, hashflow & SSS_HASHIN_MASK); 896 s5p_hash_irq_enable(dev, SSS_FCINTENSET_HRDMAINTENSET | 897 SSS_FCINTENSET_HDONEINTENSET | 898 SSS_FCINTENSET_HPARTINTENSET); 899 } 900 901 /** 902 * s5p_hash_write_ctrl() - prepare HASH block in SecSS for processing 903 * @dd: secss device 904 * @length: length for request 905 * @final: true if final op 906 * 907 * Prepare SSS HASH block for processing bytes in DMA mode. If it is called 908 * after previous updates, fill up IV words. For final, calculate and set 909 * lengths for HASH so SecSS can finalize hash. For partial, set SSS HASH 910 * length as 2^63 so it will be never reached and set to zero prelow and 911 * prehigh. 912 * 913 * This function does not start DMA transfer. 914 */ 915 static void s5p_hash_write_ctrl(struct s5p_aes_dev *dd, size_t length, 916 bool final) 917 { 918 struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req); 919 u32 prelow, prehigh, low, high; 920 u32 configflags, swapflags; 921 u64 tmplen; 922 923 configflags = ctx->engine | SSS_HASH_INIT_BIT; 924 925 if (likely(ctx->digcnt)) { 926 s5p_hash_write_ctx_iv(dd, ctx); 927 configflags |= SSS_HASH_USER_IV_EN; 928 } 929 930 if (final) { 931 /* number of bytes for last part */ 932 low = length; 933 high = 0; 934 /* total number of bits prev hashed */ 935 tmplen = ctx->digcnt * 8; 936 prelow = (u32)tmplen; 937 prehigh = (u32)(tmplen >> 32); 938 } else { 939 prelow = 0; 940 prehigh = 0; 941 low = 0; 942 high = BIT(31); 943 } 944 945 swapflags = SSS_HASH_BYTESWAP_DI | SSS_HASH_BYTESWAP_DO | 946 SSS_HASH_BYTESWAP_IV | SSS_HASH_BYTESWAP_KEY; 947 948 s5p_hash_write(dd, SSS_REG_HASH_MSG_SIZE_LOW, low); 949 s5p_hash_write(dd, SSS_REG_HASH_MSG_SIZE_HIGH, high); 950 s5p_hash_write(dd, SSS_REG_HASH_PRE_MSG_SIZE_LOW, prelow); 951 s5p_hash_write(dd, SSS_REG_HASH_PRE_MSG_SIZE_HIGH, prehigh); 952 953 s5p_hash_write(dd, SSS_REG_HASH_CTRL_SWAP, swapflags); 954 s5p_hash_write(dd, SSS_REG_HASH_CTRL, configflags); 955 } 956 957 /** 958 * s5p_hash_xmit_dma() - start DMA hash processing 959 * @dd: secss device 960 * @length: length for request 961 * @final: true if final op 962 * 963 * Update digcnt here, as it is needed for finup/final op. 964 */ 965 static int s5p_hash_xmit_dma(struct s5p_aes_dev *dd, size_t length, 966 bool final) 967 { 968 struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req); 969 unsigned int cnt; 970 971 cnt = dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE); 972 if (!cnt) { 973 dev_err(dd->dev, "dma_map_sg error\n"); 974 ctx->error = true; 975 return -EINVAL; 976 } 977 978 set_bit(HASH_FLAGS_DMA_ACTIVE, &dd->hash_flags); 979 dd->hash_sg_iter = ctx->sg; 980 dd->hash_sg_cnt = cnt; 981 s5p_hash_write_ctrl(dd, length, final); 982 ctx->digcnt += length; 983 ctx->total -= length; 984 985 /* catch last interrupt */ 986 if (final) 987 set_bit(HASH_FLAGS_FINAL, &dd->hash_flags); 988 989 s5p_set_dma_hashdata(dd, dd->hash_sg_iter); /* DMA starts */ 990 991 return -EINPROGRESS; 992 } 993 994 /** 995 * s5p_hash_copy_sgs() - copy request's bytes into new buffer 996 * @ctx: request context 997 * @sg: source scatterlist request 998 * @new_len: number of bytes to process from sg 999 * 1000 * Allocate new buffer, copy data for HASH into it. If there was xmit_buf 1001 * filled, copy it first, then copy data from sg into it. Prepare one sgl[0] 1002 * with allocated buffer. 1003 * 1004 * Set bit in dd->hash_flag so we can free it after irq ends processing. 1005 */ 1006 static int s5p_hash_copy_sgs(struct s5p_hash_reqctx *ctx, 1007 struct scatterlist *sg, unsigned int new_len) 1008 { 1009 unsigned int pages, len; 1010 void *buf; 1011 1012 len = new_len + ctx->bufcnt; 1013 pages = get_order(len); 1014 1015 buf = (void *)__get_free_pages(GFP_ATOMIC, pages); 1016 if (!buf) { 1017 dev_err(ctx->dd->dev, "alloc pages for unaligned case.\n"); 1018 ctx->error = true; 1019 return -ENOMEM; 1020 } 1021 1022 if (ctx->bufcnt) 1023 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt); 1024 1025 memcpy_from_sglist(buf + ctx->bufcnt, sg, ctx->skip, new_len); 1026 sg_init_table(ctx->sgl, 1); 1027 sg_set_buf(ctx->sgl, buf, len); 1028 ctx->sg = ctx->sgl; 1029 ctx->sg_len = 1; 1030 ctx->bufcnt = 0; 1031 ctx->skip = 0; 1032 set_bit(HASH_FLAGS_SGS_COPIED, &ctx->dd->hash_flags); 1033 1034 return 0; 1035 } 1036 1037 /** 1038 * s5p_hash_copy_sg_lists() - copy sg list and make fixes in copy 1039 * @ctx: request context 1040 * @sg: source scatterlist request 1041 * @new_len: number of bytes to process from sg 1042 * 1043 * Allocate new scatterlist table, copy data for HASH into it. If there was 1044 * xmit_buf filled, prepare it first, then copy page, length and offset from 1045 * source sg into it, adjusting begin and/or end for skip offset and 1046 * hash_later value. 1047 * 1048 * Resulting sg table will be assigned to ctx->sg. Set flag so we can free 1049 * it after irq ends processing. 1050 */ 1051 static int s5p_hash_copy_sg_lists(struct s5p_hash_reqctx *ctx, 1052 struct scatterlist *sg, unsigned int new_len) 1053 { 1054 unsigned int skip = ctx->skip, n = sg_nents(sg); 1055 struct scatterlist *tmp; 1056 unsigned int len; 1057 1058 if (ctx->bufcnt) 1059 n++; 1060 1061 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL); 1062 if (!ctx->sg) { 1063 ctx->error = true; 1064 return -ENOMEM; 1065 } 1066 1067 sg_init_table(ctx->sg, n); 1068 1069 tmp = ctx->sg; 1070 1071 ctx->sg_len = 0; 1072 1073 if (ctx->bufcnt) { 1074 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt); 1075 tmp = sg_next(tmp); 1076 ctx->sg_len++; 1077 } 1078 1079 while (sg && skip >= sg->length) { 1080 skip -= sg->length; 1081 sg = sg_next(sg); 1082 } 1083 1084 while (sg && new_len) { 1085 len = sg->length - skip; 1086 if (new_len < len) 1087 len = new_len; 1088 1089 new_len -= len; 1090 sg_set_page(tmp, sg_page(sg), len, sg->offset + skip); 1091 skip = 0; 1092 if (new_len <= 0) 1093 sg_mark_end(tmp); 1094 1095 tmp = sg_next(tmp); 1096 ctx->sg_len++; 1097 sg = sg_next(sg); 1098 } 1099 1100 set_bit(HASH_FLAGS_SGS_ALLOCED, &ctx->dd->hash_flags); 1101 1102 return 0; 1103 } 1104 1105 /** 1106 * s5p_hash_prepare_sgs() - prepare sg for processing 1107 * @ctx: request context 1108 * @sg: source scatterlist request 1109 * @new_len: number of bytes to process from sg 1110 * @final: final flag 1111 * 1112 * Check two conditions: (1) if buffers in sg have len aligned data, and (2) 1113 * sg table have good aligned elements (list_ok). If one of this checks fails, 1114 * then either (1) allocates new buffer for data with s5p_hash_copy_sgs, copy 1115 * data into this buffer and prepare request in sgl, or (2) allocates new sg 1116 * table and prepare sg elements. 1117 * 1118 * For digest or finup all conditions can be good, and we may not need any 1119 * fixes. 1120 */ 1121 static int s5p_hash_prepare_sgs(struct s5p_hash_reqctx *ctx, 1122 struct scatterlist *sg, 1123 unsigned int new_len, bool final) 1124 { 1125 unsigned int skip = ctx->skip, nbytes = new_len, n = 0; 1126 bool aligned = true, list_ok = true; 1127 struct scatterlist *sg_tmp = sg; 1128 1129 if (!sg || !sg->length || !new_len) 1130 return 0; 1131 1132 if (skip || !final) 1133 list_ok = false; 1134 1135 while (nbytes > 0 && sg_tmp) { 1136 n++; 1137 if (skip >= sg_tmp->length) { 1138 skip -= sg_tmp->length; 1139 if (!sg_tmp->length) { 1140 aligned = false; 1141 break; 1142 } 1143 } else { 1144 if (!IS_ALIGNED(sg_tmp->length - skip, BUFLEN)) { 1145 aligned = false; 1146 break; 1147 } 1148 1149 if (nbytes < sg_tmp->length - skip) { 1150 list_ok = false; 1151 break; 1152 } 1153 1154 nbytes -= sg_tmp->length - skip; 1155 skip = 0; 1156 } 1157 1158 sg_tmp = sg_next(sg_tmp); 1159 } 1160 1161 if (!aligned) 1162 return s5p_hash_copy_sgs(ctx, sg, new_len); 1163 else if (!list_ok) 1164 return s5p_hash_copy_sg_lists(ctx, sg, new_len); 1165 1166 /* 1167 * Have aligned data from previous operation and/or current 1168 * Note: will enter here only if (digest or finup) and aligned 1169 */ 1170 if (ctx->bufcnt) { 1171 ctx->sg_len = n; 1172 sg_init_table(ctx->sgl, 2); 1173 sg_set_buf(ctx->sgl, ctx->dd->xmit_buf, ctx->bufcnt); 1174 sg_chain(ctx->sgl, 2, sg); 1175 ctx->sg = ctx->sgl; 1176 ctx->sg_len++; 1177 } else { 1178 ctx->sg = sg; 1179 ctx->sg_len = n; 1180 } 1181 1182 return 0; 1183 } 1184 1185 /** 1186 * s5p_hash_prepare_request() - prepare request for processing 1187 * @req: AHASH request 1188 * @update: true if UPDATE op 1189 * 1190 * Note 1: we can have update flag _and_ final flag at the same time. 1191 * Note 2: we enter here when digcnt > BUFLEN (=HASH_BLOCK_SIZE) or 1192 * either req->nbytes or ctx->bufcnt + req->nbytes is > BUFLEN or 1193 * we have final op 1194 */ 1195 static int s5p_hash_prepare_request(struct ahash_request *req, bool update) 1196 { 1197 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1198 bool final = ctx->finup; 1199 int xmit_len, hash_later, nbytes; 1200 int ret; 1201 1202 if (update) 1203 nbytes = req->nbytes; 1204 else 1205 nbytes = 0; 1206 1207 ctx->total = nbytes + ctx->bufcnt; 1208 if (!ctx->total) 1209 return 0; 1210 1211 if (nbytes && (!IS_ALIGNED(ctx->bufcnt, BUFLEN))) { 1212 /* bytes left from previous request, so fill up to BUFLEN */ 1213 int len = BUFLEN - ctx->bufcnt % BUFLEN; 1214 1215 if (len > nbytes) 1216 len = nbytes; 1217 1218 memcpy_from_sglist(ctx->buffer + ctx->bufcnt, req->src, 0, len); 1219 ctx->bufcnt += len; 1220 nbytes -= len; 1221 ctx->skip = len; 1222 } else { 1223 ctx->skip = 0; 1224 } 1225 1226 if (ctx->bufcnt) 1227 memcpy(ctx->dd->xmit_buf, ctx->buffer, ctx->bufcnt); 1228 1229 xmit_len = ctx->total; 1230 if (final) { 1231 hash_later = 0; 1232 } else { 1233 if (IS_ALIGNED(xmit_len, BUFLEN)) 1234 xmit_len -= BUFLEN; 1235 else 1236 xmit_len -= xmit_len & (BUFLEN - 1); 1237 1238 hash_later = ctx->total - xmit_len; 1239 /* copy hash_later bytes from end of req->src */ 1240 /* previous bytes are in xmit_buf, so no overwrite */ 1241 memcpy_from_sglist(ctx->buffer, req->src, 1242 req->nbytes - hash_later, hash_later); 1243 } 1244 1245 if (xmit_len > BUFLEN) { 1246 ret = s5p_hash_prepare_sgs(ctx, req->src, nbytes - hash_later, 1247 final); 1248 if (ret) 1249 return ret; 1250 } else { 1251 /* have buffered data only */ 1252 if (unlikely(!ctx->bufcnt)) { 1253 /* first update didn't fill up buffer */ 1254 memcpy_from_sglist(ctx->dd->xmit_buf, req->src, 1255 0, xmit_len); 1256 } 1257 1258 sg_init_table(ctx->sgl, 1); 1259 sg_set_buf(ctx->sgl, ctx->dd->xmit_buf, xmit_len); 1260 1261 ctx->sg = ctx->sgl; 1262 ctx->sg_len = 1; 1263 } 1264 1265 ctx->bufcnt = hash_later; 1266 if (!final) 1267 ctx->total = xmit_len; 1268 1269 return 0; 1270 } 1271 1272 /** 1273 * s5p_hash_update_dma_stop() - unmap DMA 1274 * @dd: secss device 1275 * 1276 * Unmap scatterlist ctx->sg. 1277 */ 1278 static void s5p_hash_update_dma_stop(struct s5p_aes_dev *dd) 1279 { 1280 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req); 1281 1282 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE); 1283 clear_bit(HASH_FLAGS_DMA_ACTIVE, &dd->hash_flags); 1284 } 1285 1286 /** 1287 * s5p_hash_finish() - copy calculated digest to crypto layer 1288 * @req: AHASH request 1289 */ 1290 static void s5p_hash_finish(struct ahash_request *req) 1291 { 1292 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1293 struct s5p_aes_dev *dd = ctx->dd; 1294 1295 if (ctx->digcnt) 1296 s5p_hash_copy_result(req); 1297 1298 dev_dbg(dd->dev, "hash_finish digcnt: %lld\n", ctx->digcnt); 1299 } 1300 1301 /** 1302 * s5p_hash_finish_req() - finish request 1303 * @req: AHASH request 1304 * @err: error 1305 */ 1306 static void s5p_hash_finish_req(struct ahash_request *req, int err) 1307 { 1308 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1309 struct s5p_aes_dev *dd = ctx->dd; 1310 unsigned long flags; 1311 1312 if (test_bit(HASH_FLAGS_SGS_COPIED, &dd->hash_flags)) 1313 free_pages((unsigned long)sg_virt(ctx->sg), 1314 get_order(ctx->sg->length)); 1315 1316 if (test_bit(HASH_FLAGS_SGS_ALLOCED, &dd->hash_flags)) 1317 kfree(ctx->sg); 1318 1319 ctx->sg = NULL; 1320 dd->hash_flags &= ~(BIT(HASH_FLAGS_SGS_ALLOCED) | 1321 BIT(HASH_FLAGS_SGS_COPIED)); 1322 1323 if (!err && !ctx->error) { 1324 s5p_hash_read_msg(req); 1325 if (test_bit(HASH_FLAGS_FINAL, &dd->hash_flags)) 1326 s5p_hash_finish(req); 1327 } else { 1328 ctx->error = true; 1329 } 1330 1331 spin_lock_irqsave(&dd->hash_lock, flags); 1332 dd->hash_flags &= ~(BIT(HASH_FLAGS_BUSY) | BIT(HASH_FLAGS_FINAL) | 1333 BIT(HASH_FLAGS_DMA_READY) | 1334 BIT(HASH_FLAGS_OUTPUT_READY)); 1335 spin_unlock_irqrestore(&dd->hash_lock, flags); 1336 1337 if (req->base.complete) 1338 ahash_request_complete(req, err); 1339 } 1340 1341 /** 1342 * s5p_hash_handle_queue() - handle hash queue 1343 * @dd: device s5p_aes_dev 1344 * @req: AHASH request 1345 * 1346 * If req!=NULL enqueue it on dd->queue, if FLAGS_BUSY is not set on the 1347 * device then processes the first request from the dd->queue 1348 * 1349 * Returns: see s5p_hash_final below. 1350 */ 1351 static int s5p_hash_handle_queue(struct s5p_aes_dev *dd, 1352 struct ahash_request *req) 1353 { 1354 struct crypto_async_request *async_req, *backlog; 1355 struct s5p_hash_reqctx *ctx; 1356 unsigned long flags; 1357 int err = 0, ret = 0; 1358 1359 retry: 1360 spin_lock_irqsave(&dd->hash_lock, flags); 1361 if (req) 1362 ret = ahash_enqueue_request(&dd->hash_queue, req); 1363 1364 if (test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) { 1365 spin_unlock_irqrestore(&dd->hash_lock, flags); 1366 return ret; 1367 } 1368 1369 backlog = crypto_get_backlog(&dd->hash_queue); 1370 async_req = crypto_dequeue_request(&dd->hash_queue); 1371 if (async_req) 1372 set_bit(HASH_FLAGS_BUSY, &dd->hash_flags); 1373 1374 spin_unlock_irqrestore(&dd->hash_lock, flags); 1375 1376 if (!async_req) 1377 return ret; 1378 1379 if (backlog) 1380 crypto_request_complete(backlog, -EINPROGRESS); 1381 1382 req = ahash_request_cast(async_req); 1383 dd->hash_req = req; 1384 ctx = ahash_request_ctx(req); 1385 1386 err = s5p_hash_prepare_request(req, ctx->op_update); 1387 if (err || !ctx->total) 1388 goto out; 1389 1390 dev_dbg(dd->dev, "handling new req, op_update: %u, nbytes: %d\n", 1391 ctx->op_update, req->nbytes); 1392 1393 s5p_ahash_dma_init(dd, SSS_HASHIN_INDEPENDENT); 1394 if (ctx->digcnt) 1395 s5p_hash_write_iv(req); /* restore hash IV */ 1396 1397 if (ctx->op_update) { /* HASH_OP_UPDATE */ 1398 err = s5p_hash_xmit_dma(dd, ctx->total, ctx->finup); 1399 if (err != -EINPROGRESS && ctx->finup && !ctx->error) 1400 /* no final() after finup() */ 1401 err = s5p_hash_xmit_dma(dd, ctx->total, true); 1402 } else { /* HASH_OP_FINAL */ 1403 err = s5p_hash_xmit_dma(dd, ctx->total, true); 1404 } 1405 out: 1406 if (err != -EINPROGRESS) { 1407 /* hash_tasklet_cb will not finish it, so do it here */ 1408 s5p_hash_finish_req(req, err); 1409 req = NULL; 1410 1411 /* 1412 * Execute next request immediately if there is anything 1413 * in queue. 1414 */ 1415 goto retry; 1416 } 1417 1418 return ret; 1419 } 1420 1421 /** 1422 * s5p_hash_tasklet_cb() - hash tasklet 1423 * @data: ptr to s5p_aes_dev 1424 */ 1425 static void s5p_hash_tasklet_cb(unsigned long data) 1426 { 1427 struct s5p_aes_dev *dd = (struct s5p_aes_dev *)data; 1428 1429 if (!test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) { 1430 s5p_hash_handle_queue(dd, NULL); 1431 return; 1432 } 1433 1434 if (test_bit(HASH_FLAGS_DMA_READY, &dd->hash_flags)) { 1435 if (test_and_clear_bit(HASH_FLAGS_DMA_ACTIVE, 1436 &dd->hash_flags)) { 1437 s5p_hash_update_dma_stop(dd); 1438 } 1439 1440 if (test_and_clear_bit(HASH_FLAGS_OUTPUT_READY, 1441 &dd->hash_flags)) { 1442 /* hash or semi-hash ready */ 1443 clear_bit(HASH_FLAGS_DMA_READY, &dd->hash_flags); 1444 goto finish; 1445 } 1446 } 1447 1448 return; 1449 1450 finish: 1451 /* finish curent request */ 1452 s5p_hash_finish_req(dd->hash_req, 0); 1453 1454 /* If we are not busy, process next req */ 1455 if (!test_bit(HASH_FLAGS_BUSY, &dd->hash_flags)) 1456 s5p_hash_handle_queue(dd, NULL); 1457 } 1458 1459 /** 1460 * s5p_hash_enqueue() - enqueue request 1461 * @req: AHASH request 1462 * @op: operation UPDATE (true) or FINAL (false) 1463 * 1464 * Returns: see s5p_hash_final below. 1465 */ 1466 static int s5p_hash_enqueue(struct ahash_request *req, bool op) 1467 { 1468 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1469 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1470 1471 ctx->op_update = op; 1472 1473 return s5p_hash_handle_queue(tctx->dd, req); 1474 } 1475 1476 /** 1477 * s5p_hash_update() - process the hash input data 1478 * @req: AHASH request 1479 * 1480 * If request will fit in buffer, copy it and return immediately 1481 * else enqueue it with OP_UPDATE. 1482 * 1483 * Returns: see s5p_hash_final below. 1484 */ 1485 static int s5p_hash_update(struct ahash_request *req) 1486 { 1487 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1488 1489 if (!req->nbytes) 1490 return 0; 1491 1492 if (ctx->bufcnt + req->nbytes <= BUFLEN) { 1493 memcpy_from_sglist(ctx->buffer + ctx->bufcnt, req->src, 1494 0, req->nbytes); 1495 ctx->bufcnt += req->nbytes; 1496 return 0; 1497 } 1498 1499 return s5p_hash_enqueue(req, true); /* HASH_OP_UPDATE */ 1500 } 1501 1502 /** 1503 * s5p_hash_final() - close up hash and calculate digest 1504 * @req: AHASH request 1505 * 1506 * Note: in final req->src do not have any data, and req->nbytes can be 1507 * non-zero. 1508 * 1509 * If there were no input data processed yet and the buffered hash data is 1510 * less than BUFLEN (64) then calculate the final hash immediately by using 1511 * SW algorithm fallback. 1512 * 1513 * Otherwise enqueues the current AHASH request with OP_FINAL operation op 1514 * and finalize hash message in HW. Note that if digcnt!=0 then there were 1515 * previous update op, so there are always some buffered bytes in ctx->buffer, 1516 * which means that ctx->bufcnt!=0 1517 * 1518 * Returns: 1519 * 0 if the request has been processed immediately, 1520 * -EINPROGRESS if the operation has been queued for later execution or is set 1521 * to processing by HW, 1522 * -EBUSY if queue is full and request should be resubmitted later, 1523 * other negative values denotes an error. 1524 */ 1525 static int s5p_hash_final(struct ahash_request *req) 1526 { 1527 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1528 1529 ctx->finup = true; 1530 if (ctx->error) 1531 return -EINVAL; /* uncompleted hash is not needed */ 1532 1533 if (!ctx->digcnt && ctx->bufcnt < BUFLEN) { 1534 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm); 1535 1536 return crypto_shash_tfm_digest(tctx->fallback, ctx->buffer, 1537 ctx->bufcnt, req->result); 1538 } 1539 1540 return s5p_hash_enqueue(req, false); /* HASH_OP_FINAL */ 1541 } 1542 1543 /** 1544 * s5p_hash_finup() - process last req->src and calculate digest 1545 * @req: AHASH request containing the last update data 1546 * 1547 * Return values: see s5p_hash_final above. 1548 */ 1549 static int s5p_hash_finup(struct ahash_request *req) 1550 { 1551 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1552 int err1, err2; 1553 1554 ctx->finup = true; 1555 1556 err1 = s5p_hash_update(req); 1557 if (err1 == -EINPROGRESS || err1 == -EBUSY) 1558 return err1; 1559 1560 /* 1561 * final() has to be always called to cleanup resources even if 1562 * update() failed, except EINPROGRESS or calculate digest for small 1563 * size 1564 */ 1565 err2 = s5p_hash_final(req); 1566 1567 return err1 ?: err2; 1568 } 1569 1570 /** 1571 * s5p_hash_init() - initialize AHASH request contex 1572 * @req: AHASH request 1573 * 1574 * Init async hash request context. 1575 */ 1576 static int s5p_hash_init(struct ahash_request *req) 1577 { 1578 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1579 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 1580 struct s5p_hash_ctx *tctx = crypto_ahash_ctx(tfm); 1581 1582 ctx->dd = tctx->dd; 1583 ctx->error = false; 1584 ctx->finup = false; 1585 ctx->bufcnt = 0; 1586 ctx->digcnt = 0; 1587 ctx->total = 0; 1588 ctx->skip = 0; 1589 1590 dev_dbg(tctx->dd->dev, "init: digest size: %d\n", 1591 crypto_ahash_digestsize(tfm)); 1592 1593 switch (crypto_ahash_digestsize(tfm)) { 1594 case MD5_DIGEST_SIZE: 1595 ctx->engine = SSS_HASH_ENGINE_MD5; 1596 ctx->nregs = HASH_MD5_MAX_REG; 1597 break; 1598 case SHA1_DIGEST_SIZE: 1599 ctx->engine = SSS_HASH_ENGINE_SHA1; 1600 ctx->nregs = HASH_SHA1_MAX_REG; 1601 break; 1602 case SHA256_DIGEST_SIZE: 1603 ctx->engine = SSS_HASH_ENGINE_SHA256; 1604 ctx->nregs = HASH_SHA256_MAX_REG; 1605 break; 1606 default: 1607 ctx->error = true; 1608 return -EINVAL; 1609 } 1610 1611 return 0; 1612 } 1613 1614 /** 1615 * s5p_hash_digest - calculate digest from req->src 1616 * @req: AHASH request 1617 * 1618 * Return values: see s5p_hash_final above. 1619 */ 1620 static int s5p_hash_digest(struct ahash_request *req) 1621 { 1622 return s5p_hash_init(req) ?: s5p_hash_finup(req); 1623 } 1624 1625 /** 1626 * s5p_hash_cra_init_alg - init crypto alg transformation 1627 * @tfm: crypto transformation 1628 */ 1629 static int s5p_hash_cra_init_alg(struct crypto_tfm *tfm) 1630 { 1631 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(tfm); 1632 const char *alg_name = crypto_tfm_alg_name(tfm); 1633 1634 tctx->dd = s5p_dev; 1635 /* Allocate a fallback and abort if it failed. */ 1636 tctx->fallback = crypto_alloc_shash(alg_name, 0, 1637 CRYPTO_ALG_NEED_FALLBACK); 1638 if (IS_ERR(tctx->fallback)) { 1639 pr_err("fallback alloc fails for '%s'\n", alg_name); 1640 return PTR_ERR(tctx->fallback); 1641 } 1642 1643 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), 1644 sizeof(struct s5p_hash_reqctx) + BUFLEN); 1645 1646 return 0; 1647 } 1648 1649 /** 1650 * s5p_hash_cra_init - init crypto tfm 1651 * @tfm: crypto transformation 1652 */ 1653 static int s5p_hash_cra_init(struct crypto_tfm *tfm) 1654 { 1655 return s5p_hash_cra_init_alg(tfm); 1656 } 1657 1658 /** 1659 * s5p_hash_cra_exit - exit crypto tfm 1660 * @tfm: crypto transformation 1661 * 1662 * free allocated fallback 1663 */ 1664 static void s5p_hash_cra_exit(struct crypto_tfm *tfm) 1665 { 1666 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(tfm); 1667 1668 crypto_free_shash(tctx->fallback); 1669 tctx->fallback = NULL; 1670 } 1671 1672 /** 1673 * s5p_hash_export - export hash state 1674 * @req: AHASH request 1675 * @out: buffer for exported state 1676 */ 1677 static int s5p_hash_export(struct ahash_request *req, void *out) 1678 { 1679 const struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1680 1681 memcpy(out, ctx, sizeof(*ctx) + ctx->bufcnt); 1682 1683 return 0; 1684 } 1685 1686 /** 1687 * s5p_hash_import - import hash state 1688 * @req: AHASH request 1689 * @in: buffer with state to be imported from 1690 */ 1691 static int s5p_hash_import(struct ahash_request *req, const void *in) 1692 { 1693 struct s5p_hash_reqctx *ctx = ahash_request_ctx(req); 1694 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); 1695 struct s5p_hash_ctx *tctx = crypto_ahash_ctx(tfm); 1696 const struct s5p_hash_reqctx *ctx_in = in; 1697 1698 memcpy(ctx, in, sizeof(*ctx) + BUFLEN); 1699 if (ctx_in->bufcnt > BUFLEN) { 1700 ctx->error = true; 1701 return -EINVAL; 1702 } 1703 1704 ctx->dd = tctx->dd; 1705 ctx->error = false; 1706 1707 return 0; 1708 } 1709 1710 static struct ahash_alg algs_sha1_md5_sha256[] = { 1711 { 1712 .init = s5p_hash_init, 1713 .update = s5p_hash_update, 1714 .final = s5p_hash_final, 1715 .finup = s5p_hash_finup, 1716 .digest = s5p_hash_digest, 1717 .export = s5p_hash_export, 1718 .import = s5p_hash_import, 1719 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN, 1720 .halg.digestsize = SHA1_DIGEST_SIZE, 1721 .halg.base = { 1722 .cra_name = "sha1", 1723 .cra_driver_name = "exynos-sha1", 1724 .cra_priority = 100, 1725 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1726 CRYPTO_ALG_ASYNC | 1727 CRYPTO_ALG_NEED_FALLBACK, 1728 .cra_blocksize = HASH_BLOCK_SIZE, 1729 .cra_ctxsize = sizeof(struct s5p_hash_ctx), 1730 .cra_module = THIS_MODULE, 1731 .cra_init = s5p_hash_cra_init, 1732 .cra_exit = s5p_hash_cra_exit, 1733 } 1734 }, 1735 { 1736 .init = s5p_hash_init, 1737 .update = s5p_hash_update, 1738 .final = s5p_hash_final, 1739 .finup = s5p_hash_finup, 1740 .digest = s5p_hash_digest, 1741 .export = s5p_hash_export, 1742 .import = s5p_hash_import, 1743 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN, 1744 .halg.digestsize = MD5_DIGEST_SIZE, 1745 .halg.base = { 1746 .cra_name = "md5", 1747 .cra_driver_name = "exynos-md5", 1748 .cra_priority = 100, 1749 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1750 CRYPTO_ALG_ASYNC | 1751 CRYPTO_ALG_NEED_FALLBACK, 1752 .cra_blocksize = HASH_BLOCK_SIZE, 1753 .cra_ctxsize = sizeof(struct s5p_hash_ctx), 1754 .cra_module = THIS_MODULE, 1755 .cra_init = s5p_hash_cra_init, 1756 .cra_exit = s5p_hash_cra_exit, 1757 } 1758 }, 1759 { 1760 .init = s5p_hash_init, 1761 .update = s5p_hash_update, 1762 .final = s5p_hash_final, 1763 .finup = s5p_hash_finup, 1764 .digest = s5p_hash_digest, 1765 .export = s5p_hash_export, 1766 .import = s5p_hash_import, 1767 .halg.statesize = sizeof(struct s5p_hash_reqctx) + BUFLEN, 1768 .halg.digestsize = SHA256_DIGEST_SIZE, 1769 .halg.base = { 1770 .cra_name = "sha256", 1771 .cra_driver_name = "exynos-sha256", 1772 .cra_priority = 100, 1773 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | 1774 CRYPTO_ALG_ASYNC | 1775 CRYPTO_ALG_NEED_FALLBACK, 1776 .cra_blocksize = HASH_BLOCK_SIZE, 1777 .cra_ctxsize = sizeof(struct s5p_hash_ctx), 1778 .cra_module = THIS_MODULE, 1779 .cra_init = s5p_hash_cra_init, 1780 .cra_exit = s5p_hash_cra_exit, 1781 } 1782 } 1783 1784 }; 1785 1786 static void s5p_set_aes(struct s5p_aes_dev *dev, 1787 const u8 *key, const u8 *iv, const u8 *ctr, 1788 unsigned int keylen) 1789 { 1790 void __iomem *keystart; 1791 1792 if (iv) 1793 memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_IV_DATA(0), iv, 1794 AES_BLOCK_SIZE); 1795 1796 if (ctr) 1797 memcpy_toio(dev->aes_ioaddr + SSS_REG_AES_CNT_DATA(0), ctr, 1798 AES_BLOCK_SIZE); 1799 1800 if (keylen == AES_KEYSIZE_256) 1801 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(0); 1802 else if (keylen == AES_KEYSIZE_192) 1803 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(2); 1804 else 1805 keystart = dev->aes_ioaddr + SSS_REG_AES_KEY_DATA(4); 1806 1807 memcpy_toio(keystart, key, keylen); 1808 } 1809 1810 static bool s5p_is_sg_aligned(struct scatterlist *sg) 1811 { 1812 while (sg) { 1813 if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE)) 1814 return false; 1815 sg = sg_next(sg); 1816 } 1817 1818 return true; 1819 } 1820 1821 static int s5p_set_indata_start(struct s5p_aes_dev *dev, 1822 struct skcipher_request *req) 1823 { 1824 struct scatterlist *sg; 1825 int err; 1826 1827 dev->sg_src_cpy = NULL; 1828 sg = req->src; 1829 if (!s5p_is_sg_aligned(sg)) { 1830 dev_dbg(dev->dev, 1831 "At least one unaligned source scatter list, making a copy\n"); 1832 err = s5p_make_sg_cpy(dev, sg, &dev->sg_src_cpy); 1833 if (err) 1834 return err; 1835 1836 sg = dev->sg_src_cpy; 1837 } 1838 1839 err = s5p_set_indata(dev, sg); 1840 if (err) { 1841 s5p_free_sg_cpy(dev, &dev->sg_src_cpy); 1842 return err; 1843 } 1844 1845 return 0; 1846 } 1847 1848 static int s5p_set_outdata_start(struct s5p_aes_dev *dev, 1849 struct skcipher_request *req) 1850 { 1851 struct scatterlist *sg; 1852 int err; 1853 1854 dev->sg_dst_cpy = NULL; 1855 sg = req->dst; 1856 if (!s5p_is_sg_aligned(sg)) { 1857 dev_dbg(dev->dev, 1858 "At least one unaligned dest scatter list, making a copy\n"); 1859 err = s5p_make_sg_cpy(dev, sg, &dev->sg_dst_cpy); 1860 if (err) 1861 return err; 1862 1863 sg = dev->sg_dst_cpy; 1864 } 1865 1866 err = s5p_set_outdata(dev, sg); 1867 if (err) { 1868 s5p_free_sg_cpy(dev, &dev->sg_dst_cpy); 1869 return err; 1870 } 1871 1872 return 0; 1873 } 1874 1875 static void s5p_aes_crypt_start(struct s5p_aes_dev *dev, unsigned long mode) 1876 { 1877 struct skcipher_request *req = dev->req; 1878 u32 aes_control; 1879 unsigned long flags; 1880 int err; 1881 u8 *iv, *ctr; 1882 1883 /* This sets bit [13:12] to 00, which selects 128-bit counter */ 1884 aes_control = SSS_AES_KEY_CHANGE_MODE; 1885 if (mode & FLAGS_AES_DECRYPT) 1886 aes_control |= SSS_AES_MODE_DECRYPT; 1887 1888 if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CBC) { 1889 aes_control |= SSS_AES_CHAIN_MODE_CBC; 1890 iv = req->iv; 1891 ctr = NULL; 1892 } else if ((mode & FLAGS_AES_MODE_MASK) == FLAGS_AES_CTR) { 1893 aes_control |= SSS_AES_CHAIN_MODE_CTR; 1894 iv = NULL; 1895 ctr = req->iv; 1896 } else { 1897 iv = NULL; /* AES_ECB */ 1898 ctr = NULL; 1899 } 1900 1901 if (dev->ctx->keylen == AES_KEYSIZE_192) 1902 aes_control |= SSS_AES_KEY_SIZE_192; 1903 else if (dev->ctx->keylen == AES_KEYSIZE_256) 1904 aes_control |= SSS_AES_KEY_SIZE_256; 1905 1906 aes_control |= SSS_AES_FIFO_MODE; 1907 1908 /* as a variant it is possible to use byte swapping on DMA side */ 1909 aes_control |= SSS_AES_BYTESWAP_DI 1910 | SSS_AES_BYTESWAP_DO 1911 | SSS_AES_BYTESWAP_IV 1912 | SSS_AES_BYTESWAP_KEY 1913 | SSS_AES_BYTESWAP_CNT; 1914 1915 spin_lock_irqsave(&dev->lock, flags); 1916 1917 SSS_WRITE(dev, FCINTENCLR, 1918 SSS_FCINTENCLR_BTDMAINTENCLR | SSS_FCINTENCLR_BRDMAINTENCLR); 1919 SSS_WRITE(dev, FCFIFOCTRL, 0x00); 1920 1921 err = s5p_set_indata_start(dev, req); 1922 if (err) 1923 goto indata_error; 1924 1925 err = s5p_set_outdata_start(dev, req); 1926 if (err) 1927 goto outdata_error; 1928 1929 SSS_AES_WRITE(dev, AES_CONTROL, aes_control); 1930 s5p_set_aes(dev, dev->ctx->aes_key, iv, ctr, dev->ctx->keylen); 1931 1932 s5p_set_dma_indata(dev, dev->sg_src); 1933 s5p_set_dma_outdata(dev, dev->sg_dst); 1934 1935 SSS_WRITE(dev, FCINTENSET, 1936 SSS_FCINTENSET_BTDMAINTENSET | SSS_FCINTENSET_BRDMAINTENSET); 1937 1938 spin_unlock_irqrestore(&dev->lock, flags); 1939 1940 return; 1941 1942 outdata_error: 1943 s5p_unset_indata(dev); 1944 1945 indata_error: 1946 s5p_sg_done(dev); 1947 dev->busy = false; 1948 spin_unlock_irqrestore(&dev->lock, flags); 1949 s5p_aes_complete(req, err); 1950 } 1951 1952 static void s5p_tasklet_cb(unsigned long data) 1953 { 1954 struct s5p_aes_dev *dev = (struct s5p_aes_dev *)data; 1955 struct crypto_async_request *async_req, *backlog; 1956 struct s5p_aes_reqctx *reqctx; 1957 unsigned long flags; 1958 1959 spin_lock_irqsave(&dev->lock, flags); 1960 backlog = crypto_get_backlog(&dev->queue); 1961 async_req = crypto_dequeue_request(&dev->queue); 1962 1963 if (!async_req) { 1964 dev->busy = false; 1965 spin_unlock_irqrestore(&dev->lock, flags); 1966 return; 1967 } 1968 spin_unlock_irqrestore(&dev->lock, flags); 1969 1970 if (backlog) 1971 crypto_request_complete(backlog, -EINPROGRESS); 1972 1973 dev->req = skcipher_request_cast(async_req); 1974 dev->ctx = crypto_tfm_ctx(dev->req->base.tfm); 1975 reqctx = skcipher_request_ctx(dev->req); 1976 1977 s5p_aes_crypt_start(dev, reqctx->mode); 1978 } 1979 1980 static int s5p_aes_handle_req(struct s5p_aes_dev *dev, 1981 struct skcipher_request *req) 1982 { 1983 unsigned long flags; 1984 int err; 1985 1986 spin_lock_irqsave(&dev->lock, flags); 1987 err = crypto_enqueue_request(&dev->queue, &req->base); 1988 if (dev->busy) { 1989 spin_unlock_irqrestore(&dev->lock, flags); 1990 return err; 1991 } 1992 dev->busy = true; 1993 1994 spin_unlock_irqrestore(&dev->lock, flags); 1995 1996 tasklet_schedule(&dev->tasklet); 1997 1998 return err; 1999 } 2000 2001 static int s5p_aes_crypt(struct skcipher_request *req, unsigned long mode) 2002 { 2003 struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); 2004 struct s5p_aes_reqctx *reqctx = skcipher_request_ctx(req); 2005 struct s5p_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 2006 struct s5p_aes_dev *dev = ctx->dev; 2007 2008 if (!req->cryptlen) 2009 return 0; 2010 2011 if (!IS_ALIGNED(req->cryptlen, AES_BLOCK_SIZE) && 2012 ((mode & FLAGS_AES_MODE_MASK) != FLAGS_AES_CTR)) { 2013 dev_dbg(dev->dev, "request size is not exact amount of AES blocks\n"); 2014 return -EINVAL; 2015 } 2016 2017 reqctx->mode = mode; 2018 2019 return s5p_aes_handle_req(dev, req); 2020 } 2021 2022 static int s5p_aes_setkey(struct crypto_skcipher *cipher, 2023 const u8 *key, unsigned int keylen) 2024 { 2025 struct crypto_tfm *tfm = crypto_skcipher_tfm(cipher); 2026 struct s5p_aes_ctx *ctx = crypto_tfm_ctx(tfm); 2027 2028 if (keylen != AES_KEYSIZE_128 && 2029 keylen != AES_KEYSIZE_192 && 2030 keylen != AES_KEYSIZE_256) 2031 return -EINVAL; 2032 2033 memcpy(ctx->aes_key, key, keylen); 2034 ctx->keylen = keylen; 2035 2036 return 0; 2037 } 2038 2039 static int s5p_aes_ecb_encrypt(struct skcipher_request *req) 2040 { 2041 return s5p_aes_crypt(req, 0); 2042 } 2043 2044 static int s5p_aes_ecb_decrypt(struct skcipher_request *req) 2045 { 2046 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT); 2047 } 2048 2049 static int s5p_aes_cbc_encrypt(struct skcipher_request *req) 2050 { 2051 return s5p_aes_crypt(req, FLAGS_AES_CBC); 2052 } 2053 2054 static int s5p_aes_cbc_decrypt(struct skcipher_request *req) 2055 { 2056 return s5p_aes_crypt(req, FLAGS_AES_DECRYPT | FLAGS_AES_CBC); 2057 } 2058 2059 static int s5p_aes_ctr_crypt(struct skcipher_request *req) 2060 { 2061 return s5p_aes_crypt(req, FLAGS_AES_CTR); 2062 } 2063 2064 static int s5p_aes_init_tfm(struct crypto_skcipher *tfm) 2065 { 2066 struct s5p_aes_ctx *ctx = crypto_skcipher_ctx(tfm); 2067 2068 ctx->dev = s5p_dev; 2069 crypto_skcipher_set_reqsize(tfm, sizeof(struct s5p_aes_reqctx)); 2070 2071 return 0; 2072 } 2073 2074 static struct skcipher_alg algs[] = { 2075 { 2076 .base.cra_name = "ecb(aes)", 2077 .base.cra_driver_name = "ecb-aes-s5p", 2078 .base.cra_priority = 100, 2079 .base.cra_flags = CRYPTO_ALG_ASYNC | 2080 CRYPTO_ALG_KERN_DRIVER_ONLY, 2081 .base.cra_blocksize = AES_BLOCK_SIZE, 2082 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx), 2083 .base.cra_alignmask = 0x0f, 2084 .base.cra_module = THIS_MODULE, 2085 2086 .min_keysize = AES_MIN_KEY_SIZE, 2087 .max_keysize = AES_MAX_KEY_SIZE, 2088 .setkey = s5p_aes_setkey, 2089 .encrypt = s5p_aes_ecb_encrypt, 2090 .decrypt = s5p_aes_ecb_decrypt, 2091 .init = s5p_aes_init_tfm, 2092 }, 2093 { 2094 .base.cra_name = "cbc(aes)", 2095 .base.cra_driver_name = "cbc-aes-s5p", 2096 .base.cra_priority = 100, 2097 .base.cra_flags = CRYPTO_ALG_ASYNC | 2098 CRYPTO_ALG_KERN_DRIVER_ONLY, 2099 .base.cra_blocksize = AES_BLOCK_SIZE, 2100 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx), 2101 .base.cra_alignmask = 0x0f, 2102 .base.cra_module = THIS_MODULE, 2103 2104 .min_keysize = AES_MIN_KEY_SIZE, 2105 .max_keysize = AES_MAX_KEY_SIZE, 2106 .ivsize = AES_BLOCK_SIZE, 2107 .setkey = s5p_aes_setkey, 2108 .encrypt = s5p_aes_cbc_encrypt, 2109 .decrypt = s5p_aes_cbc_decrypt, 2110 .init = s5p_aes_init_tfm, 2111 }, 2112 { 2113 .base.cra_name = "ctr(aes)", 2114 .base.cra_driver_name = "ctr-aes-s5p", 2115 .base.cra_priority = 100, 2116 .base.cra_flags = CRYPTO_ALG_ASYNC | 2117 CRYPTO_ALG_KERN_DRIVER_ONLY, 2118 .base.cra_blocksize = 1, 2119 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx), 2120 .base.cra_alignmask = 0x0f, 2121 .base.cra_module = THIS_MODULE, 2122 2123 .min_keysize = AES_MIN_KEY_SIZE, 2124 .max_keysize = AES_MAX_KEY_SIZE, 2125 .ivsize = AES_BLOCK_SIZE, 2126 .setkey = s5p_aes_setkey, 2127 .encrypt = s5p_aes_ctr_crypt, 2128 .decrypt = s5p_aes_ctr_crypt, 2129 .init = s5p_aes_init_tfm, 2130 }, 2131 }; 2132 2133 static int s5p_aes_probe(struct platform_device *pdev) 2134 { 2135 struct device *dev = &pdev->dev; 2136 int i, j, err; 2137 const struct samsung_aes_variant *variant; 2138 struct s5p_aes_dev *pdata; 2139 struct resource *res; 2140 unsigned int hash_i; 2141 2142 if (s5p_dev) 2143 return -EEXIST; 2144 2145 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 2146 if (!pdata) 2147 return -ENOMEM; 2148 2149 variant = find_s5p_sss_version(pdev); 2150 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2151 if (!res) 2152 return -EINVAL; 2153 2154 /* 2155 * Note: HASH and PRNG uses the same registers in secss, avoid 2156 * overwrite each other. This will drop HASH when CONFIG_EXYNOS_RNG 2157 * is enabled in config. We need larger size for HASH registers in 2158 * secss, current describe only AES/DES 2159 */ 2160 if (IS_ENABLED(CONFIG_CRYPTO_DEV_EXYNOS_HASH)) { 2161 if (variant == &exynos_aes_data) { 2162 res->end += 0x300; 2163 pdata->use_hash = true; 2164 } 2165 } 2166 2167 pdata->res = res; 2168 pdata->ioaddr = devm_ioremap_resource(dev, res); 2169 if (IS_ERR(pdata->ioaddr)) { 2170 if (!pdata->use_hash) 2171 return PTR_ERR(pdata->ioaddr); 2172 /* try AES without HASH */ 2173 res->end -= 0x300; 2174 pdata->use_hash = false; 2175 pdata->ioaddr = devm_ioremap_resource(dev, res); 2176 if (IS_ERR(pdata->ioaddr)) 2177 return PTR_ERR(pdata->ioaddr); 2178 } 2179 2180 pdata->clk = devm_clk_get(dev, variant->clk_names[0]); 2181 if (IS_ERR(pdata->clk)) 2182 return dev_err_probe(dev, PTR_ERR(pdata->clk), 2183 "failed to find secss clock %s\n", 2184 variant->clk_names[0]); 2185 2186 err = clk_prepare_enable(pdata->clk); 2187 if (err < 0) { 2188 dev_err(dev, "Enabling clock %s failed, err %d\n", 2189 variant->clk_names[0], err); 2190 return err; 2191 } 2192 2193 if (variant->clk_names[1]) { 2194 pdata->pclk = devm_clk_get(dev, variant->clk_names[1]); 2195 if (IS_ERR(pdata->pclk)) { 2196 err = dev_err_probe(dev, PTR_ERR(pdata->pclk), 2197 "failed to find clock %s\n", 2198 variant->clk_names[1]); 2199 goto err_clk; 2200 } 2201 2202 err = clk_prepare_enable(pdata->pclk); 2203 if (err < 0) { 2204 dev_err(dev, "Enabling clock %s failed, err %d\n", 2205 variant->clk_names[0], err); 2206 goto err_clk; 2207 } 2208 } else { 2209 pdata->pclk = NULL; 2210 } 2211 2212 spin_lock_init(&pdata->lock); 2213 spin_lock_init(&pdata->hash_lock); 2214 2215 pdata->aes_ioaddr = pdata->ioaddr + variant->aes_offset; 2216 pdata->io_hash_base = pdata->ioaddr + variant->hash_offset; 2217 2218 pdata->irq_fc = platform_get_irq(pdev, 0); 2219 if (pdata->irq_fc < 0) { 2220 err = pdata->irq_fc; 2221 dev_warn(dev, "feed control interrupt is not available.\n"); 2222 goto err_irq; 2223 } 2224 err = devm_request_threaded_irq(dev, pdata->irq_fc, NULL, 2225 s5p_aes_interrupt, IRQF_ONESHOT, 2226 pdev->name, pdev); 2227 if (err < 0) { 2228 dev_warn(dev, "feed control interrupt is not available.\n"); 2229 goto err_irq; 2230 } 2231 2232 pdata->busy = false; 2233 pdata->dev = dev; 2234 platform_set_drvdata(pdev, pdata); 2235 s5p_dev = pdata; 2236 2237 tasklet_init(&pdata->tasklet, s5p_tasklet_cb, (unsigned long)pdata); 2238 crypto_init_queue(&pdata->queue, CRYPTO_QUEUE_LEN); 2239 2240 for (i = 0; i < ARRAY_SIZE(algs); i++) { 2241 err = crypto_register_skcipher(&algs[i]); 2242 if (err) 2243 goto err_algs; 2244 } 2245 2246 if (pdata->use_hash) { 2247 tasklet_init(&pdata->hash_tasklet, s5p_hash_tasklet_cb, 2248 (unsigned long)pdata); 2249 crypto_init_queue(&pdata->hash_queue, SSS_HASH_QUEUE_LENGTH); 2250 2251 for (hash_i = 0; hash_i < ARRAY_SIZE(algs_sha1_md5_sha256); 2252 hash_i++) { 2253 struct ahash_alg *alg; 2254 2255 alg = &algs_sha1_md5_sha256[hash_i]; 2256 err = crypto_register_ahash(alg); 2257 if (err) { 2258 dev_err(dev, "can't register '%s': %d\n", 2259 alg->halg.base.cra_driver_name, err); 2260 goto err_hash; 2261 } 2262 } 2263 } 2264 2265 dev_info(dev, "s5p-sss driver registered\n"); 2266 2267 return 0; 2268 2269 err_hash: 2270 for (j = hash_i - 1; j >= 0; j--) 2271 crypto_unregister_ahash(&algs_sha1_md5_sha256[j]); 2272 2273 tasklet_kill(&pdata->hash_tasklet); 2274 res->end -= 0x300; 2275 2276 err_algs: 2277 if (i < ARRAY_SIZE(algs)) 2278 dev_err(dev, "can't register '%s': %d\n", algs[i].base.cra_name, 2279 err); 2280 2281 for (j = 0; j < i; j++) 2282 crypto_unregister_skcipher(&algs[j]); 2283 2284 tasklet_kill(&pdata->tasklet); 2285 2286 err_irq: 2287 clk_disable_unprepare(pdata->pclk); 2288 2289 err_clk: 2290 clk_disable_unprepare(pdata->clk); 2291 s5p_dev = NULL; 2292 2293 return err; 2294 } 2295 2296 static void s5p_aes_remove(struct platform_device *pdev) 2297 { 2298 struct s5p_aes_dev *pdata = platform_get_drvdata(pdev); 2299 int i; 2300 2301 for (i = 0; i < ARRAY_SIZE(algs); i++) 2302 crypto_unregister_skcipher(&algs[i]); 2303 2304 tasklet_kill(&pdata->tasklet); 2305 if (pdata->use_hash) { 2306 for (i = ARRAY_SIZE(algs_sha1_md5_sha256) - 1; i >= 0; i--) 2307 crypto_unregister_ahash(&algs_sha1_md5_sha256[i]); 2308 2309 pdata->res->end -= 0x300; 2310 tasklet_kill(&pdata->hash_tasklet); 2311 pdata->use_hash = false; 2312 } 2313 2314 clk_disable_unprepare(pdata->pclk); 2315 2316 clk_disable_unprepare(pdata->clk); 2317 s5p_dev = NULL; 2318 } 2319 2320 static struct platform_driver s5p_aes_crypto = { 2321 .probe = s5p_aes_probe, 2322 .remove = s5p_aes_remove, 2323 .driver = { 2324 .name = "s5p-secss", 2325 .of_match_table = s5p_sss_dt_match, 2326 }, 2327 }; 2328 2329 module_platform_driver(s5p_aes_crypto); 2330 2331 MODULE_DESCRIPTION("S5PV210 AES hw acceleration support."); 2332 MODULE_LICENSE("GPL v2"); 2333 MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy@gmail.com>"); 2334 MODULE_AUTHOR("Kamil Konieczny <k.konieczny@partner.samsung.com>"); 2335