1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (C) 2020 Marvell. */ 3 4 #include "otx2_cpt_common.h" 5 #include "otx2_cptpf.h" 6 #include "rvu_reg.h" 7 8 /* Fastpath ipsec opcode with inplace processing */ 9 #define CPT_INLINE_RX_OPCODE (0x26 | (1 << 6)) 10 #define CN10K_CPT_INLINE_RX_OPCODE (0x29 | (1 << 6)) 11 12 #define cpt_inline_rx_opcode(pdev) \ 13 ({ \ 14 u8 opcode; \ 15 if (is_dev_otx2(pdev)) \ 16 opcode = CPT_INLINE_RX_OPCODE; \ 17 else \ 18 opcode = CN10K_CPT_INLINE_RX_OPCODE; \ 19 (opcode); \ 20 }) 21 22 /* 23 * CPT PF driver version, It will be incremented by 1 for every feature 24 * addition in CPT mailbox messages. 25 */ 26 #define OTX2_CPT_PF_DRV_VERSION 0x1 27 28 static int forward_to_af(struct otx2_cptpf_dev *cptpf, 29 struct otx2_cptvf_info *vf, 30 struct mbox_msghdr *req, int size) 31 { 32 struct mbox_msghdr *msg; 33 int ret; 34 35 mutex_lock(&cptpf->lock); 36 msg = otx2_mbox_alloc_msg(&cptpf->afpf_mbox, 0, size); 37 if (msg == NULL) { 38 mutex_unlock(&cptpf->lock); 39 return -ENOMEM; 40 } 41 42 memcpy((uint8_t *)msg + sizeof(struct mbox_msghdr), 43 (uint8_t *)req + sizeof(struct mbox_msghdr), size); 44 msg->id = req->id; 45 msg->pcifunc = req->pcifunc; 46 msg->sig = req->sig; 47 msg->ver = req->ver; 48 49 ret = otx2_cpt_sync_mbox_msg(&cptpf->afpf_mbox); 50 /* Error code -EIO indicate there is a communication failure 51 * to the AF. Rest of the error codes indicate that AF processed 52 * VF messages and set the error codes in response messages 53 * (if any) so simply forward responses to VF. 54 */ 55 if (ret == -EIO) { 56 dev_warn(&cptpf->pdev->dev, 57 "AF not responding to VF%d messages\n", vf->vf_id); 58 mutex_unlock(&cptpf->lock); 59 return ret; 60 } 61 mutex_unlock(&cptpf->lock); 62 return 0; 63 } 64 65 static int handle_msg_get_caps(struct otx2_cptpf_dev *cptpf, 66 struct otx2_cptvf_info *vf, 67 struct mbox_msghdr *req) 68 { 69 struct otx2_cpt_caps_rsp *rsp; 70 71 rsp = (struct otx2_cpt_caps_rsp *) 72 otx2_mbox_alloc_msg(&cptpf->vfpf_mbox, vf->vf_id, 73 sizeof(*rsp)); 74 if (!rsp) 75 return -ENOMEM; 76 77 rsp->hdr.id = MBOX_MSG_GET_CAPS; 78 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; 79 rsp->hdr.pcifunc = req->pcifunc; 80 rsp->cpt_pf_drv_version = OTX2_CPT_PF_DRV_VERSION; 81 rsp->cpt_revision = cptpf->eng_grps.rid; 82 memcpy(&rsp->eng_caps, &cptpf->eng_caps, sizeof(rsp->eng_caps)); 83 84 return 0; 85 } 86 87 static int handle_msg_get_eng_grp_num(struct otx2_cptpf_dev *cptpf, 88 struct otx2_cptvf_info *vf, 89 struct mbox_msghdr *req) 90 { 91 struct otx2_cpt_egrp_num_msg *grp_req; 92 struct otx2_cpt_egrp_num_rsp *rsp; 93 94 grp_req = (struct otx2_cpt_egrp_num_msg *)req; 95 rsp = (struct otx2_cpt_egrp_num_rsp *) 96 otx2_mbox_alloc_msg(&cptpf->vfpf_mbox, vf->vf_id, sizeof(*rsp)); 97 if (!rsp) 98 return -ENOMEM; 99 100 rsp->hdr.id = MBOX_MSG_GET_ENG_GRP_NUM; 101 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; 102 rsp->hdr.pcifunc = req->pcifunc; 103 rsp->eng_type = grp_req->eng_type; 104 rsp->eng_grp_num = otx2_cpt_get_eng_grp(&cptpf->eng_grps, 105 grp_req->eng_type); 106 107 return 0; 108 } 109 110 static int handle_msg_kvf_limits(struct otx2_cptpf_dev *cptpf, 111 struct otx2_cptvf_info *vf, 112 struct mbox_msghdr *req) 113 { 114 struct otx2_cpt_kvf_limits_rsp *rsp; 115 116 rsp = (struct otx2_cpt_kvf_limits_rsp *) 117 otx2_mbox_alloc_msg(&cptpf->vfpf_mbox, vf->vf_id, sizeof(*rsp)); 118 if (!rsp) 119 return -ENOMEM; 120 121 rsp->hdr.id = MBOX_MSG_GET_KVF_LIMITS; 122 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; 123 rsp->hdr.pcifunc = req->pcifunc; 124 rsp->kvf_limits = cptpf->kvf_limits; 125 126 return 0; 127 } 128 129 static int send_inline_ipsec_inbound_msg(struct otx2_cptpf_dev *cptpf, 130 int sso_pf_func, u8 slot) 131 { 132 struct cpt_inline_ipsec_cfg_msg *req; 133 struct pci_dev *pdev = cptpf->pdev; 134 135 req = (struct cpt_inline_ipsec_cfg_msg *) 136 otx2_mbox_alloc_msg_rsp(&cptpf->afpf_mbox, 0, 137 sizeof(*req), sizeof(struct msg_rsp)); 138 if (req == NULL) { 139 dev_err(&pdev->dev, "RVU MBOX failed to get message.\n"); 140 return -EFAULT; 141 } 142 memset(req, 0, sizeof(*req)); 143 req->hdr.id = MBOX_MSG_CPT_INLINE_IPSEC_CFG; 144 req->hdr.sig = OTX2_MBOX_REQ_SIG; 145 req->hdr.pcifunc = OTX2_CPT_RVU_PFFUNC(cptpf->pf_id, 0); 146 req->dir = CPT_INLINE_INBOUND; 147 req->slot = slot; 148 req->sso_pf_func_ovrd = cptpf->sso_pf_func_ovrd; 149 req->sso_pf_func = sso_pf_func; 150 req->enable = 1; 151 152 return otx2_cpt_send_mbox_msg(&cptpf->afpf_mbox, pdev); 153 } 154 155 static int rx_inline_ipsec_lf_cfg(struct otx2_cptpf_dev *cptpf, u8 egrp, 156 struct otx2_cpt_rx_inline_lf_cfg *req) 157 { 158 struct nix_inline_ipsec_cfg *nix_req; 159 struct pci_dev *pdev = cptpf->pdev; 160 int ret; 161 162 nix_req = (struct nix_inline_ipsec_cfg *) 163 otx2_mbox_alloc_msg_rsp(&cptpf->afpf_mbox, 0, 164 sizeof(*nix_req), 165 sizeof(struct msg_rsp)); 166 if (nix_req == NULL) { 167 dev_err(&pdev->dev, "RVU MBOX failed to get message.\n"); 168 return -EFAULT; 169 } 170 memset(nix_req, 0, sizeof(*nix_req)); 171 nix_req->hdr.id = MBOX_MSG_NIX_INLINE_IPSEC_CFG; 172 nix_req->hdr.sig = OTX2_MBOX_REQ_SIG; 173 nix_req->enable = 1; 174 nix_req->credit_th = req->credit_th; 175 nix_req->bpid = req->bpid; 176 if (!req->credit || req->credit > OTX2_CPT_INST_QLEN_MSGS) 177 nix_req->cpt_credit = OTX2_CPT_INST_QLEN_MSGS - 1; 178 else 179 nix_req->cpt_credit = req->credit - 1; 180 nix_req->gen_cfg.egrp = egrp; 181 if (req->opcode) 182 nix_req->gen_cfg.opcode = req->opcode; 183 else 184 nix_req->gen_cfg.opcode = cpt_inline_rx_opcode(pdev); 185 nix_req->gen_cfg.param1 = req->param1; 186 nix_req->gen_cfg.param2 = req->param2; 187 nix_req->inst_qsel.cpt_pf_func = OTX2_CPT_RVU_PFFUNC(cptpf->pf_id, 0); 188 nix_req->inst_qsel.cpt_slot = 0; 189 ret = otx2_cpt_send_mbox_msg(&cptpf->afpf_mbox, pdev); 190 if (ret) 191 return ret; 192 193 if (cptpf->has_cpt1) { 194 ret = send_inline_ipsec_inbound_msg(cptpf, req->sso_pf_func, 1); 195 if (ret) 196 return ret; 197 } 198 199 return send_inline_ipsec_inbound_msg(cptpf, req->sso_pf_func, 0); 200 } 201 202 int 203 otx2_inline_cptlf_setup(struct otx2_cptpf_dev *cptpf, 204 struct otx2_cptlfs_info *lfs, u8 egrp, int num_lfs) 205 { 206 int ret; 207 208 ret = otx2_cptlf_init(lfs, 1 << egrp, OTX2_CPT_QUEUE_HI_PRIO, 1); 209 if (ret) { 210 dev_err(&cptpf->pdev->dev, 211 "LF configuration failed for RX inline ipsec.\n"); 212 return ret; 213 } 214 215 /* Get msix offsets for attached LFs */ 216 ret = otx2_cpt_msix_offset_msg(lfs); 217 if (ret) 218 goto cleanup_lf; 219 220 /* Register for CPT LF Misc interrupts */ 221 ret = otx2_cptlf_register_misc_interrupts(lfs); 222 if (ret) 223 goto free_irq; 224 225 return 0; 226 free_irq: 227 otx2_cptlf_unregister_misc_interrupts(lfs); 228 cleanup_lf: 229 otx2_cptlf_shutdown(lfs); 230 return ret; 231 } 232 233 void 234 otx2_inline_cptlf_cleanup(struct otx2_cptlfs_info *lfs) 235 { 236 /* Unregister misc interrupt */ 237 otx2_cptlf_unregister_misc_interrupts(lfs); 238 239 /* Cleanup LFs */ 240 otx2_cptlf_shutdown(lfs); 241 } 242 243 static int handle_msg_rx_inline_ipsec_lf_cfg(struct otx2_cptpf_dev *cptpf, 244 struct mbox_msghdr *req) 245 { 246 struct otx2_cpt_rx_inline_lf_cfg *cfg_req; 247 int num_lfs = 1, ret; 248 u8 egrp; 249 250 cfg_req = (struct otx2_cpt_rx_inline_lf_cfg *)req; 251 if (cptpf->lfs.lfs_num) { 252 dev_err(&cptpf->pdev->dev, 253 "LF is already configured for RX inline ipsec.\n"); 254 return -EEXIST; 255 } 256 /* 257 * Allow LFs to execute requests destined to only grp IE_TYPES and 258 * set queue priority of each LF to high 259 */ 260 egrp = otx2_cpt_get_eng_grp(&cptpf->eng_grps, OTX2_CPT_IE_TYPES); 261 if (egrp == OTX2_CPT_INVALID_CRYPTO_ENG_GRP) { 262 dev_err(&cptpf->pdev->dev, 263 "Engine group for inline ipsec is not available\n"); 264 return -ENOENT; 265 } 266 267 cptpf->lfs.global_slot = 0; 268 cptpf->lfs.ctx_ilen_ovrd = cfg_req->ctx_ilen_valid; 269 cptpf->lfs.ctx_ilen = cfg_req->ctx_ilen; 270 271 ret = otx2_inline_cptlf_setup(cptpf, &cptpf->lfs, egrp, num_lfs); 272 if (ret) { 273 dev_err(&cptpf->pdev->dev, "Inline-Ipsec CPT0 LF setup failed.\n"); 274 return ret; 275 } 276 277 if (cptpf->has_cpt1) { 278 cptpf->rsrc_req_blkaddr = BLKADDR_CPT1; 279 cptpf->cpt1_lfs.global_slot = num_lfs; 280 cptpf->cpt1_lfs.ctx_ilen_ovrd = cfg_req->ctx_ilen_valid; 281 cptpf->cpt1_lfs.ctx_ilen = cfg_req->ctx_ilen; 282 ret = otx2_inline_cptlf_setup(cptpf, &cptpf->cpt1_lfs, egrp, 283 num_lfs); 284 if (ret) { 285 dev_err(&cptpf->pdev->dev, "Inline CPT1 LF setup failed.\n"); 286 goto lf_cleanup; 287 } 288 cptpf->rsrc_req_blkaddr = 0; 289 } 290 291 ret = rx_inline_ipsec_lf_cfg(cptpf, egrp, cfg_req); 292 if (ret) 293 goto lf1_cleanup; 294 295 return 0; 296 297 lf1_cleanup: 298 otx2_inline_cptlf_cleanup(&cptpf->cpt1_lfs); 299 lf_cleanup: 300 otx2_inline_cptlf_cleanup(&cptpf->lfs); 301 return ret; 302 } 303 304 static int cptpf_handle_vf_req(struct otx2_cptpf_dev *cptpf, 305 struct otx2_cptvf_info *vf, 306 struct mbox_msghdr *req, int size) 307 { 308 int err = 0; 309 310 /* Check if msg is valid, if not reply with an invalid msg */ 311 if (req->sig != OTX2_MBOX_REQ_SIG) 312 goto inval_msg; 313 314 switch (req->id) { 315 case MBOX_MSG_GET_ENG_GRP_NUM: 316 err = handle_msg_get_eng_grp_num(cptpf, vf, req); 317 break; 318 case MBOX_MSG_GET_CAPS: 319 err = handle_msg_get_caps(cptpf, vf, req); 320 break; 321 case MBOX_MSG_GET_KVF_LIMITS: 322 err = handle_msg_kvf_limits(cptpf, vf, req); 323 break; 324 case MBOX_MSG_RX_INLINE_IPSEC_LF_CFG: 325 err = handle_msg_rx_inline_ipsec_lf_cfg(cptpf, req); 326 break; 327 328 default: 329 err = forward_to_af(cptpf, vf, req, size); 330 break; 331 } 332 return err; 333 334 inval_msg: 335 otx2_reply_invalid_msg(&cptpf->vfpf_mbox, vf->vf_id, 0, req->id); 336 otx2_mbox_msg_send(&cptpf->vfpf_mbox, vf->vf_id); 337 return err; 338 } 339 340 irqreturn_t otx2_cptpf_vfpf_mbox_intr(int __always_unused irq, void *arg) 341 { 342 struct otx2_cptpf_dev *cptpf = arg; 343 struct otx2_cptvf_info *vf; 344 int i, vf_idx; 345 u64 intr; 346 347 /* 348 * Check which VF has raised an interrupt and schedule 349 * corresponding work queue to process the messages 350 */ 351 for (i = 0; i < 2; i++) { 352 /* Read the interrupt bits */ 353 intr = otx2_cpt_read64(cptpf->reg_base, BLKADDR_RVUM, 0, 354 RVU_PF_VFPF_MBOX_INTX(i)); 355 356 for (vf_idx = i * 64; vf_idx < cptpf->enabled_vfs; vf_idx++) { 357 vf = &cptpf->vf[vf_idx]; 358 if (intr & (1ULL << vf->intr_idx)) { 359 queue_work(cptpf->vfpf_mbox_wq, 360 &vf->vfpf_mbox_work); 361 /* Clear the interrupt */ 362 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 363 0, RVU_PF_VFPF_MBOX_INTX(i), 364 BIT_ULL(vf->intr_idx)); 365 } 366 } 367 } 368 return IRQ_HANDLED; 369 } 370 371 void otx2_cptpf_vfpf_mbox_handler(struct work_struct *work) 372 { 373 struct otx2_cptpf_dev *cptpf; 374 struct otx2_cptvf_info *vf; 375 struct otx2_mbox_dev *mdev; 376 struct mbox_hdr *req_hdr; 377 struct mbox_msghdr *msg; 378 struct otx2_mbox *mbox; 379 int offset, i, err; 380 381 vf = container_of(work, struct otx2_cptvf_info, vfpf_mbox_work); 382 cptpf = vf->cptpf; 383 mbox = &cptpf->vfpf_mbox; 384 /* sync with mbox memory region */ 385 smp_rmb(); 386 mdev = &mbox->dev[vf->vf_id]; 387 /* Process received mbox messages */ 388 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 389 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 390 391 for (i = 0; i < req_hdr->num_msgs; i++) { 392 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 393 394 /* Set which VF sent this message based on mbox IRQ */ 395 msg->pcifunc = ((u16)cptpf->pf_id << RVU_PFVF_PF_SHIFT) | 396 ((vf->vf_id + 1) & RVU_PFVF_FUNC_MASK); 397 398 err = cptpf_handle_vf_req(cptpf, vf, msg, 399 msg->next_msgoff - offset); 400 /* 401 * Behave as the AF, drop the msg if there is 402 * no memory, timeout handling also goes here 403 */ 404 if (err == -ENOMEM || err == -EIO) 405 break; 406 offset = msg->next_msgoff; 407 /* Write barrier required for VF responses which are handled by 408 * PF driver and not forwarded to AF. 409 */ 410 smp_wmb(); 411 } 412 /* Send mbox responses to VF */ 413 if (mdev->num_msgs) 414 otx2_mbox_msg_send(mbox, vf->vf_id); 415 } 416 417 irqreturn_t otx2_cptpf_afpf_mbox_intr(int __always_unused irq, void *arg) 418 { 419 struct otx2_cptpf_dev *cptpf = arg; 420 struct otx2_mbox_dev *mdev; 421 struct otx2_mbox *mbox; 422 struct mbox_hdr *hdr; 423 u64 intr; 424 425 /* Read the interrupt bits */ 426 intr = otx2_cpt_read64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_INT); 427 428 if (intr & 0x1ULL) { 429 mbox = &cptpf->afpf_mbox; 430 mdev = &mbox->dev[0]; 431 hdr = mdev->mbase + mbox->rx_start; 432 if (hdr->num_msgs) 433 /* Schedule work queue function to process the MBOX request */ 434 queue_work(cptpf->afpf_mbox_wq, &cptpf->afpf_mbox_work); 435 436 mbox = &cptpf->afpf_mbox_up; 437 mdev = &mbox->dev[0]; 438 hdr = mdev->mbase + mbox->rx_start; 439 if (hdr->num_msgs) 440 /* Schedule work queue function to process the MBOX request */ 441 queue_work(cptpf->afpf_mbox_wq, &cptpf->afpf_mbox_up_work); 442 /* Clear and ack the interrupt */ 443 otx2_cpt_write64(cptpf->reg_base, BLKADDR_RVUM, 0, RVU_PF_INT, 444 0x1ULL); 445 } 446 return IRQ_HANDLED; 447 } 448 449 static void process_afpf_mbox_msg(struct otx2_cptpf_dev *cptpf, 450 struct mbox_msghdr *msg) 451 { 452 struct otx2_cptlfs_info *lfs = &cptpf->lfs; 453 struct device *dev = &cptpf->pdev->dev; 454 struct cpt_rd_wr_reg_msg *rsp_rd_wr; 455 struct msix_offset_rsp *rsp_msix; 456 int i; 457 458 if (msg->id >= MBOX_MSG_MAX) { 459 dev_err(dev, "MBOX msg with unknown ID %d\n", msg->id); 460 return; 461 } 462 if (msg->sig != OTX2_MBOX_RSP_SIG) { 463 dev_err(dev, "MBOX msg with wrong signature %x, ID %d\n", 464 msg->sig, msg->id); 465 return; 466 } 467 if (cptpf->rsrc_req_blkaddr == BLKADDR_CPT1) 468 lfs = &cptpf->cpt1_lfs; 469 470 switch (msg->id) { 471 case MBOX_MSG_READY: 472 cptpf->pf_id = (msg->pcifunc >> RVU_PFVF_PF_SHIFT) & 473 RVU_PFVF_PF_MASK; 474 break; 475 case MBOX_MSG_MSIX_OFFSET: 476 rsp_msix = (struct msix_offset_rsp *) msg; 477 for (i = 0; i < rsp_msix->cptlfs; i++) 478 lfs->lf[i].msix_offset = rsp_msix->cptlf_msixoff[i]; 479 480 for (i = 0; i < rsp_msix->cpt1_lfs; i++) 481 lfs->lf[i].msix_offset = rsp_msix->cpt1_lf_msixoff[i]; 482 break; 483 case MBOX_MSG_CPT_RD_WR_REGISTER: 484 rsp_rd_wr = (struct cpt_rd_wr_reg_msg *)msg; 485 if (msg->rc) { 486 dev_err(dev, "Reg %llx rd/wr(%d) failed %d\n", 487 rsp_rd_wr->reg_offset, rsp_rd_wr->is_write, 488 msg->rc); 489 return; 490 } 491 if (!rsp_rd_wr->is_write) 492 *rsp_rd_wr->ret_val = rsp_rd_wr->val; 493 break; 494 case MBOX_MSG_ATTACH_RESOURCES: 495 if (!msg->rc) 496 lfs->are_lfs_attached = 1; 497 break; 498 case MBOX_MSG_DETACH_RESOURCES: 499 if (!msg->rc) 500 lfs->are_lfs_attached = 0; 501 break; 502 case MBOX_MSG_CPT_INLINE_IPSEC_CFG: 503 case MBOX_MSG_NIX_INLINE_IPSEC_CFG: 504 case MBOX_MSG_CPT_LF_RESET: 505 case MBOX_MSG_LMTST_TBL_SETUP: 506 break; 507 508 default: 509 dev_err(dev, 510 "Unsupported msg %d received.\n", msg->id); 511 break; 512 } 513 } 514 515 static void forward_to_vf(struct otx2_cptpf_dev *cptpf, struct mbox_msghdr *msg, 516 int vf_id, int size) 517 { 518 struct otx2_mbox *vfpf_mbox; 519 struct mbox_msghdr *fwd; 520 521 if (msg->id >= MBOX_MSG_MAX) { 522 dev_err(&cptpf->pdev->dev, 523 "MBOX msg with unknown ID %d\n", msg->id); 524 return; 525 } 526 if (msg->sig != OTX2_MBOX_RSP_SIG) { 527 dev_err(&cptpf->pdev->dev, 528 "MBOX msg with wrong signature %x, ID %d\n", 529 msg->sig, msg->id); 530 return; 531 } 532 vfpf_mbox = &cptpf->vfpf_mbox; 533 vf_id--; 534 if (vf_id >= cptpf->enabled_vfs) { 535 dev_err(&cptpf->pdev->dev, 536 "MBOX msg to unknown VF: %d >= %d\n", 537 vf_id, cptpf->enabled_vfs); 538 return; 539 } 540 if (msg->id == MBOX_MSG_VF_FLR) 541 return; 542 543 fwd = otx2_mbox_alloc_msg(vfpf_mbox, vf_id, size); 544 if (!fwd) { 545 dev_err(&cptpf->pdev->dev, 546 "Forwarding to VF%d failed.\n", vf_id); 547 return; 548 } 549 memcpy((uint8_t *)fwd + sizeof(struct mbox_msghdr), 550 (uint8_t *)msg + sizeof(struct mbox_msghdr), size); 551 fwd->id = msg->id; 552 fwd->pcifunc = msg->pcifunc; 553 fwd->sig = msg->sig; 554 fwd->ver = msg->ver; 555 fwd->rc = msg->rc; 556 } 557 558 /* Handle mailbox messages received from AF */ 559 void otx2_cptpf_afpf_mbox_handler(struct work_struct *work) 560 { 561 struct otx2_cptpf_dev *cptpf; 562 struct otx2_mbox *afpf_mbox; 563 struct otx2_mbox_dev *mdev; 564 struct mbox_hdr *rsp_hdr; 565 struct mbox_msghdr *msg; 566 int offset, vf_id, i; 567 568 cptpf = container_of(work, struct otx2_cptpf_dev, afpf_mbox_work); 569 afpf_mbox = &cptpf->afpf_mbox; 570 mdev = &afpf_mbox->dev[0]; 571 /* Sync mbox data into memory */ 572 smp_wmb(); 573 574 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + afpf_mbox->rx_start); 575 offset = ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 576 577 for (i = 0; i < rsp_hdr->num_msgs; i++) { 578 msg = (struct mbox_msghdr *)(mdev->mbase + afpf_mbox->rx_start + 579 offset); 580 vf_id = (msg->pcifunc >> RVU_PFVF_FUNC_SHIFT) & 581 RVU_PFVF_FUNC_MASK; 582 if (vf_id > 0) 583 forward_to_vf(cptpf, msg, vf_id, 584 msg->next_msgoff - offset); 585 else 586 process_afpf_mbox_msg(cptpf, msg); 587 588 offset = msg->next_msgoff; 589 /* Sync VF response ready to be sent */ 590 smp_wmb(); 591 mdev->msgs_acked++; 592 } 593 otx2_mbox_reset(afpf_mbox, 0); 594 } 595 596 static void handle_msg_cpt_inst_lmtst(struct otx2_cptpf_dev *cptpf, 597 struct mbox_msghdr *msg) 598 { 599 struct cpt_inst_lmtst_req *req = (struct cpt_inst_lmtst_req *)msg; 600 struct otx2_cptlfs_info *lfs = &cptpf->lfs; 601 struct msg_rsp *rsp; 602 603 if (cptpf->lfs.lfs_num) 604 lfs->ops->send_cmd((union otx2_cpt_inst_s *)req->inst, 1, 605 &lfs->lf[0]); 606 607 rsp = (struct msg_rsp *)otx2_mbox_alloc_msg(&cptpf->afpf_mbox_up, 0, 608 sizeof(*rsp)); 609 if (!rsp) 610 return; 611 612 rsp->hdr.id = msg->id; 613 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; 614 rsp->hdr.pcifunc = 0; 615 rsp->hdr.rc = 0; 616 } 617 618 static void process_afpf_mbox_up_msg(struct otx2_cptpf_dev *cptpf, 619 struct mbox_msghdr *msg) 620 { 621 if (msg->id >= MBOX_MSG_MAX) { 622 dev_err(&cptpf->pdev->dev, 623 "MBOX msg with unknown ID %d\n", msg->id); 624 return; 625 } 626 627 switch (msg->id) { 628 case MBOX_MSG_CPT_INST_LMTST: 629 handle_msg_cpt_inst_lmtst(cptpf, msg); 630 break; 631 default: 632 otx2_reply_invalid_msg(&cptpf->afpf_mbox_up, 0, 0, msg->id); 633 } 634 } 635 636 void otx2_cptpf_afpf_mbox_up_handler(struct work_struct *work) 637 { 638 struct otx2_cptpf_dev *cptpf; 639 struct otx2_mbox_dev *mdev; 640 struct mbox_hdr *rsp_hdr; 641 struct mbox_msghdr *msg; 642 struct otx2_mbox *mbox; 643 int offset, i; 644 645 cptpf = container_of(work, struct otx2_cptpf_dev, afpf_mbox_up_work); 646 mbox = &cptpf->afpf_mbox_up; 647 mdev = &mbox->dev[0]; 648 /* Sync mbox data into memory */ 649 smp_wmb(); 650 651 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 652 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 653 654 for (i = 0; i < rsp_hdr->num_msgs; i++) { 655 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 656 657 process_afpf_mbox_up_msg(cptpf, msg); 658 659 offset = mbox->rx_start + msg->next_msgoff; 660 } 661 otx2_mbox_msg_send(mbox, 0); 662 } 663