15e8ce833SSrujana Challa /* SPDX-License-Identifier: GPL-2.0-only 25e8ce833SSrujana Challa * Copyright (C) 2020 Marvell. 35e8ce833SSrujana Challa */ 45e8ce833SSrujana Challa 55e8ce833SSrujana Challa #ifndef __OTX2_CPTPF_H 65e8ce833SSrujana Challa #define __OTX2_CPTPF_H 75e8ce833SSrujana Challa 883ffcf78SSrujana Challa #include "otx2_cpt_common.h" 943ac0b82SSrujana Challa #include "otx2_cptpf_ucode.h" 1064506017SSrujana Challa #include "otx2_cptlf.h" 1183ffcf78SSrujana Challa 12fe16eceaSSrujana Challa struct otx2_cptpf_dev; 13fe16eceaSSrujana Challa struct otx2_cptvf_info { 14fe16eceaSSrujana Challa struct otx2_cptpf_dev *cptpf; /* PF pointer this VF belongs to */ 15fe16eceaSSrujana Challa struct work_struct vfpf_mbox_work; 16fe16eceaSSrujana Challa struct pci_dev *vf_dev; 17fe16eceaSSrujana Challa int vf_id; 18fe16eceaSSrujana Challa int intr_idx; 19fe16eceaSSrujana Challa }; 20fe16eceaSSrujana Challa 21fe16eceaSSrujana Challa struct cptpf_flr_work { 22fe16eceaSSrujana Challa struct work_struct work; 23fe16eceaSSrujana Challa struct otx2_cptpf_dev *pf; 24fe16eceaSSrujana Challa }; 25fe16eceaSSrujana Challa 265e8ce833SSrujana Challa struct otx2_cptpf_dev { 275e8ce833SSrujana Challa void __iomem *reg_base; /* CPT PF registers start address */ 2883ffcf78SSrujana Challa void __iomem *afpf_mbox_base; /* PF-AF mbox start address */ 29fe16eceaSSrujana Challa void __iomem *vfpf_mbox_base; /* VF-PF mbox start address */ 305e8ce833SSrujana Challa struct pci_dev *pdev; /* PCI device handle */ 31fe16eceaSSrujana Challa struct otx2_cptvf_info vf[OTX2_CPT_MAX_VFS_NUM]; 3243ac0b82SSrujana Challa struct otx2_cpt_eng_grps eng_grps;/* Engine groups information */ 3364506017SSrujana Challa struct otx2_cptlfs_info lfs; /* CPT LFs attached to this PF */ 3478506c2aSSrujana Challa /* HW capabilities for each engine type */ 3578506c2aSSrujana Challa union otx2_cpt_eng_caps eng_caps[OTX2_CPT_MAX_ENG_TYPES]; 3678506c2aSSrujana Challa bool is_eng_caps_discovered; 3743ac0b82SSrujana Challa 3883ffcf78SSrujana Challa /* AF <=> PF mbox */ 3983ffcf78SSrujana Challa struct otx2_mbox afpf_mbox; 4083ffcf78SSrujana Challa struct work_struct afpf_mbox_work; 4183ffcf78SSrujana Challa struct workqueue_struct *afpf_mbox_wq; 4283ffcf78SSrujana Challa 43fe16eceaSSrujana Challa /* VF <=> PF mbox */ 44fe16eceaSSrujana Challa struct otx2_mbox vfpf_mbox; 45fe16eceaSSrujana Challa struct workqueue_struct *vfpf_mbox_wq; 46fe16eceaSSrujana Challa 47fe16eceaSSrujana Challa struct workqueue_struct *flr_wq; 48fe16eceaSSrujana Challa struct cptpf_flr_work *flr_work; 49fe16eceaSSrujana Challa 5083ffcf78SSrujana Challa u8 pf_id; /* RVU PF number */ 51fe16eceaSSrujana Challa u8 max_vfs; /* Maximum number of VFs supported by CPT */ 52fe16eceaSSrujana Challa u8 enabled_vfs; /* Number of enabled VFs */ 535e8ce833SSrujana Challa }; 545e8ce833SSrujana Challa 5583ffcf78SSrujana Challa irqreturn_t otx2_cptpf_afpf_mbox_intr(int irq, void *arg); 5683ffcf78SSrujana Challa void otx2_cptpf_afpf_mbox_handler(struct work_struct *work); 57fe16eceaSSrujana Challa irqreturn_t otx2_cptpf_vfpf_mbox_intr(int irq, void *arg); 58fe16eceaSSrujana Challa void otx2_cptpf_vfpf_mbox_handler(struct work_struct *work); 5983ffcf78SSrujana Challa 605e8ce833SSrujana Challa #endif /* __OTX2_CPTPF_H */ 61