1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Sophgo SG2044 clock controller driver 4 * 5 * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com> 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/cleanup.h> 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/io.h> 15 #include <linux/iopoll.h> 16 #include <linux/math64.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 #include <linux/spinlock.h> 21 22 #include <dt-bindings/clock/sophgo,sg2044-clk.h> 23 24 #define DIV_ASSERT BIT(0) 25 #define DIV_FACTOR_REG_SOURCE BIT(3) 26 #define DIV_BRANCH_EN BIT(4) 27 28 #define DIV_ASSERT_TIME 2 29 30 struct sg2044_div_internal { 31 u32 offset; 32 u32 initval; 33 u8 shift; 34 u8 width; 35 u16 flags; 36 }; 37 38 struct sg2044_mux_internal { 39 const u32 *table; 40 u32 offset; 41 u16 shift; 42 u16 flags; 43 }; 44 45 struct sg2044_gate_internal { 46 u32 offset; 47 u16 shift; 48 u16 flags; 49 }; 50 51 struct sg2044_clk_common { 52 struct clk_hw hw; 53 void __iomem *base; 54 spinlock_t *lock; 55 unsigned int id; 56 }; 57 58 struct sg2044_div { 59 struct sg2044_clk_common common; 60 struct sg2044_div_internal div; 61 }; 62 63 struct sg2044_mux { 64 struct sg2044_clk_common common; 65 struct sg2044_mux_internal mux; 66 struct notifier_block nb; 67 u8 saved_parent; 68 }; 69 70 struct sg2044_gate { 71 struct sg2044_clk_common common; 72 struct sg2044_gate_internal gate; 73 }; 74 75 struct sg2044_clk_ctrl { 76 spinlock_t lock; 77 struct clk_hw_onecell_data data; 78 }; 79 80 struct sg2044_clk_desc_data { 81 struct sg2044_clk_common * const *pll; 82 struct sg2044_clk_common * const *div; 83 struct sg2044_clk_common * const *mux; 84 struct sg2044_clk_common * const *gate; 85 u16 num_pll; 86 u16 num_div; 87 u16 num_mux; 88 u16 num_gate; 89 }; 90 91 #define hw_to_sg2044_clk_common(_hw) \ 92 container_of((_hw), struct sg2044_clk_common, hw) 93 94 static inline struct sg2044_div *hw_to_sg2044_div(struct clk_hw *hw) 95 { 96 return container_of(hw_to_sg2044_clk_common(hw), 97 struct sg2044_div, common); 98 } 99 100 static u32 sg2044_div_get_reg_div(u32 reg, struct sg2044_div_internal *div) 101 { 102 if ((reg & DIV_FACTOR_REG_SOURCE)) 103 return (reg >> div->shift) & clk_div_mask(div->width); 104 105 return div->initval == 0 ? 1 : div->initval; 106 } 107 108 static unsigned long _sg2044_div_recalc_rate(struct sg2044_clk_common *common, 109 struct sg2044_div_internal *div, 110 unsigned long parent_rate) 111 { 112 u32 reg = readl(common->base + div->offset); 113 u32 val = sg2044_div_get_reg_div(reg, div); 114 115 return divider_recalc_rate(&common->hw, parent_rate, val, NULL, 116 div->flags, div->width); 117 } 118 119 static unsigned long sg2044_div_recalc_rate(struct clk_hw *hw, 120 unsigned long parent_rate) 121 { 122 struct sg2044_div *div = hw_to_sg2044_div(hw); 123 124 return _sg2044_div_recalc_rate(&div->common, &div->div, 125 parent_rate); 126 } 127 128 static int _sg2044_div_determine_rate(struct sg2044_clk_common *common, 129 struct sg2044_div_internal *div, 130 struct clk_rate_request *req) 131 { 132 if (div->flags & CLK_DIVIDER_READ_ONLY) { 133 u32 reg = readl(common->base + div->offset); 134 u32 val = sg2044_div_get_reg_div(reg, div); 135 136 return divider_ro_determine_rate(&common->hw, req, NULL, 137 div->width, div->flags, 138 val); 139 } 140 141 return divider_determine_rate(&common->hw, req, NULL, 142 div->width, div->flags); 143 } 144 145 static int sg2044_div_determine_rate(struct clk_hw *hw, 146 struct clk_rate_request *req) 147 { 148 struct sg2044_div *div = hw_to_sg2044_div(hw); 149 150 return _sg2044_div_determine_rate(&div->common, &div->div, req); 151 } 152 153 static void sg2044_div_set_reg_div(struct sg2044_clk_common *common, 154 struct sg2044_div_internal *div, 155 u32 value) 156 { 157 void __iomem *addr = common->base + div->offset; 158 u32 reg; 159 160 reg = readl(addr); 161 162 /* assert */ 163 reg &= ~DIV_ASSERT; 164 writel(reg, addr); 165 166 /* set value */ 167 reg = readl(addr); 168 reg &= ~(clk_div_mask(div->width) << div->shift); 169 reg |= (value << div->shift) | DIV_FACTOR_REG_SOURCE; 170 writel(reg, addr); 171 172 /* de-assert */ 173 reg |= DIV_ASSERT; 174 writel(reg, addr); 175 } 176 177 static int sg2044_div_set_rate(struct clk_hw *hw, 178 unsigned long rate, unsigned long parent_rate) 179 { 180 struct sg2044_div *div = hw_to_sg2044_div(hw); 181 u32 value; 182 183 value = divider_get_val(rate, parent_rate, NULL, 184 div->div.width, div->div.flags); 185 186 guard(spinlock_irqsave)(div->common.lock); 187 188 sg2044_div_set_reg_div(&div->common, &div->div, value); 189 190 return 0; 191 } 192 193 static int sg2044_div_enable(struct clk_hw *hw) 194 { 195 struct sg2044_div *div = hw_to_sg2044_div(hw); 196 void __iomem *addr = div->common.base + div->div.offset; 197 u32 value; 198 199 guard(spinlock_irqsave)(div->common.lock); 200 201 value = readl(addr); 202 value |= DIV_BRANCH_EN; 203 writel(value, addr); 204 205 return 0; 206 } 207 208 static void sg2044_div_disable(struct clk_hw *hw) 209 { 210 struct sg2044_div *div = hw_to_sg2044_div(hw); 211 void __iomem *addr = div->common.base + div->div.offset; 212 u32 value; 213 214 guard(spinlock_irqsave)(div->common.lock); 215 216 value = readl(addr); 217 value &= ~DIV_BRANCH_EN; 218 writel(value, addr); 219 } 220 221 static int sg2044_div_is_enabled(struct clk_hw *hw) 222 { 223 struct sg2044_div *div = hw_to_sg2044_div(hw); 224 225 return readl(div->common.base + div->div.offset) & DIV_BRANCH_EN; 226 } 227 228 static const struct clk_ops sg2044_gateable_div_ops = { 229 .enable = sg2044_div_enable, 230 .disable = sg2044_div_disable, 231 .is_enabled = sg2044_div_is_enabled, 232 .recalc_rate = sg2044_div_recalc_rate, 233 .determine_rate = sg2044_div_determine_rate, 234 .set_rate = sg2044_div_set_rate, 235 }; 236 237 static const struct clk_ops sg2044_div_ops = { 238 .recalc_rate = sg2044_div_recalc_rate, 239 .determine_rate = sg2044_div_determine_rate, 240 .set_rate = sg2044_div_set_rate, 241 }; 242 243 static const struct clk_ops sg2044_div_ro_ops = { 244 .recalc_rate = sg2044_div_recalc_rate, 245 .determine_rate = sg2044_div_determine_rate, 246 }; 247 248 static inline struct sg2044_mux *hw_to_sg2044_mux(struct clk_hw *hw) 249 { 250 return container_of(hw_to_sg2044_clk_common(hw), 251 struct sg2044_mux, common); 252 } 253 254 static inline struct sg2044_mux *nb_to_sg2044_mux(struct notifier_block *nb) 255 { 256 return container_of(nb, struct sg2044_mux, nb); 257 } 258 259 static const u32 sg2044_mux_table[] = {0, 1}; 260 261 static int sg2044_mux_notifier_cb(struct notifier_block *nb, 262 unsigned long event, 263 void *data) 264 { 265 struct sg2044_mux *mux = nb_to_sg2044_mux(nb); 266 const struct clk_ops *ops = &clk_mux_ops; 267 struct clk_notifier_data *ndata = data; 268 struct clk_hw *hw = __clk_get_hw(ndata->clk); 269 int ret = 0; 270 271 if (event == PRE_RATE_CHANGE) { 272 mux->saved_parent = ops->get_parent(hw); 273 if (mux->saved_parent) 274 ret = ops->set_parent(hw, 0); 275 } else if (event == POST_RATE_CHANGE) { 276 ret = ops->set_parent(hw, mux->saved_parent); 277 } 278 279 return notifier_from_errno(ret); 280 } 281 282 static inline struct sg2044_gate *hw_to_sg2044_gate(struct clk_hw *hw) 283 { 284 return container_of(hw_to_sg2044_clk_common(hw), 285 struct sg2044_gate, common); 286 } 287 288 #define SG2044_CLK_COMMON_PDATA(_id, _name, _parents, _op, _flags) \ 289 { \ 290 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parents, \ 291 _op, (_flags)), \ 292 .id = (_id), \ 293 } 294 295 #define SG2044_CLK_COMMON_PHWS(_id, _name, _parents, _op, _flags) \ 296 { \ 297 .hw.init = CLK_HW_INIT_PARENTS_HW(_name, _parents, \ 298 _op, (_flags)), \ 299 .id = (_id), \ 300 } 301 302 #define DEFINE_SG2044_GATEABLE_DIV(_id, _name, _parent, _flags, \ 303 _div_offset, _div_shift, _div_width, \ 304 _div_flags, _div_initval) \ 305 struct sg2044_div _name = { \ 306 .common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \ 307 &sg2044_gateable_div_ops,\ 308 (_flags)), \ 309 .div = { \ 310 .offset = (_div_offset), \ 311 .initval = (_div_initval), \ 312 .shift = (_div_shift), \ 313 .width = (_div_width), \ 314 .flags = (_div_flags), \ 315 }, \ 316 } 317 318 #define DEFINE_SG2044_DIV(_id, _name, _parent, _flags, \ 319 _div_offset, _div_shift, _div_width, \ 320 _div_flags, _div_initval) \ 321 struct sg2044_div _name = { \ 322 .common = SG2044_CLK_COMMON_PHWS(_id, #_name, _parent, \ 323 &sg2044_div_ops, \ 324 (_flags)), \ 325 .div = { \ 326 .offset = (_div_offset), \ 327 .initval = (_div_initval), \ 328 .shift = (_div_shift), \ 329 .width = (_div_width), \ 330 .flags = (_div_flags), \ 331 }, \ 332 } 333 334 #define DEFINE_SG2044_DIV_PDATA(_id, _name, _parent, _flags, \ 335 _div_offset, _div_shift, _div_width, \ 336 _div_flags, _div_initval) \ 337 struct sg2044_div _name = { \ 338 .common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \ 339 &sg2044_div_ops, \ 340 (_flags)), \ 341 .div = { \ 342 .offset = (_div_offset), \ 343 .initval = (_div_initval), \ 344 .shift = (_div_shift), \ 345 .width = (_div_width), \ 346 .flags = (_div_flags), \ 347 }, \ 348 } 349 350 #define DEFINE_SG2044_DIV_RO(_id, _name, _parent, _flags, \ 351 _div_offset, _div_shift, _div_width, \ 352 _div_flags, _div_initval) \ 353 struct sg2044_div _name = { \ 354 .common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \ 355 &sg2044_div_ro_ops, \ 356 (_flags)), \ 357 .div = { \ 358 .offset = (_div_offset), \ 359 .initval = (_div_initval), \ 360 .shift = (_div_shift), \ 361 .width = (_div_width), \ 362 .flags = (_div_flags) | CLK_DIVIDER_READ_ONLY,\ 363 }, \ 364 } 365 366 #define DEFINE_SG2044_MUX(_id, _name, _parent, _flags, \ 367 _mux_offset, _mux_shift, \ 368 _mux_table, _mux_flags) \ 369 struct sg2044_mux _name = { \ 370 .common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \ 371 &clk_mux_ops, (_flags)),\ 372 .mux = { \ 373 .table = (_mux_table), \ 374 .offset = (_mux_offset), \ 375 .shift = (_mux_shift), \ 376 .flags = (_mux_flags), \ 377 }, \ 378 } 379 380 #define DEFINE_SG2044_GATE(_id, _name, _parent, _flags, \ 381 _gate_offset, _gate_shift, _gate_flags) \ 382 struct sg2044_gate _name = { \ 383 .common = SG2044_CLK_COMMON_PHWS(_id, #_name, _parent, \ 384 &clk_gate_ops, (_flags)),\ 385 .gate = { \ 386 .offset = (_gate_offset), \ 387 .shift = (_gate_shift), \ 388 .flags = (_gate_flags), \ 389 }, \ 390 } 391 392 static const struct clk_parent_data clk_fpll0_parent[] = { 393 { .fw_name = "fpll0" }, 394 }; 395 396 static const struct clk_parent_data clk_fpll1_parent[] = { 397 { .fw_name = "fpll1" }, 398 }; 399 400 static const struct clk_parent_data clk_fpll2_parent[] = { 401 { .fw_name = "fpll2" }, 402 }; 403 404 static const struct clk_parent_data clk_dpll0_parent[] = { 405 { .fw_name = "dpll0" }, 406 }; 407 408 static const struct clk_parent_data clk_dpll1_parent[] = { 409 { .fw_name = "dpll1" }, 410 }; 411 412 static const struct clk_parent_data clk_dpll2_parent[] = { 413 { .fw_name = "dpll2" }, 414 }; 415 416 static const struct clk_parent_data clk_dpll3_parent[] = { 417 { .fw_name = "dpll3" }, 418 }; 419 420 static const struct clk_parent_data clk_dpll4_parent[] = { 421 { .fw_name = "dpll4" }, 422 }; 423 424 static const struct clk_parent_data clk_dpll5_parent[] = { 425 { .fw_name = "dpll5" }, 426 }; 427 428 static const struct clk_parent_data clk_dpll6_parent[] = { 429 { .fw_name = "dpll6" }, 430 }; 431 432 static const struct clk_parent_data clk_dpll7_parent[] = { 433 { .fw_name = "dpll7" }, 434 }; 435 436 static const struct clk_parent_data clk_mpll0_parent[] = { 437 { .fw_name = "mpll0" }, 438 }; 439 440 static const struct clk_parent_data clk_mpll1_parent[] = { 441 { .fw_name = "mpll1" }, 442 }; 443 444 static const struct clk_parent_data clk_mpll2_parent[] = { 445 { .fw_name = "mpll2" }, 446 }; 447 448 static const struct clk_parent_data clk_mpll3_parent[] = { 449 { .fw_name = "mpll3" }, 450 }; 451 452 static const struct clk_parent_data clk_mpll4_parent[] = { 453 { .fw_name = "mpll4" }, 454 }; 455 456 static const struct clk_parent_data clk_mpll5_parent[] = { 457 { .fw_name = "mpll5" }, 458 }; 459 460 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_AP_SYS_FIXED, clk_div_ap_sys_fixed, 461 clk_fpll0_parent, 0, 462 0x044, 16, 8, 463 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | 464 CLK_IS_CRITICAL, 465 1); 466 467 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_AP_SYS_MAIN, clk_div_ap_sys_main, 468 clk_mpll0_parent, 0, 469 0x040, 16, 8, 470 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | 471 CLK_IS_CRITICAL, 472 1); 473 474 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_RP_SYS_FIXED, clk_div_rp_sys_fixed, 475 clk_fpll0_parent, 0, 476 0x050, 16, 8, 477 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | 478 CLK_IS_CRITICAL, 479 1); 480 481 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_RP_SYS_MAIN, clk_div_rp_sys_main, 482 clk_mpll1_parent, 0, 483 0x04c, 16, 8, 484 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | 485 CLK_IS_CRITICAL, 486 1); 487 488 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_TPU_SYS_FIXED, clk_div_tpu_sys_fixed, 489 clk_fpll0_parent, 0, 490 0x058, 16, 8, 491 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | 492 CLK_IS_CRITICAL, 493 2); 494 495 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_TPU_SYS_MAIN, clk_div_tpu_sys_main, 496 clk_mpll2_parent, 0, 497 0x054, 16, 8, 498 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | 499 CLK_IS_CRITICAL, 500 1); 501 502 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_NOC_SYS_FIXED, clk_div_noc_sys_fixed, 503 clk_fpll0_parent, 0, 504 0x070, 16, 8, 505 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | 506 CLK_IS_CRITICAL, 507 1); 508 509 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_NOC_SYS_MAIN, clk_div_noc_sys_main, 510 clk_mpll3_parent, 0, 511 0x06c, 16, 8, 512 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | 513 CLK_IS_CRITICAL, 514 1); 515 516 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_VC_SRC0_FIXED, clk_div_vc_src0_fixed, 517 clk_fpll0_parent, 0, 518 0x078, 16, 8, 519 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | 520 CLK_IS_CRITICAL, 521 2); 522 523 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_VC_SRC0_MAIN, clk_div_vc_src0_main, 524 clk_mpll4_parent, 0, 525 0x074, 16, 8, 526 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | 527 CLK_IS_CRITICAL, 528 1); 529 530 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_VC_SRC1_FIXED, clk_div_vc_src1_fixed, 531 clk_fpll0_parent, 0, 532 0x080, 16, 8, 533 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | 534 CLK_IS_CRITICAL, 535 3); 536 537 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_VC_SRC1_MAIN, clk_div_vc_src1_main, 538 clk_mpll5_parent, 0, 539 0x07c, 16, 8, 540 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | 541 CLK_IS_CRITICAL, 542 1); 543 544 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_CXP_MAC_FIXED, clk_div_cxp_mac_fixed, 545 clk_fpll0_parent, 0, 546 0x088, 16, 8, 547 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | 548 CLK_IS_CRITICAL, 549 2); 550 551 static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_CXP_MAC_MAIN, clk_div_cxp_mac_main, 552 clk_fpll1_parent, 0, 553 0x084, 16, 8, 554 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | 555 CLK_IS_CRITICAL, 556 1); 557 558 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR0_FIXED, clk_div_ddr0_fixed, 559 clk_fpll0_parent, 0, 560 0x124, 16, 8, 561 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 562 2); 563 564 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR0_MAIN, clk_div_ddr0_main, 565 clk_dpll0_parent, 0, 566 0x120, 16, 8, 567 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 568 1); 569 570 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR1_FIXED, clk_div_ddr1_fixed, 571 clk_fpll0_parent, 0, 572 0x12c, 16, 8, 573 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 574 2); 575 576 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR1_MAIN, clk_div_ddr1_main, 577 clk_dpll1_parent, 0, 578 0x128, 16, 8, 579 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 580 1); 581 582 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR2_FIXED, clk_div_ddr2_fixed, 583 clk_fpll0_parent, 0, 584 0x134, 16, 8, 585 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 586 2); 587 588 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR2_MAIN, clk_div_ddr2_main, 589 clk_dpll2_parent, 0, 590 0x130, 16, 8, 591 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 592 1); 593 594 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR3_FIXED, clk_div_ddr3_fixed, 595 clk_fpll0_parent, 0, 596 0x13c, 16, 8, 597 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 598 2); 599 600 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR3_MAIN, clk_div_ddr3_main, 601 clk_dpll3_parent, 0, 602 0x138, 16, 8, 603 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 604 1); 605 606 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR4_FIXED, clk_div_ddr4_fixed, 607 clk_fpll0_parent, 0, 608 0x144, 16, 8, 609 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 610 2); 611 612 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR4_MAIN, clk_div_ddr4_main, 613 clk_dpll4_parent, 0, 614 0x140, 16, 8, 615 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 616 1); 617 618 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR5_FIXED, clk_div_ddr5_fixed, 619 clk_fpll0_parent, 0, 620 0x14c, 16, 8, 621 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 622 2); 623 624 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR5_MAIN, clk_div_ddr5_main, 625 clk_dpll5_parent, 0, 626 0x148, 16, 8, 627 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 628 1); 629 630 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR6_FIXED, clk_div_ddr6_fixed, 631 clk_fpll0_parent, 0, 632 0x154, 16, 8, 633 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 634 2); 635 636 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR6_MAIN, clk_div_ddr6_main, 637 clk_dpll6_parent, 0, 638 0x150, 16, 8, 639 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 640 1); 641 642 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR7_FIXED, clk_div_ddr7_fixed, 643 clk_fpll0_parent, 0, 644 0x15c, 16, 8, 645 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 646 2); 647 648 static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR7_MAIN, clk_div_ddr7_main, 649 clk_dpll7_parent, 0, 650 0x158, 16, 8, 651 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 652 1); 653 654 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_TOP_50M, clk_div_top_50m, 655 clk_fpll0_parent, 0, 656 0x048, 16, 8, 657 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 658 40); 659 660 static const struct clk_hw *clk_div_top_50m_parent[] = { 661 &clk_div_top_50m.common.hw, 662 }; 663 664 static DEFINE_SG2044_DIV_RO(CLK_DIV_TOP_AXI0, clk_div_top_axi0, 665 clk_fpll0_parent, 0, 666 0x118, 16, 8, 667 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 668 20); 669 670 static const struct clk_hw *clk_div_top_axi0_parent[] = { 671 &clk_div_top_axi0.common.hw, 672 }; 673 674 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_TOP_AXI_HSPERI, clk_div_top_axi_hsperi, 675 clk_fpll0_parent, 0, 676 0x11c, 16, 8, 677 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 678 8); 679 680 static const struct clk_hw *clk_div_top_axi_hsperi_parent[] = { 681 &clk_div_top_axi_hsperi.common.hw, 682 }; 683 684 static DEFINE_SG2044_DIV(CLK_DIV_TIMER0, clk_div_timer0, 685 clk_div_top_50m_parent, 0, 686 0x0d0, 16, 16, 687 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 688 1); 689 690 static DEFINE_SG2044_DIV(CLK_DIV_TIMER1, clk_div_timer1, 691 clk_div_top_50m_parent, 0, 692 0x0d4, 16, 16, 693 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 694 1); 695 696 static DEFINE_SG2044_DIV(CLK_DIV_TIMER2, clk_div_timer2, 697 clk_div_top_50m_parent, 0, 698 0x0d8, 16, 16, 699 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 700 1); 701 702 static DEFINE_SG2044_DIV(CLK_DIV_TIMER3, clk_div_timer3, 703 clk_div_top_50m_parent, 0, 704 0x0dc, 16, 16, 705 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 706 1); 707 708 static DEFINE_SG2044_DIV(CLK_DIV_TIMER4, clk_div_timer4, 709 clk_div_top_50m_parent, 0, 710 0x0e0, 16, 16, 711 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 712 1); 713 714 static DEFINE_SG2044_DIV(CLK_DIV_TIMER5, clk_div_timer5, 715 clk_div_top_50m_parent, 0, 716 0x0e4, 16, 16, 717 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 718 1); 719 720 static DEFINE_SG2044_DIV(CLK_DIV_TIMER6, clk_div_timer6, 721 clk_div_top_50m_parent, 0, 722 0x0e8, 16, 16, 723 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 724 1); 725 726 static DEFINE_SG2044_DIV(CLK_DIV_TIMER7, clk_div_timer7, 727 clk_div_top_50m_parent, 0, 728 0x0ec, 16, 16, 729 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 730 1); 731 732 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_CXP_TEST_PHY, clk_div_cxp_test_phy, 733 clk_fpll0_parent, 0, 734 0x064, 16, 8, 735 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 736 1); 737 738 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_CXP_TEST_ETH_PHY, clk_div_cxp_test_eth_phy, 739 clk_fpll2_parent, 0, 740 0x068, 16, 8, 741 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 742 1); 743 744 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_C2C0_TEST_PHY, clk_div_c2c0_test_phy, 745 clk_fpll0_parent, 0, 746 0x05c, 16, 8, 747 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 748 1); 749 750 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_C2C1_TEST_PHY, clk_div_c2c1_test_phy, 751 clk_fpll0_parent, 0, 752 0x060, 16, 8, 753 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 754 1); 755 756 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_PCIE_1G, clk_div_pcie_1g, 757 clk_fpll1_parent, 0, 758 0x160, 16, 8, 759 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 760 1); 761 762 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_UART_500M, clk_div_uart_500m, 763 clk_fpll0_parent, 0, 764 0x0cc, 16, 8, 765 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 766 4); 767 768 static DEFINE_SG2044_DIV(CLK_DIV_GPIO_DB, clk_div_gpio_db, 769 clk_div_top_axi0_parent, 0, 770 0x0f8, 16, 16, 771 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 772 1000); 773 774 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_SD, clk_div_sd, 775 clk_fpll0_parent, 0, 776 0x110, 16, 16, 777 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 778 5); 779 780 static DEFINE_SG2044_DIV(CLK_DIV_SD_100K, clk_div_sd_100k, 781 clk_div_top_axi0_parent, 0, 782 0x114, 16, 16, 783 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 784 1000); 785 786 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_EMMC, clk_div_emmc, 787 clk_fpll0_parent, 0, 788 0x108, 16, 16, 789 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 790 5); 791 792 static DEFINE_SG2044_DIV(CLK_DIV_EMMC_100K, clk_div_emmc_100k, 793 clk_div_top_axi0_parent, 0, 794 0x10c, 16, 16, 795 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 796 1000); 797 798 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_EFUSE, clk_div_efuse, 799 clk_fpll0_parent, 0, 800 0x0f4, 16, 8, 801 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 802 80); 803 804 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_TX_ETH0, clk_div_tx_eth0, 805 clk_fpll0_parent, 0, 806 0x0fc, 16, 8, 807 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 808 16); 809 810 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_PTP_REF_I_ETH0, clk_div_ptp_ref_i_eth0, 811 clk_fpll0_parent, 0, 812 0x100, 16, 8, 813 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 814 40); 815 816 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_REF_ETH0, clk_div_ref_eth0, 817 clk_fpll0_parent, 0, 818 0x104, 16, 8, 819 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 820 80); 821 822 static DEFINE_SG2044_DIV_PDATA(CLK_DIV_PKA, clk_div_pka, 823 clk_fpll0_parent, 0, 824 0x0f0, 16, 8, 825 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 826 2); 827 828 static const struct clk_parent_data clk_mux_ddr0_parents[] = { 829 { .hw = &clk_div_ddr0_fixed.common.hw }, 830 { .hw = &clk_div_ddr0_main.common.hw }, 831 }; 832 833 static DEFINE_SG2044_MUX(CLK_MUX_DDR0, clk_mux_ddr0, 834 clk_mux_ddr0_parents, 835 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 836 0x020, 7, sg2044_mux_table, CLK_MUX_READ_ONLY); 837 838 static const struct clk_parent_data clk_mux_ddr1_parents[] = { 839 { .hw = &clk_div_ddr1_fixed.common.hw }, 840 { .hw = &clk_div_ddr1_main.common.hw }, 841 }; 842 843 static DEFINE_SG2044_MUX(CLK_MUX_DDR1, clk_mux_ddr1, 844 clk_mux_ddr1_parents, 845 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 846 0x020, 8, sg2044_mux_table, CLK_MUX_READ_ONLY); 847 848 static const struct clk_parent_data clk_mux_ddr2_parents[] = { 849 { .hw = &clk_div_ddr2_fixed.common.hw }, 850 { .hw = &clk_div_ddr2_main.common.hw }, 851 }; 852 853 static DEFINE_SG2044_MUX(CLK_MUX_DDR2, clk_mux_ddr2, 854 clk_mux_ddr2_parents, 855 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 856 0x020, 9, sg2044_mux_table, CLK_MUX_READ_ONLY); 857 858 static const struct clk_parent_data clk_mux_ddr3_parents[] = { 859 { .hw = &clk_div_ddr3_fixed.common.hw }, 860 { .hw = &clk_div_ddr3_main.common.hw }, 861 }; 862 863 static DEFINE_SG2044_MUX(CLK_MUX_DDR3, clk_mux_ddr3, 864 clk_mux_ddr3_parents, 865 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 866 0x020, 10, sg2044_mux_table, CLK_MUX_READ_ONLY); 867 868 static const struct clk_parent_data clk_mux_ddr4_parents[] = { 869 { .hw = &clk_div_ddr4_fixed.common.hw }, 870 { .hw = &clk_div_ddr4_main.common.hw }, 871 }; 872 873 static DEFINE_SG2044_MUX(CLK_MUX_DDR4, clk_mux_ddr4, 874 clk_mux_ddr4_parents, 875 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 876 0x020, 11, sg2044_mux_table, CLK_MUX_READ_ONLY); 877 878 static const struct clk_parent_data clk_mux_ddr5_parents[] = { 879 { .hw = &clk_div_ddr5_fixed.common.hw }, 880 { .hw = &clk_div_ddr5_main.common.hw }, 881 }; 882 883 static DEFINE_SG2044_MUX(CLK_MUX_DDR5, clk_mux_ddr5, 884 clk_mux_ddr5_parents, 885 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 886 0x020, 12, sg2044_mux_table, CLK_MUX_READ_ONLY); 887 888 static const struct clk_parent_data clk_mux_ddr6_parents[] = { 889 { .hw = &clk_div_ddr6_fixed.common.hw }, 890 { .hw = &clk_div_ddr6_main.common.hw }, 891 }; 892 893 static DEFINE_SG2044_MUX(CLK_MUX_DDR6, clk_mux_ddr6, 894 clk_mux_ddr6_parents, 895 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 896 0x020, 13, sg2044_mux_table, CLK_MUX_READ_ONLY); 897 898 static const struct clk_parent_data clk_mux_ddr7_parents[] = { 899 { .hw = &clk_div_ddr7_fixed.common.hw }, 900 { .hw = &clk_div_ddr7_main.common.hw }, 901 }; 902 903 static DEFINE_SG2044_MUX(CLK_MUX_DDR7, clk_mux_ddr7, 904 clk_mux_ddr7_parents, 905 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 906 0x020, 14, sg2044_mux_table, CLK_MUX_READ_ONLY); 907 908 static const struct clk_parent_data clk_mux_noc_sys_parents[] = { 909 { .hw = &clk_div_noc_sys_fixed.common.hw }, 910 { .hw = &clk_div_noc_sys_main.common.hw }, 911 }; 912 913 static DEFINE_SG2044_MUX(CLK_MUX_NOC_SYS, clk_mux_noc_sys, 914 clk_mux_noc_sys_parents, 915 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 916 0x020, 3, sg2044_mux_table, 0); 917 918 static const struct clk_parent_data clk_mux_tpu_sys_parents[] = { 919 { .hw = &clk_div_tpu_sys_fixed.common.hw }, 920 { .hw = &clk_div_tpu_sys_main.common.hw }, 921 }; 922 923 static DEFINE_SG2044_MUX(CLK_MUX_TPU_SYS, clk_mux_tpu_sys, 924 clk_mux_tpu_sys_parents, 925 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 926 0x020, 2, sg2044_mux_table, 0); 927 928 static const struct clk_parent_data clk_mux_rp_sys_parents[] = { 929 { .hw = &clk_div_rp_sys_fixed.common.hw }, 930 { .hw = &clk_div_rp_sys_main.common.hw }, 931 }; 932 933 static DEFINE_SG2044_MUX(CLK_MUX_RP_SYS, clk_mux_rp_sys, 934 clk_mux_rp_sys_parents, 935 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 936 0x020, 1, sg2044_mux_table, 0); 937 938 static const struct clk_parent_data clk_mux_ap_sys_parents[] = { 939 { .hw = &clk_div_ap_sys_fixed.common.hw }, 940 { .hw = &clk_div_ap_sys_main.common.hw }, 941 }; 942 943 static DEFINE_SG2044_MUX(CLK_MUX_AP_SYS, clk_mux_ap_sys, 944 clk_mux_ap_sys_parents, 945 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 946 0x020, 0, sg2044_mux_table, 0); 947 948 static const struct clk_parent_data clk_mux_vc_src0_parents[] = { 949 { .hw = &clk_div_vc_src0_fixed.common.hw }, 950 { .hw = &clk_div_vc_src0_main.common.hw }, 951 }; 952 953 static DEFINE_SG2044_MUX(CLK_MUX_VC_SRC0, clk_mux_vc_src0, 954 clk_mux_vc_src0_parents, 955 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 956 0x020, 4, sg2044_mux_table, 0); 957 958 static const struct clk_parent_data clk_mux_vc_src1_parents[] = { 959 { .hw = &clk_div_vc_src1_fixed.common.hw }, 960 { .hw = &clk_div_vc_src1_main.common.hw }, 961 }; 962 963 static DEFINE_SG2044_MUX(CLK_MUX_VC_SRC1, clk_mux_vc_src1, 964 clk_mux_vc_src1_parents, 965 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 966 0x020, 5, sg2044_mux_table, 0); 967 968 static const struct clk_parent_data clk_mux_cxp_mac_parents[] = { 969 { .hw = &clk_div_cxp_mac_fixed.common.hw }, 970 { .hw = &clk_div_cxp_mac_main.common.hw }, 971 }; 972 973 static DEFINE_SG2044_MUX(CLK_MUX_CXP_MAC, clk_mux_cxp_mac, 974 clk_mux_cxp_mac_parents, 975 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 976 0x020, 6, sg2044_mux_table, 0); 977 978 static const struct clk_hw *clk_gate_ap_sys_parent[] = { 979 &clk_mux_ap_sys.common.hw, 980 }; 981 982 static DEFINE_SG2044_GATE(CLK_GATE_AP_SYS, clk_gate_ap_sys, 983 clk_gate_ap_sys_parent, 984 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 985 0x000, 0, 0); 986 987 static const struct clk_hw *clk_gate_rp_sys_parent[] = { 988 &clk_mux_rp_sys.common.hw, 989 }; 990 991 static DEFINE_SG2044_GATE(CLK_GATE_RP_SYS, clk_gate_rp_sys, 992 clk_gate_rp_sys_parent, 993 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 994 0x000, 2, 0); 995 996 static const struct clk_hw *clk_gate_tpu_sys_parent[] = { 997 &clk_mux_tpu_sys.common.hw, 998 }; 999 1000 static DEFINE_SG2044_GATE(CLK_GATE_TPU_SYS, clk_gate_tpu_sys, 1001 clk_gate_tpu_sys_parent, 1002 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1003 0x000, 3, 0); 1004 1005 static const struct clk_hw *clk_gate_noc_sys_parent[] = { 1006 &clk_mux_noc_sys.common.hw, 1007 }; 1008 1009 static DEFINE_SG2044_GATE(CLK_GATE_NOC_SYS, clk_gate_noc_sys, 1010 clk_gate_noc_sys_parent, 1011 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1012 0x000, 8, 0); 1013 1014 static const struct clk_hw *clk_gate_vc_src0_parent[] = { 1015 &clk_mux_vc_src0.common.hw, 1016 }; 1017 1018 static DEFINE_SG2044_GATE(CLK_GATE_VC_SRC0, clk_gate_vc_src0, 1019 clk_gate_vc_src0_parent, 1020 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1021 0x000, 9, 0); 1022 1023 static const struct clk_hw *clk_gate_vc_src1_parent[] = { 1024 &clk_mux_vc_src1.common.hw, 1025 }; 1026 1027 static DEFINE_SG2044_GATE(CLK_GATE_VC_SRC1, clk_gate_vc_src1, 1028 clk_gate_vc_src1_parent, 1029 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1030 0x000, 10, 0); 1031 1032 static const struct clk_hw *clk_gate_ddr0_parent[] = { 1033 &clk_mux_ddr0.common.hw, 1034 }; 1035 1036 static DEFINE_SG2044_GATE(CLK_GATE_DDR0, clk_gate_ddr0, 1037 clk_gate_ddr0_parent, 1038 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1039 0x008, 7, 0); 1040 1041 static const struct clk_hw *clk_gate_ddr1_parent[] = { 1042 &clk_mux_ddr1.common.hw, 1043 }; 1044 1045 static DEFINE_SG2044_GATE(CLK_GATE_DDR1, clk_gate_ddr1, 1046 clk_gate_ddr1_parent, 1047 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1048 0x008, 8, 0); 1049 1050 static const struct clk_hw *clk_gate_ddr2_parent[] = { 1051 &clk_mux_ddr2.common.hw, 1052 }; 1053 1054 static DEFINE_SG2044_GATE(CLK_GATE_DDR2, clk_gate_ddr2, 1055 clk_gate_ddr2_parent, 1056 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1057 0x008, 9, 0); 1058 1059 static const struct clk_hw *clk_gate_ddr3_parent[] = { 1060 &clk_mux_ddr3.common.hw, 1061 }; 1062 1063 static DEFINE_SG2044_GATE(CLK_GATE_DDR3, clk_gate_ddr3, 1064 clk_gate_ddr3_parent, 1065 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1066 0x008, 10, 0); 1067 1068 static const struct clk_hw *clk_gate_ddr4_parent[] = { 1069 &clk_mux_ddr4.common.hw, 1070 }; 1071 1072 static DEFINE_SG2044_GATE(CLK_GATE_DDR4, clk_gate_ddr4, 1073 clk_gate_ddr4_parent, 1074 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1075 0x008, 11, 0); 1076 1077 static const struct clk_hw *clk_gate_ddr5_parent[] = { 1078 &clk_mux_ddr5.common.hw, 1079 }; 1080 1081 static DEFINE_SG2044_GATE(CLK_GATE_DDR5, clk_gate_ddr5, 1082 clk_gate_ddr5_parent, 1083 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1084 0x008, 12, 0); 1085 1086 static const struct clk_hw *clk_gate_ddr6_parent[] = { 1087 &clk_mux_ddr6.common.hw, 1088 }; 1089 1090 static DEFINE_SG2044_GATE(CLK_GATE_DDR6, clk_gate_ddr6, 1091 clk_gate_ddr6_parent, 1092 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1093 0x008, 13, 0); 1094 1095 static const struct clk_hw *clk_gate_ddr7_parent[] = { 1096 &clk_mux_ddr7.common.hw, 1097 }; 1098 1099 static DEFINE_SG2044_GATE(CLK_GATE_DDR7, clk_gate_ddr7, 1100 clk_gate_ddr7_parent, 1101 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1102 0x008, 14, 0); 1103 1104 static const struct clk_hw *clk_gate_top_50m_parent[] = { 1105 &clk_div_top_50m.common.hw, 1106 }; 1107 1108 static DEFINE_SG2044_GATE(CLK_GATE_TOP_50M, clk_gate_top_50m, 1109 clk_gate_top_50m_parent, 1110 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1111 0x000, 1, 0); 1112 1113 static const struct clk_hw *clk_gate_sc_rx_parent[] = { 1114 &clk_div_top_50m.common.hw, 1115 }; 1116 1117 static DEFINE_SG2044_GATE(CLK_GATE_SC_RX, clk_gate_sc_rx, 1118 clk_gate_sc_rx_parent, 1119 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1120 0x000, 12, 0); 1121 1122 static const struct clk_hw *clk_gate_sc_rx_x0y1_parent[] = { 1123 &clk_div_top_50m.common.hw, 1124 }; 1125 1126 static DEFINE_SG2044_GATE(CLK_GATE_SC_RX_X0Y1, clk_gate_sc_rx_x0y1, 1127 clk_gate_sc_rx_x0y1_parent, 1128 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1129 0x000, 13, 0); 1130 1131 static DEFINE_SG2044_GATE(CLK_GATE_TOP_AXI0, clk_gate_top_axi0, 1132 clk_div_top_axi0_parent, 1133 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1134 0x008, 5, 0); 1135 1136 static const struct clk_hw *clk_gate_mailbox_intc_parent[] = { 1137 &clk_gate_top_axi0.common.hw, 1138 }; 1139 1140 static DEFINE_SG2044_GATE(CLK_GATE_INTC0, clk_gate_intc0, 1141 clk_gate_mailbox_intc_parent, 1142 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1143 0x020, 20, 0); 1144 1145 static DEFINE_SG2044_GATE(CLK_GATE_INTC1, clk_gate_intc1, 1146 clk_gate_mailbox_intc_parent, 1147 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1148 0x020, 21, 0); 1149 1150 static DEFINE_SG2044_GATE(CLK_GATE_INTC2, clk_gate_intc2, 1151 clk_gate_mailbox_intc_parent, 1152 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1153 0x020, 22, 0); 1154 1155 static DEFINE_SG2044_GATE(CLK_GATE_INTC3, clk_gate_intc3, 1156 clk_gate_mailbox_intc_parent, 1157 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1158 0x020, 23, 0); 1159 1160 static DEFINE_SG2044_GATE(CLK_GATE_MAILBOX0, clk_gate_mailbox0, 1161 clk_gate_mailbox_intc_parent, 1162 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1163 0x020, 16, 0); 1164 1165 static DEFINE_SG2044_GATE(CLK_GATE_MAILBOX1, clk_gate_mailbox1, 1166 clk_gate_mailbox_intc_parent, 1167 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1168 0x020, 17, 0); 1169 1170 static DEFINE_SG2044_GATE(CLK_GATE_MAILBOX2, clk_gate_mailbox2, 1171 clk_gate_mailbox_intc_parent, 1172 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1173 0x020, 18, 0); 1174 1175 static DEFINE_SG2044_GATE(CLK_GATE_MAILBOX3, clk_gate_mailbox3, 1176 clk_gate_mailbox_intc_parent, 1177 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1178 0x020, 19, 0); 1179 1180 static DEFINE_SG2044_GATE(CLK_GATE_TOP_AXI_HSPERI, clk_gate_top_axi_hsperi, 1181 clk_div_top_axi_hsperi_parent, 1182 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1183 0x008, 6, 0); 1184 1185 static DEFINE_SG2044_GATE(CLK_GATE_APB_TIMER, clk_gate_apb_timer, 1186 clk_div_top_axi0_parent, 1187 CLK_SET_RATE_PARENT, 1188 0x004, 7, 0); 1189 1190 static const struct clk_hw *clk_gate_timer0_parent[] = { 1191 &clk_div_timer0.common.hw, 1192 }; 1193 1194 static DEFINE_SG2044_GATE(CLK_GATE_TIMER0, clk_gate_timer0, 1195 clk_gate_timer0_parent, 1196 CLK_SET_RATE_PARENT, 1197 0x004, 8, 0); 1198 1199 static const struct clk_hw *clk_gate_timer1_parent[] = { 1200 &clk_div_timer1.common.hw, 1201 }; 1202 1203 static DEFINE_SG2044_GATE(CLK_GATE_TIMER1, clk_gate_timer1, 1204 clk_gate_timer1_parent, 1205 CLK_SET_RATE_PARENT, 1206 0x004, 9, 0); 1207 1208 static const struct clk_hw *clk_gate_timer2_parent[] = { 1209 &clk_div_timer2.common.hw, 1210 }; 1211 1212 static DEFINE_SG2044_GATE(CLK_GATE_TIMER2, clk_gate_timer2, 1213 clk_gate_timer2_parent, 1214 CLK_SET_RATE_PARENT, 1215 0x004, 10, 0); 1216 1217 static const struct clk_hw *clk_gate_timer3_parent[] = { 1218 &clk_div_timer3.common.hw, 1219 }; 1220 1221 static DEFINE_SG2044_GATE(CLK_GATE_TIMER3, clk_gate_timer3, 1222 clk_gate_timer3_parent, 1223 CLK_SET_RATE_PARENT, 1224 0x004, 11, 0); 1225 1226 static const struct clk_hw *clk_gate_timer4_parent[] = { 1227 &clk_div_timer4.common.hw, 1228 }; 1229 1230 static DEFINE_SG2044_GATE(CLK_GATE_TIMER4, clk_gate_timer4, 1231 clk_gate_timer4_parent, 1232 CLK_SET_RATE_PARENT, 1233 0x004, 12, 0); 1234 1235 static const struct clk_hw *clk_gate_timer5_parent[] = { 1236 &clk_div_timer5.common.hw, 1237 }; 1238 1239 static DEFINE_SG2044_GATE(CLK_GATE_TIMER5, clk_gate_timer5, 1240 clk_gate_timer5_parent, 1241 CLK_SET_RATE_PARENT, 1242 0x004, 13, 0); 1243 1244 static const struct clk_hw *clk_gate_timer6_parent[] = { 1245 &clk_div_timer6.common.hw, 1246 }; 1247 1248 static DEFINE_SG2044_GATE(CLK_GATE_TIMER6, clk_gate_timer6, 1249 clk_gate_timer6_parent, 1250 CLK_SET_RATE_PARENT, 1251 0x004, 14, 0); 1252 1253 static const struct clk_hw *clk_gate_timer7_parent[] = { 1254 &clk_div_timer7.common.hw, 1255 }; 1256 1257 static DEFINE_SG2044_GATE(CLK_GATE_TIMER7, clk_gate_timer7, 1258 clk_gate_timer7_parent, 1259 CLK_SET_RATE_PARENT, 1260 0x004, 15, 0); 1261 1262 static DEFINE_SG2044_GATE(CLK_GATE_CXP_CFG, clk_gate_cxp_cfg, 1263 clk_div_top_axi0_parent, 1264 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1265 0x000, 15, 0); 1266 1267 static const struct clk_hw *clk_gate_cxp_mac_parent[] = { 1268 &clk_mux_cxp_mac.common.hw, 1269 }; 1270 1271 static DEFINE_SG2044_GATE(CLK_GATE_CXP_MAC, clk_gate_cxp_mac, 1272 clk_gate_cxp_mac_parent, 1273 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1274 0x000, 14, 0); 1275 1276 static const struct clk_hw *clk_gate_cxp_test_phy_parent[] = { 1277 &clk_div_cxp_test_phy.common.hw, 1278 }; 1279 1280 static DEFINE_SG2044_GATE(CLK_GATE_CXP_TEST_PHY, clk_gate_cxp_test_phy, 1281 clk_gate_cxp_test_phy_parent, 1282 CLK_SET_RATE_PARENT, 1283 0x000, 6, 0); 1284 1285 static const struct clk_hw *clk_gate_cxp_test_eth_phy_parent[] = { 1286 &clk_div_cxp_test_eth_phy.common.hw, 1287 }; 1288 1289 static DEFINE_SG2044_GATE(CLK_GATE_CXP_TEST_ETH_PHY, clk_gate_cxp_test_eth_phy, 1290 clk_gate_cxp_test_eth_phy_parent, 1291 CLK_SET_RATE_PARENT, 1292 0x000, 7, 0); 1293 1294 static const struct clk_hw *clk_gate_pcie_1g_parent[] = { 1295 &clk_div_pcie_1g.common.hw, 1296 }; 1297 1298 static DEFINE_SG2044_GATE(CLK_GATE_PCIE_1G, clk_gate_pcie_1g, 1299 clk_gate_pcie_1g_parent, 1300 CLK_SET_RATE_PARENT, 1301 0x008, 15, 0); 1302 1303 static const struct clk_hw *clk_gate_c2c0_test_phy_parent[] = { 1304 &clk_div_c2c0_test_phy.common.hw, 1305 }; 1306 1307 static DEFINE_SG2044_GATE(CLK_GATE_C2C0_TEST_PHY, clk_gate_c2c0_test_phy, 1308 clk_gate_c2c0_test_phy_parent, 1309 CLK_SET_RATE_PARENT, 1310 0x000, 4, 0); 1311 1312 static const struct clk_hw *clk_gate_c2c1_test_phy_parent[] = { 1313 &clk_div_c2c1_test_phy.common.hw, 1314 }; 1315 1316 static DEFINE_SG2044_GATE(CLK_GATE_C2C1_TEST_PHY, clk_gate_c2c1_test_phy, 1317 clk_gate_c2c1_test_phy_parent, 1318 CLK_SET_RATE_PARENT, 1319 0x000, 5, 0); 1320 1321 static const struct clk_hw *clk_gate_uart_500m_parent[] = { 1322 &clk_div_uart_500m.common.hw, 1323 }; 1324 1325 static DEFINE_SG2044_GATE(CLK_GATE_UART_500M, clk_gate_uart_500m, 1326 clk_gate_uart_500m_parent, 1327 CLK_SET_RATE_PARENT, 1328 0x004, 1, 0); 1329 1330 static DEFINE_SG2044_GATE(CLK_GATE_APB_UART, clk_gate_apb_uart, 1331 clk_div_top_axi_hsperi_parent, 1332 CLK_SET_RATE_PARENT, 1333 0x004, 2, 0); 1334 1335 static DEFINE_SG2044_GATE(CLK_GATE_APB_SPI, clk_gate_apb_spi, 1336 clk_div_top_axi_hsperi_parent, 1337 CLK_SET_RATE_PARENT, 1338 0x004, 22, 0); 1339 1340 static DEFINE_SG2044_GATE(CLK_GATE_AHB_SPIFMC, clk_gate_ahb_spifmc, 1341 clk_div_top_axi0_parent, 1342 CLK_SET_RATE_PARENT, 1343 0x004, 5, 0); 1344 1345 static DEFINE_SG2044_GATE(CLK_GATE_APB_I2C, clk_gate_apb_i2c, 1346 clk_div_top_axi0_parent, 1347 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1348 0x004, 23, 0); 1349 1350 static DEFINE_SG2044_GATE(CLK_GATE_AXI_DBG_I2C, clk_gate_axi_dbg_i2c, 1351 clk_div_top_axi_hsperi_parent, 1352 CLK_SET_RATE_PARENT, 1353 0x004, 3, 0); 1354 1355 static const struct clk_hw *clk_gate_gpio_db_parent[] = { 1356 &clk_div_gpio_db.common.hw, 1357 }; 1358 1359 static DEFINE_SG2044_GATE(CLK_GATE_GPIO_DB, clk_gate_gpio_db, 1360 clk_gate_gpio_db_parent, 1361 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1362 0x004, 21, 0); 1363 1364 static DEFINE_SG2044_GATE(CLK_GATE_APB_GPIO_INTR, clk_gate_apb_gpio_intr, 1365 clk_div_top_axi0_parent, 1366 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1367 0x004, 20, 0); 1368 1369 static DEFINE_SG2044_GATE(CLK_GATE_APB_GPIO, clk_gate_apb_gpio, 1370 clk_div_top_axi0_parent, 1371 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1372 0x004, 19, 0); 1373 1374 static const struct clk_hw *clk_gate_sd_parent[] = { 1375 &clk_div_sd.common.hw, 1376 }; 1377 1378 static DEFINE_SG2044_GATE(CLK_GATE_SD, clk_gate_sd, 1379 clk_gate_sd_parent, 1380 CLK_SET_RATE_PARENT, 1381 0x008, 3, 0); 1382 1383 static DEFINE_SG2044_GATE(CLK_GATE_AXI_SD, clk_gate_axi_sd, 1384 clk_div_top_axi_hsperi_parent, 1385 CLK_SET_RATE_PARENT, 1386 0x008, 2, 0); 1387 1388 static const struct clk_hw *clk_gate_sd_100k_parent[] = { 1389 &clk_div_sd_100k.common.hw, 1390 }; 1391 1392 static DEFINE_SG2044_GATE(CLK_GATE_SD_100K, clk_gate_sd_100k, 1393 clk_gate_sd_100k_parent, 1394 CLK_SET_RATE_PARENT, 1395 0x008, 4, 0); 1396 1397 static const struct clk_hw *clk_gate_emmc_parent[] = { 1398 &clk_div_emmc.common.hw, 1399 }; 1400 1401 static DEFINE_SG2044_GATE(CLK_GATE_EMMC, clk_gate_emmc, 1402 clk_gate_emmc_parent, 1403 CLK_SET_RATE_PARENT, 1404 0x008, 0, 0); 1405 1406 static DEFINE_SG2044_GATE(CLK_GATE_AXI_EMMC, clk_gate_axi_emmc, 1407 clk_div_top_axi_hsperi_parent, 1408 CLK_SET_RATE_PARENT, 1409 0x004, 31, 0); 1410 1411 static const struct clk_hw *clk_gate_emmc_100k_parent[] = { 1412 &clk_div_emmc_100k.common.hw, 1413 }; 1414 1415 static DEFINE_SG2044_GATE(CLK_GATE_EMMC_100K, clk_gate_emmc_100k, 1416 clk_gate_emmc_100k_parent, 1417 CLK_SET_RATE_PARENT, 1418 0x008, 1, 0); 1419 1420 static const struct clk_hw *clk_gate_efuse_parent[] = { 1421 &clk_div_efuse.common.hw, 1422 }; 1423 1424 static DEFINE_SG2044_GATE(CLK_GATE_EFUSE, clk_gate_efuse, 1425 clk_gate_efuse_parent, 1426 CLK_SET_RATE_PARENT, 1427 0x004, 17, 0); 1428 1429 static DEFINE_SG2044_GATE(CLK_GATE_APB_EFUSE, clk_gate_apb_efuse, 1430 clk_div_top_axi0_parent, 1431 CLK_SET_RATE_PARENT, 1432 0x004, 18, 0); 1433 1434 static DEFINE_SG2044_GATE(CLK_GATE_SYSDMA_AXI, clk_gate_sysdma_axi, 1435 clk_div_top_axi_hsperi_parent, 1436 CLK_SET_RATE_PARENT, 1437 0x004, 0, 0); 1438 1439 static const struct clk_hw *clk_gate_tx_eth0_parent[] = { 1440 &clk_div_tx_eth0.common.hw, 1441 }; 1442 1443 static DEFINE_SG2044_GATE(CLK_GATE_TX_ETH0, clk_gate_tx_eth0, 1444 clk_gate_tx_eth0_parent, 1445 CLK_SET_RATE_PARENT, 1446 0x004, 27, 0); 1447 1448 static DEFINE_SG2044_GATE(CLK_GATE_AXI_ETH0, clk_gate_axi_eth0, 1449 clk_div_top_axi_hsperi_parent, 1450 CLK_SET_RATE_PARENT, 1451 0x004, 28, 0); 1452 1453 static const struct clk_hw *clk_gate_ptp_ref_i_eth0_parent[] = { 1454 &clk_div_ptp_ref_i_eth0.common.hw, 1455 }; 1456 1457 static DEFINE_SG2044_GATE(CLK_GATE_PTP_REF_I_ETH0, clk_gate_ptp_ref_i_eth0, 1458 clk_gate_ptp_ref_i_eth0_parent, 1459 CLK_SET_RATE_PARENT, 1460 0x004, 29, 0); 1461 1462 static const struct clk_hw *clk_gate_ref_eth0_parent[] = { 1463 &clk_div_ref_eth0.common.hw, 1464 }; 1465 1466 static DEFINE_SG2044_GATE(CLK_GATE_REF_ETH0, clk_gate_ref_eth0, 1467 clk_gate_ref_eth0_parent, 1468 CLK_SET_RATE_PARENT, 1469 0x004, 30, 0); 1470 1471 static DEFINE_SG2044_GATE(CLK_GATE_APB_RTC, clk_gate_apb_rtc, 1472 clk_div_top_axi0_parent, 1473 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1474 0x004, 26, 0); 1475 1476 static DEFINE_SG2044_GATE(CLK_GATE_APB_PWM, clk_gate_apb_pwm, 1477 clk_div_top_axi0_parent, 1478 CLK_SET_RATE_PARENT, 1479 0x004, 25, 0); 1480 1481 static DEFINE_SG2044_GATE(CLK_GATE_APB_WDT, clk_gate_apb_wdt, 1482 clk_div_top_axi0_parent, 1483 CLK_SET_RATE_PARENT, 1484 0x004, 24, 0); 1485 1486 static DEFINE_SG2044_GATE(CLK_GATE_AXI_SRAM, clk_gate_axi_sram, 1487 clk_div_top_axi0_parent, 1488 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1489 0x004, 6, 0); 1490 1491 static DEFINE_SG2044_GATE(CLK_GATE_AHB_ROM, clk_gate_ahb_rom, 1492 clk_div_top_axi0_parent, 1493 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 1494 0x004, 4, 0); 1495 1496 static const struct clk_hw *clk_gate_pka_parent[] = { 1497 &clk_div_pka.common.hw, 1498 }; 1499 1500 static DEFINE_SG2044_GATE(CLK_GATE_PKA, clk_gate_pka, 1501 clk_gate_pka_parent, 1502 CLK_SET_RATE_PARENT, 1503 0x004, 16, 0); 1504 1505 static struct sg2044_clk_common * const sg2044_div_commons[] = { 1506 &clk_div_ap_sys_fixed.common, 1507 &clk_div_ap_sys_main.common, 1508 &clk_div_rp_sys_fixed.common, 1509 &clk_div_rp_sys_main.common, 1510 &clk_div_tpu_sys_fixed.common, 1511 &clk_div_tpu_sys_main.common, 1512 &clk_div_noc_sys_fixed.common, 1513 &clk_div_noc_sys_main.common, 1514 &clk_div_vc_src0_fixed.common, 1515 &clk_div_vc_src0_main.common, 1516 &clk_div_vc_src1_fixed.common, 1517 &clk_div_vc_src1_main.common, 1518 &clk_div_cxp_mac_fixed.common, 1519 &clk_div_cxp_mac_main.common, 1520 &clk_div_ddr0_fixed.common, 1521 &clk_div_ddr0_main.common, 1522 &clk_div_ddr1_fixed.common, 1523 &clk_div_ddr1_main.common, 1524 &clk_div_ddr2_fixed.common, 1525 &clk_div_ddr2_main.common, 1526 &clk_div_ddr3_fixed.common, 1527 &clk_div_ddr3_main.common, 1528 &clk_div_ddr4_fixed.common, 1529 &clk_div_ddr4_main.common, 1530 &clk_div_ddr5_fixed.common, 1531 &clk_div_ddr5_main.common, 1532 &clk_div_ddr6_fixed.common, 1533 &clk_div_ddr6_main.common, 1534 &clk_div_ddr7_fixed.common, 1535 &clk_div_ddr7_main.common, 1536 &clk_div_top_50m.common, 1537 &clk_div_top_axi0.common, 1538 &clk_div_top_axi_hsperi.common, 1539 &clk_div_timer0.common, 1540 &clk_div_timer1.common, 1541 &clk_div_timer2.common, 1542 &clk_div_timer3.common, 1543 &clk_div_timer4.common, 1544 &clk_div_timer5.common, 1545 &clk_div_timer6.common, 1546 &clk_div_timer7.common, 1547 &clk_div_cxp_test_phy.common, 1548 &clk_div_cxp_test_eth_phy.common, 1549 &clk_div_c2c0_test_phy.common, 1550 &clk_div_c2c1_test_phy.common, 1551 &clk_div_pcie_1g.common, 1552 &clk_div_uart_500m.common, 1553 &clk_div_gpio_db.common, 1554 &clk_div_sd.common, 1555 &clk_div_sd_100k.common, 1556 &clk_div_emmc.common, 1557 &clk_div_emmc_100k.common, 1558 &clk_div_efuse.common, 1559 &clk_div_tx_eth0.common, 1560 &clk_div_ptp_ref_i_eth0.common, 1561 &clk_div_ref_eth0.common, 1562 &clk_div_pka.common, 1563 }; 1564 1565 static struct sg2044_clk_common * const sg2044_mux_commons[] = { 1566 &clk_mux_ddr0.common, 1567 &clk_mux_ddr1.common, 1568 &clk_mux_ddr2.common, 1569 &clk_mux_ddr3.common, 1570 &clk_mux_ddr4.common, 1571 &clk_mux_ddr5.common, 1572 &clk_mux_ddr6.common, 1573 &clk_mux_ddr7.common, 1574 &clk_mux_noc_sys.common, 1575 &clk_mux_tpu_sys.common, 1576 &clk_mux_rp_sys.common, 1577 &clk_mux_ap_sys.common, 1578 &clk_mux_vc_src0.common, 1579 &clk_mux_vc_src1.common, 1580 &clk_mux_cxp_mac.common, 1581 }; 1582 1583 static struct sg2044_clk_common * const sg2044_gate_commons[] = { 1584 &clk_gate_ap_sys.common, 1585 &clk_gate_rp_sys.common, 1586 &clk_gate_tpu_sys.common, 1587 &clk_gate_noc_sys.common, 1588 &clk_gate_vc_src0.common, 1589 &clk_gate_vc_src1.common, 1590 &clk_gate_ddr0.common, 1591 &clk_gate_ddr1.common, 1592 &clk_gate_ddr2.common, 1593 &clk_gate_ddr3.common, 1594 &clk_gate_ddr4.common, 1595 &clk_gate_ddr5.common, 1596 &clk_gate_ddr6.common, 1597 &clk_gate_ddr7.common, 1598 &clk_gate_top_50m.common, 1599 &clk_gate_sc_rx.common, 1600 &clk_gate_sc_rx_x0y1.common, 1601 &clk_gate_top_axi0.common, 1602 &clk_gate_intc0.common, 1603 &clk_gate_intc1.common, 1604 &clk_gate_intc2.common, 1605 &clk_gate_intc3.common, 1606 &clk_gate_mailbox0.common, 1607 &clk_gate_mailbox1.common, 1608 &clk_gate_mailbox2.common, 1609 &clk_gate_mailbox3.common, 1610 &clk_gate_top_axi_hsperi.common, 1611 &clk_gate_apb_timer.common, 1612 &clk_gate_timer0.common, 1613 &clk_gate_timer1.common, 1614 &clk_gate_timer2.common, 1615 &clk_gate_timer3.common, 1616 &clk_gate_timer4.common, 1617 &clk_gate_timer5.common, 1618 &clk_gate_timer6.common, 1619 &clk_gate_timer7.common, 1620 &clk_gate_cxp_cfg.common, 1621 &clk_gate_cxp_mac.common, 1622 &clk_gate_cxp_test_phy.common, 1623 &clk_gate_cxp_test_eth_phy.common, 1624 &clk_gate_pcie_1g.common, 1625 &clk_gate_c2c0_test_phy.common, 1626 &clk_gate_c2c1_test_phy.common, 1627 &clk_gate_uart_500m.common, 1628 &clk_gate_apb_uart.common, 1629 &clk_gate_apb_spi.common, 1630 &clk_gate_ahb_spifmc.common, 1631 &clk_gate_apb_i2c.common, 1632 &clk_gate_axi_dbg_i2c.common, 1633 &clk_gate_gpio_db.common, 1634 &clk_gate_apb_gpio_intr.common, 1635 &clk_gate_apb_gpio.common, 1636 &clk_gate_sd.common, 1637 &clk_gate_axi_sd.common, 1638 &clk_gate_sd_100k.common, 1639 &clk_gate_emmc.common, 1640 &clk_gate_axi_emmc.common, 1641 &clk_gate_emmc_100k.common, 1642 &clk_gate_efuse.common, 1643 &clk_gate_apb_efuse.common, 1644 &clk_gate_sysdma_axi.common, 1645 &clk_gate_tx_eth0.common, 1646 &clk_gate_axi_eth0.common, 1647 &clk_gate_ptp_ref_i_eth0.common, 1648 &clk_gate_ref_eth0.common, 1649 &clk_gate_apb_rtc.common, 1650 &clk_gate_apb_pwm.common, 1651 &clk_gate_apb_wdt.common, 1652 &clk_gate_axi_sram.common, 1653 &clk_gate_ahb_rom.common, 1654 &clk_gate_pka.common, 1655 }; 1656 1657 static void sg2044_clk_fix_init_parent(struct clk_hw **pdata, 1658 const struct clk_init_data *init, 1659 struct clk_hw_onecell_data *data) 1660 { 1661 u8 i; 1662 const struct clk_hw *hw; 1663 const struct sg2044_clk_common *common; 1664 1665 for (i = 0; i < init->num_parents; i++) { 1666 hw = init->parent_hws[i]; 1667 common = hw_to_sg2044_clk_common(hw); 1668 1669 WARN(!data->hws[common->id], "clk %u is not register\n", 1670 common->id); 1671 pdata[i] = data->hws[common->id]; 1672 } 1673 } 1674 1675 static int sg2044_clk_init_ctrl(struct device *dev, void __iomem *reg, 1676 struct sg2044_clk_ctrl *ctrl, 1677 const struct sg2044_clk_desc_data *desc) 1678 { 1679 int ret, i; 1680 struct clk_hw *hw; 1681 1682 spin_lock_init(&ctrl->lock); 1683 1684 for (i = 0; i < desc->num_div; i++) { 1685 struct sg2044_clk_common *common = desc->div[i]; 1686 1687 common->lock = &ctrl->lock; 1688 common->base = reg; 1689 1690 ret = devm_clk_hw_register(dev, &common->hw); 1691 if (ret) 1692 return ret; 1693 1694 ctrl->data.hws[common->id] = &common->hw; 1695 } 1696 1697 for (i = 0; i < desc->num_mux; i++) { 1698 struct sg2044_clk_common *common = desc->mux[i]; 1699 struct sg2044_mux *mux = hw_to_sg2044_mux(&common->hw); 1700 const struct clk_init_data *init = common->hw.init; 1701 1702 common->lock = &ctrl->lock; 1703 common->base = reg; 1704 1705 hw = devm_clk_hw_register_mux_parent_data_table(dev, 1706 init->name, 1707 init->parent_data, 1708 init->num_parents, 1709 init->flags, 1710 reg + mux->mux.offset, 1711 mux->mux.shift, 1712 1, 1713 mux->mux.flags, 1714 mux->mux.table, 1715 &ctrl->lock); 1716 if (IS_ERR(hw)) 1717 return PTR_ERR(hw); 1718 1719 if (!(mux->mux.flags & CLK_MUX_READ_ONLY)) { 1720 mux->nb.notifier_call = sg2044_mux_notifier_cb; 1721 ret = devm_clk_notifier_register(dev, hw->clk, 1722 &mux->nb); 1723 if (ret < 0) 1724 return dev_err_probe(dev, ret, 1725 "%s: failed to register notifier\n", 1726 clk_hw_get_name(hw)); 1727 } 1728 1729 ctrl->data.hws[common->id] = hw; 1730 } 1731 1732 for (i = 0; i < desc->num_gate; i++) { 1733 struct sg2044_clk_common *common = desc->gate[i]; 1734 struct sg2044_gate *gate = hw_to_sg2044_gate(&common->hw); 1735 const struct clk_init_data *init = common->hw.init; 1736 struct clk_hw *parent_hws[1] = { }; 1737 1738 sg2044_clk_fix_init_parent(parent_hws, init, &ctrl->data); 1739 common->lock = &ctrl->lock; 1740 common->base = reg; 1741 1742 hw = devm_clk_hw_register_gate_parent_hw(dev, init->name, 1743 parent_hws[0], 1744 init->flags, 1745 reg + gate->gate.offset, 1746 gate->gate.shift, 1747 gate->gate.flags, 1748 &ctrl->lock); 1749 if (IS_ERR(hw)) 1750 return PTR_ERR(hw); 1751 1752 ctrl->data.hws[common->id] = hw; 1753 } 1754 1755 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 1756 &ctrl->data); 1757 } 1758 1759 static int sg2044_clk_probe(struct platform_device *pdev) 1760 { 1761 struct device *dev = &pdev->dev; 1762 struct sg2044_clk_ctrl *ctrl; 1763 const struct sg2044_clk_desc_data *desc; 1764 void __iomem *reg; 1765 u32 num_clks; 1766 1767 reg = devm_platform_ioremap_resource(pdev, 0); 1768 if (IS_ERR(reg)) 1769 return PTR_ERR(reg); 1770 1771 desc = device_get_match_data(dev); 1772 if (!desc) 1773 return dev_err_probe(dev, -EINVAL, "no match data for platform\n"); 1774 1775 num_clks = desc->num_div + desc->num_gate + desc->num_mux; 1776 1777 ctrl = devm_kzalloc(dev, struct_size(ctrl, data.hws, num_clks), GFP_KERNEL); 1778 if (!ctrl) 1779 return -ENOMEM; 1780 1781 ctrl->data.num = num_clks; 1782 1783 return sg2044_clk_init_ctrl(dev, reg, ctrl, desc); 1784 } 1785 1786 static const struct sg2044_clk_desc_data sg2044_clk_desc_data = { 1787 .div = sg2044_div_commons, 1788 .mux = sg2044_mux_commons, 1789 .gate = sg2044_gate_commons, 1790 .num_div = ARRAY_SIZE(sg2044_div_commons), 1791 .num_mux = ARRAY_SIZE(sg2044_mux_commons), 1792 .num_gate = ARRAY_SIZE(sg2044_gate_commons), 1793 }; 1794 1795 static const struct of_device_id sg2044_clk_match[] = { 1796 { .compatible = "sophgo,sg2044-clk", .data = &sg2044_clk_desc_data }, 1797 { /* sentinel */ } 1798 }; 1799 MODULE_DEVICE_TABLE(of, sg2044_clk_match); 1800 1801 static struct platform_driver sg2044_clk_driver = { 1802 .probe = sg2044_clk_probe, 1803 .driver = { 1804 .name = "sg2044-clk", 1805 .of_match_table = sg2044_clk_match, 1806 }, 1807 }; 1808 module_platform_driver(sg2044_clk_driver); 1809 1810 MODULE_AUTHOR("Inochi Amaoto <inochiama@gmail.com>"); 1811 MODULE_DESCRIPTION("Sophgo SG2044 clock driver"); 1812 MODULE_LICENSE("GPL"); 1813