1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/of.h> 13 14 #include "clk.h" 15 #include <dt-bindings/clock/exynos7-clk.h> 16 17 /* Register Offset definitions for CMU_TOPC (0x10570000) */ 18 #define CC_PLL_LOCK 0x0000 19 #define BUS0_PLL_LOCK 0x0004 20 #define BUS1_DPLL_LOCK 0x0008 21 #define MFC_PLL_LOCK 0x000C 22 #define AUD_PLL_LOCK 0x0010 23 #define CC_PLL_CON0 0x0100 24 #define BUS0_PLL_CON0 0x0110 25 #define BUS1_DPLL_CON0 0x0120 26 #define MFC_PLL_CON0 0x0130 27 #define AUD_PLL_CON0 0x0140 28 #define MUX_SEL_TOPC0 0x0200 29 #define MUX_SEL_TOPC1 0x0204 30 #define MUX_SEL_TOPC2 0x0208 31 #define MUX_SEL_TOPC3 0x020C 32 #define DIV_TOPC0 0x0600 33 #define DIV_TOPC1 0x0604 34 #define DIV_TOPC3 0x060C 35 #define ENABLE_ACLK_TOPC1 0x0804 36 37 static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { 38 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0), 39 FFACTOR(0, "ffac_topc_bus0_pll_div4", 40 "ffac_topc_bus0_pll_div2", 1, 2, 0), 41 FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0), 42 FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0), 43 FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0), 44 }; 45 46 /* List of parent clocks for Muxes in CMU_TOPC */ 47 PNAME(mout_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" }; 48 PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; 49 PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; 50 PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; 51 PNAME(mout_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; 52 53 PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc", 54 "mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc", 55 "mout_sclk_mfc_pll_cmuc" }; 56 57 PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl", 58 "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"}; 59 PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl", 60 "ffac_topc_bus1_pll_div2"}; 61 PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl", 62 "ffac_topc_cc_pll_div2"}; 63 PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl", 64 "ffac_topc_mfc_pll_div2"}; 65 66 67 PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl", 68 "ffac_topc_bus0_pll_div2"}; 69 70 static unsigned long topc_clk_regs[] __initdata = { 71 CC_PLL_LOCK, 72 BUS0_PLL_LOCK, 73 BUS1_DPLL_LOCK, 74 MFC_PLL_LOCK, 75 AUD_PLL_LOCK, 76 CC_PLL_CON0, 77 BUS0_PLL_CON0, 78 BUS1_DPLL_CON0, 79 MFC_PLL_CON0, 80 AUD_PLL_CON0, 81 MUX_SEL_TOPC0, 82 MUX_SEL_TOPC1, 83 MUX_SEL_TOPC2, 84 MUX_SEL_TOPC3, 85 DIV_TOPC0, 86 DIV_TOPC1, 87 DIV_TOPC3, 88 }; 89 90 static struct samsung_mux_clock topc_mux_clks[] __initdata = { 91 MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1), 92 MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1), 93 MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1), 94 MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1), 95 96 MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p, 97 MUX_SEL_TOPC0, 16, 2), 98 MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p, 99 MUX_SEL_TOPC0, 20, 1), 100 MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p, 101 MUX_SEL_TOPC0, 24, 1), 102 MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p, 103 MUX_SEL_TOPC0, 28, 1), 104 105 MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1), 106 MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p, 107 MUX_SEL_TOPC1, 16, 1), 108 109 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), 110 111 MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2), 112 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), 113 }; 114 115 static struct samsung_div_clock topc_div_clks[] __initdata = { 116 DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133", 117 DIV_TOPC0, 4, 4), 118 119 DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532", 120 DIV_TOPC1, 20, 4), 121 DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", 122 DIV_TOPC1, 24, 4), 123 124 DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out", 125 DIV_TOPC3, 0, 4), 126 DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl", 127 DIV_TOPC3, 8, 4), 128 DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl", 129 DIV_TOPC3, 12, 4), 130 DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl", 131 DIV_TOPC3, 16, 4), 132 DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl", 133 DIV_TOPC3, 28, 4), 134 }; 135 136 static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = { 137 PLL_36XX_RATE(491520000, 20, 1, 0, 31457), 138 {}, 139 }; 140 141 static struct samsung_gate_clock topc_gate_clks[] __initdata = { 142 GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532", 143 ENABLE_ACLK_TOPC1, 20, 0, 0), 144 }; 145 146 static struct samsung_pll_clock topc_pll_clks[] __initdata = { 147 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK, 148 BUS0_PLL_CON0, NULL), 149 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK, 150 CC_PLL_CON0, NULL), 151 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK, 152 BUS1_DPLL_CON0, NULL), 153 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK, 154 MFC_PLL_CON0, NULL), 155 PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, 156 AUD_PLL_CON0, pll1460x_24mhz_tbl), 157 }; 158 159 static struct samsung_cmu_info topc_cmu_info __initdata = { 160 .pll_clks = topc_pll_clks, 161 .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), 162 .mux_clks = topc_mux_clks, 163 .nr_mux_clks = ARRAY_SIZE(topc_mux_clks), 164 .div_clks = topc_div_clks, 165 .nr_div_clks = ARRAY_SIZE(topc_div_clks), 166 .gate_clks = topc_gate_clks, 167 .nr_gate_clks = ARRAY_SIZE(topc_gate_clks), 168 .fixed_factor_clks = topc_fixed_factor_clks, 169 .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks), 170 .nr_clk_ids = TOPC_NR_CLK, 171 .clk_regs = topc_clk_regs, 172 .nr_clk_regs = ARRAY_SIZE(topc_clk_regs), 173 }; 174 175 static void __init exynos7_clk_topc_init(struct device_node *np) 176 { 177 samsung_cmu_register_one(np, &topc_cmu_info); 178 } 179 180 CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", 181 exynos7_clk_topc_init); 182 183 /* Register Offset definitions for CMU_TOP0 (0x105D0000) */ 184 #define MUX_SEL_TOP00 0x0200 185 #define MUX_SEL_TOP01 0x0204 186 #define MUX_SEL_TOP03 0x020C 187 #define MUX_SEL_TOP0_PERIC0 0x0230 188 #define MUX_SEL_TOP0_PERIC1 0x0234 189 #define MUX_SEL_TOP0_PERIC2 0x0238 190 #define MUX_SEL_TOP0_PERIC3 0x023C 191 #define DIV_TOP03 0x060C 192 #define DIV_TOP0_PERIC0 0x0630 193 #define DIV_TOP0_PERIC1 0x0634 194 #define DIV_TOP0_PERIC2 0x0638 195 #define DIV_TOP0_PERIC3 0x063C 196 #define ENABLE_SCLK_TOP0_PERIC0 0x0A30 197 #define ENABLE_SCLK_TOP0_PERIC1 0x0A34 198 #define ENABLE_SCLK_TOP0_PERIC2 0x0A38 199 #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C 200 201 /* List of parent clocks for Muxes in CMU_TOP0 */ 202 PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; 203 PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" }; 204 PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" }; 205 PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" }; 206 PNAME(mout_aud_pll_p) = { "fin_pll", "dout_sclk_aud_pll" }; 207 208 PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll", 209 "ffac_top0_bus0_pll_div2"}; 210 PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll", 211 "ffac_top0_bus1_pll_div2"}; 212 PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll", 213 "ffac_top0_cc_pll_div2"}; 214 PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll", 215 "ffac_top0_mfc_pll_div2"}; 216 217 PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll", 218 "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll", 219 "mout_top0_half_mfc_pll"}; 220 PNAME(mout_top0_group3) = {"ioclk_audiocdclk0", 221 "ioclk_audiocdclk1", "ioclk_spdif_extclk", 222 "mout_top0_aud_pll", "mout_top0_half_bus0_pll", 223 "mout_top0_half_bus1_pll"}; 224 PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll", 225 "mout_top0_half_bus0_pll", "mout_top0_half_bus1_pll"}; 226 227 static unsigned long top0_clk_regs[] __initdata = { 228 MUX_SEL_TOP00, 229 MUX_SEL_TOP01, 230 MUX_SEL_TOP03, 231 MUX_SEL_TOP0_PERIC0, 232 MUX_SEL_TOP0_PERIC1, 233 MUX_SEL_TOP0_PERIC2, 234 MUX_SEL_TOP0_PERIC3, 235 DIV_TOP03, 236 DIV_TOP0_PERIC0, 237 DIV_TOP0_PERIC1, 238 DIV_TOP0_PERIC2, 239 DIV_TOP0_PERIC3, 240 ENABLE_SCLK_TOP0_PERIC0, 241 ENABLE_SCLK_TOP0_PERIC1, 242 ENABLE_SCLK_TOP0_PERIC2, 243 ENABLE_SCLK_TOP0_PERIC3, 244 }; 245 246 static struct samsung_mux_clock top0_mux_clks[] __initdata = { 247 MUX(0, "mout_top0_aud_pll", mout_aud_pll_p, MUX_SEL_TOP00, 0, 1), 248 MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1), 249 MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1), 250 MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1), 251 MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1), 252 253 MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p, 254 MUX_SEL_TOP01, 4, 1), 255 MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p, 256 MUX_SEL_TOP01, 8, 1), 257 MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p, 258 MUX_SEL_TOP01, 12, 1), 259 MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p, 260 MUX_SEL_TOP01, 16, 1), 261 262 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), 263 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), 264 265 MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3), 266 MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2), 267 MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2), 268 269 MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2), 270 MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2), 271 272 MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2), 273 MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2), 274 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2), 275 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2), 276 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2), 277 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2), 278 MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2), 279 }; 280 281 static struct samsung_div_clock top0_div_clks[] __initdata = { 282 DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66", 283 DIV_TOP03, 12, 6), 284 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", 285 DIV_TOP03, 20, 6), 286 287 DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4), 288 DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12), 289 DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10), 290 291 DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12), 292 DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12), 293 294 DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12), 295 DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12), 296 297 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4), 298 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4), 299 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4), 300 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4), 301 DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12), 302 }; 303 304 static struct samsung_gate_clock top0_gate_clks[] __initdata = { 305 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif", 306 ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 307 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1", 308 ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 309 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1", 310 ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0), 311 312 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1", 313 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0), 314 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0", 315 ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0), 316 317 GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3", 318 ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0), 319 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2", 320 ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0), 321 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3", 322 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0), 323 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2", 324 ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0), 325 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1", 326 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0), 327 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0", 328 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0), 329 GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4", 330 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0), 331 }; 332 333 static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { 334 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0), 335 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0), 336 FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0), 337 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0), 338 }; 339 340 static struct samsung_cmu_info top0_cmu_info __initdata = { 341 .mux_clks = top0_mux_clks, 342 .nr_mux_clks = ARRAY_SIZE(top0_mux_clks), 343 .div_clks = top0_div_clks, 344 .nr_div_clks = ARRAY_SIZE(top0_div_clks), 345 .gate_clks = top0_gate_clks, 346 .nr_gate_clks = ARRAY_SIZE(top0_gate_clks), 347 .fixed_factor_clks = top0_fixed_factor_clks, 348 .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks), 349 .nr_clk_ids = TOP0_NR_CLK, 350 .clk_regs = top0_clk_regs, 351 .nr_clk_regs = ARRAY_SIZE(top0_clk_regs), 352 }; 353 354 static void __init exynos7_clk_top0_init(struct device_node *np) 355 { 356 samsung_cmu_register_one(np, &top0_cmu_info); 357 } 358 359 CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", 360 exynos7_clk_top0_init); 361 362 /* Register Offset definitions for CMU_TOP1 (0x105E0000) */ 363 #define MUX_SEL_TOP10 0x0200 364 #define MUX_SEL_TOP11 0x0204 365 #define MUX_SEL_TOP13 0x020C 366 #define MUX_SEL_TOP1_FSYS0 0x0224 367 #define MUX_SEL_TOP1_FSYS1 0x0228 368 #define MUX_SEL_TOP1_FSYS11 0x022C 369 #define DIV_TOP13 0x060C 370 #define DIV_TOP1_FSYS0 0x0624 371 #define DIV_TOP1_FSYS1 0x0628 372 #define DIV_TOP1_FSYS11 0x062C 373 #define ENABLE_ACLK_TOP13 0x080C 374 #define ENABLE_SCLK_TOP1_FSYS0 0x0A24 375 #define ENABLE_SCLK_TOP1_FSYS1 0x0A28 376 #define ENABLE_SCLK_TOP1_FSYS11 0x0A2C 377 378 /* List of parent clocks for Muxes in CMU_TOP1 */ 379 PNAME(mout_top1_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; 380 PNAME(mout_top1_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll_b" }; 381 PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" }; 382 PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" }; 383 384 PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll", 385 "ffac_top1_bus0_pll_div2"}; 386 PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll", 387 "ffac_top1_bus1_pll_div2"}; 388 PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll", 389 "ffac_top1_cc_pll_div2"}; 390 PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll", 391 "ffac_top1_mfc_pll_div2"}; 392 393 PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll", 394 "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll", 395 "mout_top1_half_mfc_pll"}; 396 397 static unsigned long top1_clk_regs[] __initdata = { 398 MUX_SEL_TOP10, 399 MUX_SEL_TOP11, 400 MUX_SEL_TOP13, 401 MUX_SEL_TOP1_FSYS0, 402 MUX_SEL_TOP1_FSYS1, 403 MUX_SEL_TOP1_FSYS11, 404 DIV_TOP13, 405 DIV_TOP1_FSYS0, 406 DIV_TOP1_FSYS1, 407 DIV_TOP1_FSYS11, 408 ENABLE_ACLK_TOP13, 409 ENABLE_SCLK_TOP1_FSYS0, 410 ENABLE_SCLK_TOP1_FSYS1, 411 ENABLE_SCLK_TOP1_FSYS11, 412 }; 413 414 static struct samsung_mux_clock top1_mux_clks[] __initdata = { 415 MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1), 416 MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1), 417 MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p, 418 MUX_SEL_TOP10, 12, 1), 419 MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p, 420 MUX_SEL_TOP10, 16, 1), 421 422 MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p, 423 MUX_SEL_TOP11, 4, 1), 424 MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p, 425 MUX_SEL_TOP11, 8, 1), 426 MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p, 427 MUX_SEL_TOP11, 12, 1), 428 MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p, 429 MUX_SEL_TOP11, 16, 1), 430 431 MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2), 432 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2), 433 434 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2), 435 MUX(0, "mout_sclk_usbdrd300", mout_top1_group1, 436 MUX_SEL_TOP1_FSYS0, 28, 2), 437 438 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2), 439 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2), 440 }; 441 442 static struct samsung_div_clock top1_div_clks[] __initdata = { 443 DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200", 444 DIV_TOP13, 24, 4), 445 DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", 446 DIV_TOP13, 28, 4), 447 448 DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2", 449 DIV_TOP1_FSYS0, 16, 10), 450 DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300", 451 DIV_TOP1_FSYS0, 28, 4), 452 453 DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1", 454 DIV_TOP1_FSYS11, 0, 10), 455 DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0", 456 DIV_TOP1_FSYS11, 12, 10), 457 }; 458 459 static struct samsung_gate_clock top1_gate_clks[] __initdata = { 460 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", 461 ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0), 462 GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300", 463 ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0), 464 465 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1", 466 ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0), 467 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0", 468 ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0), 469 }; 470 471 static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { 472 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0), 473 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0), 474 FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0), 475 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0), 476 }; 477 478 static struct samsung_cmu_info top1_cmu_info __initdata = { 479 .mux_clks = top1_mux_clks, 480 .nr_mux_clks = ARRAY_SIZE(top1_mux_clks), 481 .div_clks = top1_div_clks, 482 .nr_div_clks = ARRAY_SIZE(top1_div_clks), 483 .gate_clks = top1_gate_clks, 484 .nr_gate_clks = ARRAY_SIZE(top1_gate_clks), 485 .fixed_factor_clks = top1_fixed_factor_clks, 486 .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks), 487 .nr_clk_ids = TOP1_NR_CLK, 488 .clk_regs = top1_clk_regs, 489 .nr_clk_regs = ARRAY_SIZE(top1_clk_regs), 490 }; 491 492 static void __init exynos7_clk_top1_init(struct device_node *np) 493 { 494 samsung_cmu_register_one(np, &top1_cmu_info); 495 } 496 497 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", 498 exynos7_clk_top1_init); 499 500 /* Register Offset definitions for CMU_CCORE (0x105B0000) */ 501 #define MUX_SEL_CCORE 0x0200 502 #define DIV_CCORE 0x0600 503 #define ENABLE_ACLK_CCORE0 0x0800 504 #define ENABLE_ACLK_CCORE1 0x0804 505 #define ENABLE_PCLK_CCORE 0x0900 506 507 /* 508 * List of parent clocks for Muxes in CMU_CCORE 509 */ 510 PNAME(mout_aclk_ccore_133_p) = { "fin_pll", "dout_aclk_ccore_133" }; 511 512 static unsigned long ccore_clk_regs[] __initdata = { 513 MUX_SEL_CCORE, 514 ENABLE_PCLK_CCORE, 515 }; 516 517 static struct samsung_mux_clock ccore_mux_clks[] __initdata = { 518 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p, 519 MUX_SEL_CCORE, 1, 1), 520 }; 521 522 static struct samsung_gate_clock ccore_gate_clks[] __initdata = { 523 GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user", 524 ENABLE_PCLK_CCORE, 8, 0, 0), 525 }; 526 527 static struct samsung_cmu_info ccore_cmu_info __initdata = { 528 .mux_clks = ccore_mux_clks, 529 .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks), 530 .gate_clks = ccore_gate_clks, 531 .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks), 532 .nr_clk_ids = CCORE_NR_CLK, 533 .clk_regs = ccore_clk_regs, 534 .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs), 535 }; 536 537 static void __init exynos7_clk_ccore_init(struct device_node *np) 538 { 539 samsung_cmu_register_one(np, &ccore_cmu_info); 540 } 541 542 CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", 543 exynos7_clk_ccore_init); 544 545 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ 546 #define MUX_SEL_PERIC0 0x0200 547 #define ENABLE_PCLK_PERIC0 0x0900 548 #define ENABLE_SCLK_PERIC0 0x0A00 549 550 /* List of parent clocks for Muxes in CMU_PERIC0 */ 551 PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" }; 552 PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" }; 553 554 static unsigned long peric0_clk_regs[] __initdata = { 555 MUX_SEL_PERIC0, 556 ENABLE_PCLK_PERIC0, 557 ENABLE_SCLK_PERIC0, 558 }; 559 560 static struct samsung_mux_clock peric0_mux_clks[] __initdata = { 561 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p, 562 MUX_SEL_PERIC0, 0, 1), 563 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p, 564 MUX_SEL_PERIC0, 16, 1), 565 }; 566 567 static struct samsung_gate_clock peric0_gate_clks[] __initdata = { 568 GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user", 569 ENABLE_PCLK_PERIC0, 8, 0, 0), 570 GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user", 571 ENABLE_PCLK_PERIC0, 9, 0, 0), 572 GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user", 573 ENABLE_PCLK_PERIC0, 10, 0, 0), 574 GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user", 575 ENABLE_PCLK_PERIC0, 11, 0, 0), 576 GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user", 577 ENABLE_PCLK_PERIC0, 12, 0, 0), 578 GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user", 579 ENABLE_PCLK_PERIC0, 13, 0, 0), 580 GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user", 581 ENABLE_PCLK_PERIC0, 14, 0, 0), 582 GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", 583 ENABLE_PCLK_PERIC0, 16, 0, 0), 584 GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user", 585 ENABLE_PCLK_PERIC0, 20, 0, 0), 586 GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user", 587 ENABLE_PCLK_PERIC0, 21, 0, 0), 588 589 GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user", 590 ENABLE_SCLK_PERIC0, 16, 0, 0), 591 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), 592 }; 593 594 static struct samsung_cmu_info peric0_cmu_info __initdata = { 595 .mux_clks = peric0_mux_clks, 596 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 597 .gate_clks = peric0_gate_clks, 598 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), 599 .nr_clk_ids = PERIC0_NR_CLK, 600 .clk_regs = peric0_clk_regs, 601 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 602 }; 603 604 static void __init exynos7_clk_peric0_init(struct device_node *np) 605 { 606 samsung_cmu_register_one(np, &peric0_cmu_info); 607 } 608 609 /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ 610 #define MUX_SEL_PERIC10 0x0200 611 #define MUX_SEL_PERIC11 0x0204 612 #define MUX_SEL_PERIC12 0x0208 613 #define ENABLE_PCLK_PERIC1 0x0900 614 #define ENABLE_SCLK_PERIC10 0x0A00 615 616 CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", 617 exynos7_clk_peric0_init); 618 619 /* List of parent clocks for Muxes in CMU_PERIC1 */ 620 PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" }; 621 PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" }; 622 PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" }; 623 PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" }; 624 PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" }; 625 PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" }; 626 PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" }; 627 PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" }; 628 PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" }; 629 630 static unsigned long peric1_clk_regs[] __initdata = { 631 MUX_SEL_PERIC10, 632 MUX_SEL_PERIC11, 633 MUX_SEL_PERIC12, 634 ENABLE_PCLK_PERIC1, 635 ENABLE_SCLK_PERIC10, 636 }; 637 638 static struct samsung_mux_clock peric1_mux_clks[] __initdata = { 639 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p, 640 MUX_SEL_PERIC10, 0, 1), 641 642 MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p, 643 MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0), 644 MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p, 645 MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0), 646 MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p, 647 MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0), 648 MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p, 649 MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0), 650 MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p, 651 MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0), 652 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p, 653 MUX_SEL_PERIC11, 20, 1), 654 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p, 655 MUX_SEL_PERIC11, 24, 1), 656 MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p, 657 MUX_SEL_PERIC11, 28, 1), 658 }; 659 660 static struct samsung_gate_clock peric1_gate_clks[] __initdata = { 661 GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user", 662 ENABLE_PCLK_PERIC1, 4, 0, 0), 663 GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user", 664 ENABLE_PCLK_PERIC1, 5, 0, 0), 665 GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user", 666 ENABLE_PCLK_PERIC1, 6, 0, 0), 667 GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user", 668 ENABLE_PCLK_PERIC1, 7, 0, 0), 669 GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user", 670 ENABLE_PCLK_PERIC1, 8, 0, 0), 671 GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user", 672 ENABLE_PCLK_PERIC1, 9, 0, 0), 673 GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user", 674 ENABLE_PCLK_PERIC1, 10, 0, 0), 675 GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user", 676 ENABLE_PCLK_PERIC1, 11, 0, 0), 677 GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user", 678 ENABLE_PCLK_PERIC1, 12, 0, 0), 679 GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user", 680 ENABLE_PCLK_PERIC1, 13, 0, 0), 681 GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user", 682 ENABLE_PCLK_PERIC1, 14, 0, 0), 683 GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user", 684 ENABLE_PCLK_PERIC1, 15, 0, 0), 685 GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user", 686 ENABLE_PCLK_PERIC1, 16, 0, 0), 687 GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user", 688 ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0), 689 GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user", 690 ENABLE_PCLK_PERIC1, 18, 0, 0), 691 GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user", 692 ENABLE_PCLK_PERIC1, 19, 0, 0), 693 694 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", 695 ENABLE_SCLK_PERIC10, 9, 0, 0), 696 GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user", 697 ENABLE_SCLK_PERIC10, 10, 0, 0), 698 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user", 699 ENABLE_SCLK_PERIC10, 11, 0, 0), 700 GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user", 701 ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0), 702 GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user", 703 ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0), 704 GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user", 705 ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0), 706 GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user", 707 ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0), 708 GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user", 709 ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0), 710 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1", 711 ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0), 712 GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1", 713 ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0), 714 GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif", 715 ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0), 716 }; 717 718 static struct samsung_cmu_info peric1_cmu_info __initdata = { 719 .mux_clks = peric1_mux_clks, 720 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 721 .gate_clks = peric1_gate_clks, 722 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), 723 .nr_clk_ids = PERIC1_NR_CLK, 724 .clk_regs = peric1_clk_regs, 725 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 726 }; 727 728 static void __init exynos7_clk_peric1_init(struct device_node *np) 729 { 730 samsung_cmu_register_one(np, &peric1_cmu_info); 731 } 732 733 CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", 734 exynos7_clk_peric1_init); 735 736 /* Register Offset definitions for CMU_PERIS (0x10040000) */ 737 #define MUX_SEL_PERIS 0x0200 738 #define ENABLE_PCLK_PERIS 0x0900 739 #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910 740 #define ENABLE_SCLK_PERIS 0x0A00 741 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10 742 743 /* List of parent clocks for Muxes in CMU_PERIS */ 744 PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" }; 745 746 static unsigned long peris_clk_regs[] __initdata = { 747 MUX_SEL_PERIS, 748 ENABLE_PCLK_PERIS, 749 ENABLE_PCLK_PERIS_SECURE_CHIPID, 750 ENABLE_SCLK_PERIS, 751 ENABLE_SCLK_PERIS_SECURE_CHIPID, 752 }; 753 754 static struct samsung_mux_clock peris_mux_clks[] __initdata = { 755 MUX(0, "mout_aclk_peris_66_user", 756 mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1), 757 }; 758 759 static struct samsung_gate_clock peris_gate_clks[] __initdata = { 760 GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user", 761 ENABLE_PCLK_PERIS, 6, 0, 0), 762 GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user", 763 ENABLE_PCLK_PERIS, 10, 0, 0), 764 765 GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user", 766 ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 767 GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll", 768 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 769 770 GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), 771 }; 772 773 static struct samsung_cmu_info peris_cmu_info __initdata = { 774 .mux_clks = peris_mux_clks, 775 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), 776 .gate_clks = peris_gate_clks, 777 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 778 .nr_clk_ids = PERIS_NR_CLK, 779 .clk_regs = peris_clk_regs, 780 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 781 }; 782 783 static void __init exynos7_clk_peris_init(struct device_node *np) 784 { 785 samsung_cmu_register_one(np, &peris_cmu_info); 786 } 787 788 CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", 789 exynos7_clk_peris_init); 790 791 /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */ 792 #define MUX_SEL_FSYS00 0x0200 793 #define MUX_SEL_FSYS01 0x0204 794 #define MUX_SEL_FSYS02 0x0208 795 #define ENABLE_ACLK_FSYS00 0x0800 796 #define ENABLE_ACLK_FSYS01 0x0804 797 #define ENABLE_SCLK_FSYS01 0x0A04 798 #define ENABLE_SCLK_FSYS02 0x0A08 799 #define ENABLE_SCLK_FSYS04 0x0A10 800 801 /* 802 * List of parent clocks for Muxes in CMU_FSYS0 803 */ 804 PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" }; 805 PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" }; 806 807 PNAME(mout_sclk_usbdrd300_p) = { "fin_pll", "sclk_usbdrd300" }; 808 PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p) = { "fin_pll", 809 "phyclk_usbdrd300_udrd30_phyclock" }; 810 PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p) = { "fin_pll", 811 "phyclk_usbdrd300_udrd30_pipe_pclk" }; 812 813 /* fixed rate clocks used in the FSYS0 block */ 814 struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = { 815 FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 816 CLK_IS_ROOT, 60000000), 817 FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 818 CLK_IS_ROOT, 125000000), 819 }; 820 821 static unsigned long fsys0_clk_regs[] __initdata = { 822 MUX_SEL_FSYS00, 823 MUX_SEL_FSYS01, 824 MUX_SEL_FSYS02, 825 ENABLE_ACLK_FSYS00, 826 ENABLE_ACLK_FSYS01, 827 ENABLE_SCLK_FSYS01, 828 ENABLE_SCLK_FSYS02, 829 ENABLE_SCLK_FSYS04, 830 }; 831 832 static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { 833 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p, 834 MUX_SEL_FSYS00, 24, 1), 835 836 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1), 837 MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p, 838 MUX_SEL_FSYS01, 28, 1), 839 840 MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", 841 mout_phyclk_usbdrd300_udrd30_pipe_pclk_p, 842 MUX_SEL_FSYS02, 24, 1), 843 MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user", 844 mout_phyclk_usbdrd300_udrd30_phyclk_p, 845 MUX_SEL_FSYS02, 28, 1), 846 }; 847 848 static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { 849 GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user", 850 ENABLE_ACLK_FSYS00, 3, 0, 0), 851 GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user", 852 ENABLE_ACLK_FSYS00, 4, 0, 0), 853 GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", 854 "mout_aclk_fsys0_200_user", 855 ENABLE_ACLK_FSYS00, 19, 0, 0), 856 857 GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user", 858 ENABLE_ACLK_FSYS01, 29, 0, 0), 859 GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user", 860 ENABLE_ACLK_FSYS01, 31, 0, 0), 861 862 GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk", 863 "mout_sclk_usbdrd300_user", 864 ENABLE_SCLK_FSYS01, 4, 0, 0), 865 GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll", 866 ENABLE_SCLK_FSYS01, 8, 0, 0), 867 868 GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER, 869 "phyclk_usbdrd300_udrd30_pipe_pclk_user", 870 "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", 871 ENABLE_SCLK_FSYS02, 24, 0, 0), 872 GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER, 873 "phyclk_usbdrd300_udrd30_phyclk_user", 874 "mout_phyclk_usbdrd300_udrd30_phyclk_user", 875 ENABLE_SCLK_FSYS02, 28, 0, 0), 876 877 GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy", 878 "fin_pll", 879 ENABLE_SCLK_FSYS04, 28, 0, 0), 880 }; 881 882 static struct samsung_cmu_info fsys0_cmu_info __initdata = { 883 .mux_clks = fsys0_mux_clks, 884 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), 885 .gate_clks = fsys0_gate_clks, 886 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), 887 .nr_clk_ids = FSYS0_NR_CLK, 888 .clk_regs = fsys0_clk_regs, 889 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), 890 }; 891 892 static void __init exynos7_clk_fsys0_init(struct device_node *np) 893 { 894 samsung_cmu_register_one(np, &fsys0_cmu_info); 895 } 896 897 CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", 898 exynos7_clk_fsys0_init); 899 900 /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ 901 #define MUX_SEL_FSYS10 0x0200 902 #define MUX_SEL_FSYS11 0x0204 903 #define ENABLE_ACLK_FSYS1 0x0800 904 905 /* 906 * List of parent clocks for Muxes in CMU_FSYS1 907 */ 908 PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" }; 909 PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" }; 910 PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" }; 911 912 static unsigned long fsys1_clk_regs[] __initdata = { 913 MUX_SEL_FSYS10, 914 MUX_SEL_FSYS11, 915 ENABLE_ACLK_FSYS1, 916 }; 917 918 static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { 919 MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p, 920 MUX_SEL_FSYS10, 28, 1), 921 922 MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1), 923 MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1), 924 }; 925 926 static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { 927 GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user", 928 ENABLE_ACLK_FSYS1, 29, 0, 0), 929 GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user", 930 ENABLE_ACLK_FSYS1, 30, 0, 0), 931 }; 932 933 static struct samsung_cmu_info fsys1_cmu_info __initdata = { 934 .mux_clks = fsys1_mux_clks, 935 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), 936 .gate_clks = fsys1_gate_clks, 937 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), 938 .nr_clk_ids = TOP1_NR_CLK, 939 .clk_regs = fsys1_clk_regs, 940 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), 941 }; 942 943 static void __init exynos7_clk_fsys1_init(struct device_node *np) 944 { 945 samsung_cmu_register_one(np, &fsys1_cmu_info); 946 } 947 948 CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", 949 exynos7_clk_fsys1_init); 950 951 #define MUX_SEL_MSCL 0x0200 952 #define DIV_MSCL 0x0600 953 #define ENABLE_ACLK_MSCL 0x0800 954 #define ENABLE_PCLK_MSCL 0x0900 955 956 /* List of parent clocks for Muxes in CMU_MSCL */ 957 PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" }; 958 959 static unsigned long mscl_clk_regs[] __initdata = { 960 MUX_SEL_MSCL, 961 DIV_MSCL, 962 ENABLE_ACLK_MSCL, 963 ENABLE_PCLK_MSCL, 964 }; 965 966 static struct samsung_mux_clock mscl_mux_clks[] __initdata = { 967 MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532", 968 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1), 969 }; 970 static struct samsung_div_clock mscl_div_clks[] __initdata = { 971 DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532", 972 DIV_MSCL, 0, 3), 973 }; 974 static struct samsung_gate_clock mscl_gate_clks[] __initdata = { 975 976 GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532", 977 ENABLE_ACLK_MSCL, 31, 0, 0), 978 GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532", 979 ENABLE_ACLK_MSCL, 30, 0, 0), 980 GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532", 981 ENABLE_ACLK_MSCL, 29, 0, 0), 982 GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532", 983 ENABLE_ACLK_MSCL, 28, 0, 0), 984 GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0", 985 "usermux_aclk_mscl_532", 986 ENABLE_ACLK_MSCL, 27, 0, 0), 987 GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1", 988 "usermux_aclk_mscl_532", 989 ENABLE_ACLK_MSCL, 26, 0, 0), 990 GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532", 991 ENABLE_ACLK_MSCL, 25, 0, 0), 992 GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532", 993 ENABLE_ACLK_MSCL, 24, 0, 0), 994 GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge", 995 "usermux_aclk_mscl_532", 996 ENABLE_ACLK_MSCL, 23, 0, 0), 997 GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532", 998 ENABLE_ACLK_MSCL, 22, 0, 0), 999 GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532", 1000 ENABLE_ACLK_MSCL, 21, 0, 0), 1001 GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532", 1002 ENABLE_ACLK_MSCL, 20, 0, 0), 1003 GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532", 1004 ENABLE_ACLK_MSCL, 19, 0, 0), 1005 GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532", 1006 ENABLE_ACLK_MSCL, 18, 0, 0), 1007 GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532", 1008 ENABLE_ACLK_MSCL, 17, 0, 0), 1009 GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532", 1010 ENABLE_ACLK_MSCL, 16, 0, 0), 1011 GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p", 1012 "usermux_aclk_mscl_532", 1013 ENABLE_ACLK_MSCL, 15, 0, 0), 1014 GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p", 1015 "usermux_aclk_mscl_532", 1016 ENABLE_ACLK_MSCL, 14, 0, 0), 1017 1018 GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl", 1019 ENABLE_PCLK_MSCL, 31, 0, 0), 1020 GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl", 1021 ENABLE_PCLK_MSCL, 30, 0, 0), 1022 GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl", 1023 ENABLE_PCLK_MSCL, 29, 0, 0), 1024 GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl", 1025 ENABLE_PCLK_MSCL, 28, 0, 0), 1026 GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl", 1027 ENABLE_PCLK_MSCL, 27, 0, 0), 1028 GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl", 1029 ENABLE_PCLK_MSCL, 26, 0, 0), 1030 GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl", 1031 ENABLE_PCLK_MSCL, 25, 0, 0), 1032 GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl", 1033 ENABLE_PCLK_MSCL, 24, 0, 0), 1034 GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl", 1035 ENABLE_PCLK_MSCL, 23, 0, 0), 1036 GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl", 1037 ENABLE_PCLK_MSCL, 22, 0, 0), 1038 GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl", 1039 ENABLE_PCLK_MSCL, 21, 0, 0), 1040 GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl", 1041 ENABLE_PCLK_MSCL, 20, 0, 0), 1042 }; 1043 1044 static struct samsung_cmu_info mscl_cmu_info __initdata = { 1045 .mux_clks = mscl_mux_clks, 1046 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 1047 .div_clks = mscl_div_clks, 1048 .nr_div_clks = ARRAY_SIZE(mscl_div_clks), 1049 .gate_clks = mscl_gate_clks, 1050 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), 1051 .nr_clk_ids = MSCL_NR_CLK, 1052 .clk_regs = mscl_clk_regs, 1053 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), 1054 }; 1055 1056 static void __init exynos7_clk_mscl_init(struct device_node *np) 1057 { 1058 samsung_cmu_register_one(np, &mscl_cmu_info); 1059 } 1060 1061 CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl", 1062 exynos7_clk_mscl_init); 1063 1064 /* Register Offset definitions for CMU_AUD (0x114C0000) */ 1065 #define MUX_SEL_AUD 0x0200 1066 #define DIV_AUD0 0x0600 1067 #define DIV_AUD1 0x0604 1068 #define ENABLE_ACLK_AUD 0x0800 1069 #define ENABLE_PCLK_AUD 0x0900 1070 #define ENABLE_SCLK_AUD 0x0A00 1071 1072 /* 1073 * List of parent clocks for Muxes in CMU_AUD 1074 */ 1075 PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" }; 1076 PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" }; 1077 1078 static unsigned long aud_clk_regs[] __initdata = { 1079 MUX_SEL_AUD, 1080 DIV_AUD0, 1081 DIV_AUD1, 1082 ENABLE_ACLK_AUD, 1083 ENABLE_PCLK_AUD, 1084 ENABLE_SCLK_AUD, 1085 }; 1086 1087 static struct samsung_mux_clock aud_mux_clks[] __initdata = { 1088 MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1), 1089 MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1), 1090 MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1), 1091 }; 1092 1093 static struct samsung_div_clock aud_div_clks[] __initdata = { 1094 DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4), 1095 DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4), 1096 DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4), 1097 1098 DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4), 1099 DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8), 1100 DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4), 1101 DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5), 1102 DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4), 1103 }; 1104 1105 static struct samsung_gate_clock aud_gate_clks[] __initdata = { 1106 GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm", 1107 ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 1108 GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s", 1109 ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0), 1110 GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0), 1111 GATE(0, "sclk_slimbus", "dout_sclk_slimbus", 1112 ENABLE_SCLK_AUD, 30, 0, 0), 1113 1114 GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0), 1115 GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0), 1116 GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0), 1117 GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0), 1118 GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0), 1119 GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0), 1120 GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud", 1121 ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0), 1122 GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud", 1123 ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 1124 GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0), 1125 GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0), 1126 1127 GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0), 1128 GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud", 1129 ENABLE_ACLK_AUD, 28, 0, 0), 1130 GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0), 1131 }; 1132 1133 static struct samsung_cmu_info aud_cmu_info __initdata = { 1134 .mux_clks = aud_mux_clks, 1135 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 1136 .div_clks = aud_div_clks, 1137 .nr_div_clks = ARRAY_SIZE(aud_div_clks), 1138 .gate_clks = aud_gate_clks, 1139 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 1140 .nr_clk_ids = AUD_NR_CLK, 1141 .clk_regs = aud_clk_regs, 1142 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 1143 }; 1144 1145 static void __init exynos7_clk_aud_init(struct device_node *np) 1146 { 1147 samsung_cmu_register_one(np, &aud_cmu_info); 1148 } 1149 1150 CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud", 1151 exynos7_clk_aud_init); 1152