1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/of.h> 13 14 #include "clk.h" 15 #include <dt-bindings/clock/exynos7-clk.h> 16 17 /* Register Offset definitions for CMU_TOPC (0x10570000) */ 18 #define CC_PLL_LOCK 0x0000 19 #define BUS0_PLL_LOCK 0x0004 20 #define BUS1_DPLL_LOCK 0x0008 21 #define MFC_PLL_LOCK 0x000C 22 #define AUD_PLL_LOCK 0x0010 23 #define CC_PLL_CON0 0x0100 24 #define BUS0_PLL_CON0 0x0110 25 #define BUS1_DPLL_CON0 0x0120 26 #define MFC_PLL_CON0 0x0130 27 #define AUD_PLL_CON0 0x0140 28 #define MUX_SEL_TOPC0 0x0200 29 #define MUX_SEL_TOPC1 0x0204 30 #define MUX_SEL_TOPC2 0x0208 31 #define MUX_SEL_TOPC3 0x020C 32 #define DIV_TOPC0 0x0600 33 #define DIV_TOPC1 0x0604 34 #define DIV_TOPC3 0x060C 35 #define ENABLE_ACLK_TOPC0 0x0800 36 #define ENABLE_ACLK_TOPC1 0x0804 37 #define ENABLE_SCLK_TOPC1 0x0A04 38 39 static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { 40 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0), 41 FFACTOR(0, "ffac_topc_bus0_pll_div4", 42 "ffac_topc_bus0_pll_div2", 1, 2, 0), 43 FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0), 44 FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0), 45 FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0), 46 }; 47 48 /* List of parent clocks for Muxes in CMU_TOPC */ 49 PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" }; 50 PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; 51 PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; 52 PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; 53 PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; 54 55 PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half", 56 "mout_topc_bus1_pll_half", "mout_topc_cc_pll_half", 57 "mout_topc_mfc_pll_half" }; 58 59 PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll", 60 "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"}; 61 PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll", 62 "ffac_topc_bus1_pll_div2"}; 63 PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll", 64 "ffac_topc_cc_pll_div2"}; 65 PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll", 66 "ffac_topc_mfc_pll_div2"}; 67 68 69 PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll", 70 "ffac_topc_bus0_pll_div2"}; 71 72 static unsigned long topc_clk_regs[] __initdata = { 73 CC_PLL_LOCK, 74 BUS0_PLL_LOCK, 75 BUS1_DPLL_LOCK, 76 MFC_PLL_LOCK, 77 AUD_PLL_LOCK, 78 CC_PLL_CON0, 79 BUS0_PLL_CON0, 80 BUS1_DPLL_CON0, 81 MFC_PLL_CON0, 82 AUD_PLL_CON0, 83 MUX_SEL_TOPC0, 84 MUX_SEL_TOPC1, 85 MUX_SEL_TOPC2, 86 MUX_SEL_TOPC3, 87 DIV_TOPC0, 88 DIV_TOPC1, 89 DIV_TOPC3, 90 }; 91 92 static struct samsung_mux_clock topc_mux_clks[] __initdata = { 93 MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p, 94 MUX_SEL_TOPC0, 0, 1), 95 MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p, 96 MUX_SEL_TOPC0, 4, 1), 97 MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p, 98 MUX_SEL_TOPC0, 8, 1), 99 MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p, 100 MUX_SEL_TOPC0, 12, 1), 101 MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p, 102 MUX_SEL_TOPC0, 16, 2), 103 MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p, 104 MUX_SEL_TOPC0, 20, 1), 105 MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p, 106 MUX_SEL_TOPC0, 24, 1), 107 MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p, 108 MUX_SEL_TOPC0, 28, 1), 109 110 MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p, 111 MUX_SEL_TOPC1, 0, 1), 112 MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p, 113 MUX_SEL_TOPC1, 16, 1), 114 115 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), 116 117 MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2), 118 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), 119 }; 120 121 static struct samsung_div_clock topc_div_clks[] __initdata = { 122 DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133", 123 DIV_TOPC0, 4, 4), 124 125 DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532", 126 DIV_TOPC1, 20, 4), 127 DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", 128 DIV_TOPC1, 24, 4), 129 130 DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out", 131 DIV_TOPC3, 0, 4), 132 DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll", 133 DIV_TOPC3, 8, 4), 134 DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll", 135 DIV_TOPC3, 12, 4), 136 DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll", 137 DIV_TOPC3, 16, 4), 138 DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll", 139 DIV_TOPC3, 28, 4), 140 }; 141 142 static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = { 143 PLL_36XX_RATE(491520000, 20, 1, 0, 31457), 144 {}, 145 }; 146 147 static struct samsung_gate_clock topc_gate_clks[] __initdata = { 148 GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133", 149 ENABLE_ACLK_TOPC0, 4, 0, 0), 150 151 GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532", 152 ENABLE_ACLK_TOPC1, 20, 0, 0), 153 154 GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66", 155 ENABLE_ACLK_TOPC1, 24, 0, 0), 156 157 GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll", 158 ENABLE_SCLK_TOPC1, 20, 0, 0), 159 GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll", 160 ENABLE_SCLK_TOPC1, 17, 0, 0), 161 GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll", 162 ENABLE_SCLK_TOPC1, 16, 0, 0), 163 GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll", 164 ENABLE_SCLK_TOPC1, 13, 0, 0), 165 GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll", 166 ENABLE_SCLK_TOPC1, 12, 0, 0), 167 GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll", 168 ENABLE_SCLK_TOPC1, 5, 0, 0), 169 GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll", 170 ENABLE_SCLK_TOPC1, 4, 0, 0), 171 GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll", 172 ENABLE_SCLK_TOPC1, 1, 0, 0), 173 GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll", 174 ENABLE_SCLK_TOPC1, 0, 0, 0), 175 }; 176 177 static struct samsung_pll_clock topc_pll_clks[] __initdata = { 178 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK, 179 BUS0_PLL_CON0, NULL), 180 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK, 181 CC_PLL_CON0, NULL), 182 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK, 183 BUS1_DPLL_CON0, NULL), 184 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK, 185 MFC_PLL_CON0, NULL), 186 PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, 187 AUD_PLL_CON0, pll1460x_24mhz_tbl), 188 }; 189 190 static struct samsung_cmu_info topc_cmu_info __initdata = { 191 .pll_clks = topc_pll_clks, 192 .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), 193 .mux_clks = topc_mux_clks, 194 .nr_mux_clks = ARRAY_SIZE(topc_mux_clks), 195 .div_clks = topc_div_clks, 196 .nr_div_clks = ARRAY_SIZE(topc_div_clks), 197 .gate_clks = topc_gate_clks, 198 .nr_gate_clks = ARRAY_SIZE(topc_gate_clks), 199 .fixed_factor_clks = topc_fixed_factor_clks, 200 .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks), 201 .nr_clk_ids = TOPC_NR_CLK, 202 .clk_regs = topc_clk_regs, 203 .nr_clk_regs = ARRAY_SIZE(topc_clk_regs), 204 }; 205 206 static void __init exynos7_clk_topc_init(struct device_node *np) 207 { 208 samsung_cmu_register_one(np, &topc_cmu_info); 209 } 210 211 CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", 212 exynos7_clk_topc_init); 213 214 /* Register Offset definitions for CMU_TOP0 (0x105D0000) */ 215 #define MUX_SEL_TOP00 0x0200 216 #define MUX_SEL_TOP01 0x0204 217 #define MUX_SEL_TOP03 0x020C 218 #define MUX_SEL_TOP0_PERIC0 0x0230 219 #define MUX_SEL_TOP0_PERIC1 0x0234 220 #define MUX_SEL_TOP0_PERIC2 0x0238 221 #define MUX_SEL_TOP0_PERIC3 0x023C 222 #define DIV_TOP03 0x060C 223 #define DIV_TOP0_PERIC0 0x0630 224 #define DIV_TOP0_PERIC1 0x0634 225 #define DIV_TOP0_PERIC2 0x0638 226 #define DIV_TOP0_PERIC3 0x063C 227 #define ENABLE_SCLK_TOP0_PERIC0 0x0A30 228 #define ENABLE_SCLK_TOP0_PERIC1 0x0A34 229 #define ENABLE_SCLK_TOP0_PERIC2 0x0A38 230 #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C 231 232 /* List of parent clocks for Muxes in CMU_TOP0 */ 233 PNAME(mout_top0_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_a" }; 234 PNAME(mout_top0_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_a" }; 235 PNAME(mout_top0_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_a" }; 236 PNAME(mout_top0_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_a" }; 237 PNAME(mout_top0_aud_pll_user_p) = { "fin_pll", "sclk_aud_pll" }; 238 239 PNAME(mout_top0_bus0_pll_half_p) = {"mout_top0_bus0_pll_user", 240 "ffac_top0_bus0_pll_div2"}; 241 PNAME(mout_top0_bus1_pll_half_p) = {"mout_top0_bus1_pll_user", 242 "ffac_top0_bus1_pll_div2"}; 243 PNAME(mout_top0_cc_pll_half_p) = {"mout_top0_cc_pll_user", 244 "ffac_top0_cc_pll_div2"}; 245 PNAME(mout_top0_mfc_pll_half_p) = {"mout_top0_mfc_pll_user", 246 "ffac_top0_mfc_pll_div2"}; 247 248 PNAME(mout_top0_group1) = {"mout_top0_bus0_pll_half", 249 "mout_top0_bus1_pll_half", "mout_top0_cc_pll_half", 250 "mout_top0_mfc_pll_half"}; 251 PNAME(mout_top0_group3) = {"ioclk_audiocdclk0", 252 "ioclk_audiocdclk1", "ioclk_spdif_extclk", 253 "mout_top0_aud_pll_user", "mout_top0_bus0_pll_half", 254 "mout_top0_bus1_pll_half"}; 255 PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user", 256 "mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"}; 257 258 static unsigned long top0_clk_regs[] __initdata = { 259 MUX_SEL_TOP00, 260 MUX_SEL_TOP01, 261 MUX_SEL_TOP03, 262 MUX_SEL_TOP0_PERIC0, 263 MUX_SEL_TOP0_PERIC1, 264 MUX_SEL_TOP0_PERIC2, 265 MUX_SEL_TOP0_PERIC3, 266 DIV_TOP03, 267 DIV_TOP0_PERIC0, 268 DIV_TOP0_PERIC1, 269 DIV_TOP0_PERIC2, 270 DIV_TOP0_PERIC3, 271 ENABLE_SCLK_TOP0_PERIC0, 272 ENABLE_SCLK_TOP0_PERIC1, 273 ENABLE_SCLK_TOP0_PERIC2, 274 ENABLE_SCLK_TOP0_PERIC3, 275 }; 276 277 static struct samsung_mux_clock top0_mux_clks[] __initdata = { 278 MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p, 279 MUX_SEL_TOP00, 0, 1), 280 MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p, 281 MUX_SEL_TOP00, 4, 1), 282 MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p, 283 MUX_SEL_TOP00, 8, 1), 284 MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p, 285 MUX_SEL_TOP00, 12, 1), 286 MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p, 287 MUX_SEL_TOP00, 16, 1), 288 289 MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p, 290 MUX_SEL_TOP01, 4, 1), 291 MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p, 292 MUX_SEL_TOP01, 8, 1), 293 MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p, 294 MUX_SEL_TOP01, 12, 1), 295 MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p, 296 MUX_SEL_TOP01, 16, 1), 297 298 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), 299 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), 300 301 MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3), 302 MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2), 303 MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2), 304 305 MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2), 306 MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2), 307 308 MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2), 309 MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2), 310 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2), 311 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2), 312 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2), 313 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2), 314 MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2), 315 }; 316 317 static struct samsung_div_clock top0_div_clks[] __initdata = { 318 DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66", 319 DIV_TOP03, 12, 6), 320 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", 321 DIV_TOP03, 20, 6), 322 323 DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4), 324 DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12), 325 DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10), 326 327 DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12), 328 DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12), 329 330 DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12), 331 DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12), 332 333 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4), 334 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4), 335 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4), 336 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4), 337 DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12), 338 }; 339 340 static struct samsung_gate_clock top0_gate_clks[] __initdata = { 341 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif", 342 ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 343 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1", 344 ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 345 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1", 346 ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0), 347 348 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1", 349 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0), 350 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0", 351 ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0), 352 353 GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3", 354 ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0), 355 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2", 356 ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0), 357 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3", 358 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0), 359 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2", 360 ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0), 361 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1", 362 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0), 363 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0", 364 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0), 365 GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4", 366 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0), 367 }; 368 369 static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { 370 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user", 371 1, 2, 0), 372 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user", 373 1, 2, 0), 374 FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0), 375 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0), 376 }; 377 378 static struct samsung_cmu_info top0_cmu_info __initdata = { 379 .mux_clks = top0_mux_clks, 380 .nr_mux_clks = ARRAY_SIZE(top0_mux_clks), 381 .div_clks = top0_div_clks, 382 .nr_div_clks = ARRAY_SIZE(top0_div_clks), 383 .gate_clks = top0_gate_clks, 384 .nr_gate_clks = ARRAY_SIZE(top0_gate_clks), 385 .fixed_factor_clks = top0_fixed_factor_clks, 386 .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks), 387 .nr_clk_ids = TOP0_NR_CLK, 388 .clk_regs = top0_clk_regs, 389 .nr_clk_regs = ARRAY_SIZE(top0_clk_regs), 390 }; 391 392 static void __init exynos7_clk_top0_init(struct device_node *np) 393 { 394 samsung_cmu_register_one(np, &top0_cmu_info); 395 } 396 397 CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", 398 exynos7_clk_top0_init); 399 400 /* Register Offset definitions for CMU_TOP1 (0x105E0000) */ 401 #define MUX_SEL_TOP10 0x0200 402 #define MUX_SEL_TOP11 0x0204 403 #define MUX_SEL_TOP13 0x020C 404 #define MUX_SEL_TOP1_FSYS0 0x0224 405 #define MUX_SEL_TOP1_FSYS1 0x0228 406 #define MUX_SEL_TOP1_FSYS11 0x022C 407 #define DIV_TOP13 0x060C 408 #define DIV_TOP1_FSYS0 0x0624 409 #define DIV_TOP1_FSYS1 0x0628 410 #define DIV_TOP1_FSYS11 0x062C 411 #define ENABLE_ACLK_TOP13 0x080C 412 #define ENABLE_SCLK_TOP1_FSYS0 0x0A24 413 #define ENABLE_SCLK_TOP1_FSYS1 0x0A28 414 #define ENABLE_SCLK_TOP1_FSYS11 0x0A2C 415 416 /* List of parent clocks for Muxes in CMU_TOP1 */ 417 PNAME(mout_top1_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_b" }; 418 PNAME(mout_top1_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_b" }; 419 PNAME(mout_top1_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_b" }; 420 PNAME(mout_top1_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_b" }; 421 422 PNAME(mout_top1_bus0_pll_half_p) = {"mout_top1_bus0_pll_user", 423 "ffac_top1_bus0_pll_div2"}; 424 PNAME(mout_top1_bus1_pll_half_p) = {"mout_top1_bus1_pll_user", 425 "ffac_top1_bus1_pll_div2"}; 426 PNAME(mout_top1_cc_pll_half_p) = {"mout_top1_cc_pll_user", 427 "ffac_top1_cc_pll_div2"}; 428 PNAME(mout_top1_mfc_pll_half_p) = {"mout_top1_mfc_pll_user", 429 "ffac_top1_mfc_pll_div2"}; 430 431 PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half", 432 "mout_top1_bus1_pll_half", "mout_top1_cc_pll_half", 433 "mout_top1_mfc_pll_half"}; 434 435 static unsigned long top1_clk_regs[] __initdata = { 436 MUX_SEL_TOP10, 437 MUX_SEL_TOP11, 438 MUX_SEL_TOP13, 439 MUX_SEL_TOP1_FSYS0, 440 MUX_SEL_TOP1_FSYS1, 441 MUX_SEL_TOP1_FSYS11, 442 DIV_TOP13, 443 DIV_TOP1_FSYS0, 444 DIV_TOP1_FSYS1, 445 DIV_TOP1_FSYS11, 446 ENABLE_ACLK_TOP13, 447 ENABLE_SCLK_TOP1_FSYS0, 448 ENABLE_SCLK_TOP1_FSYS1, 449 ENABLE_SCLK_TOP1_FSYS11, 450 }; 451 452 static struct samsung_mux_clock top1_mux_clks[] __initdata = { 453 MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p, 454 MUX_SEL_TOP10, 4, 1), 455 MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p, 456 MUX_SEL_TOP10, 8, 1), 457 MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p, 458 MUX_SEL_TOP10, 12, 1), 459 MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p, 460 MUX_SEL_TOP10, 16, 1), 461 462 MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p, 463 MUX_SEL_TOP11, 4, 1), 464 MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p, 465 MUX_SEL_TOP11, 8, 1), 466 MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p, 467 MUX_SEL_TOP11, 12, 1), 468 MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p, 469 MUX_SEL_TOP11, 16, 1), 470 471 MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2), 472 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2), 473 474 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2), 475 MUX(0, "mout_sclk_usbdrd300", mout_top1_group1, 476 MUX_SEL_TOP1_FSYS0, 28, 2), 477 478 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2), 479 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2), 480 }; 481 482 static struct samsung_div_clock top1_div_clks[] __initdata = { 483 DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200", 484 DIV_TOP13, 24, 4), 485 DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", 486 DIV_TOP13, 28, 4), 487 488 DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2", 489 DIV_TOP1_FSYS0, 16, 10), 490 DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300", 491 DIV_TOP1_FSYS0, 28, 4), 492 493 DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1", 494 DIV_TOP1_FSYS11, 0, 10), 495 DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0", 496 DIV_TOP1_FSYS11, 12, 10), 497 }; 498 499 static struct samsung_gate_clock top1_gate_clks[] __initdata = { 500 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", 501 ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0), 502 GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300", 503 ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0), 504 505 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1", 506 ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0), 507 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0", 508 ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0), 509 }; 510 511 static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { 512 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user", 513 1, 2, 0), 514 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user", 515 1, 2, 0), 516 FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0), 517 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0), 518 }; 519 520 static struct samsung_cmu_info top1_cmu_info __initdata = { 521 .mux_clks = top1_mux_clks, 522 .nr_mux_clks = ARRAY_SIZE(top1_mux_clks), 523 .div_clks = top1_div_clks, 524 .nr_div_clks = ARRAY_SIZE(top1_div_clks), 525 .gate_clks = top1_gate_clks, 526 .nr_gate_clks = ARRAY_SIZE(top1_gate_clks), 527 .fixed_factor_clks = top1_fixed_factor_clks, 528 .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks), 529 .nr_clk_ids = TOP1_NR_CLK, 530 .clk_regs = top1_clk_regs, 531 .nr_clk_regs = ARRAY_SIZE(top1_clk_regs), 532 }; 533 534 static void __init exynos7_clk_top1_init(struct device_node *np) 535 { 536 samsung_cmu_register_one(np, &top1_cmu_info); 537 } 538 539 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", 540 exynos7_clk_top1_init); 541 542 /* Register Offset definitions for CMU_CCORE (0x105B0000) */ 543 #define MUX_SEL_CCORE 0x0200 544 #define DIV_CCORE 0x0600 545 #define ENABLE_ACLK_CCORE0 0x0800 546 #define ENABLE_ACLK_CCORE1 0x0804 547 #define ENABLE_PCLK_CCORE 0x0900 548 549 /* 550 * List of parent clocks for Muxes in CMU_CCORE 551 */ 552 PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" }; 553 554 static unsigned long ccore_clk_regs[] __initdata = { 555 MUX_SEL_CCORE, 556 ENABLE_PCLK_CCORE, 557 }; 558 559 static struct samsung_mux_clock ccore_mux_clks[] __initdata = { 560 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p, 561 MUX_SEL_CCORE, 1, 1), 562 }; 563 564 static struct samsung_gate_clock ccore_gate_clks[] __initdata = { 565 GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user", 566 ENABLE_PCLK_CCORE, 8, 0, 0), 567 }; 568 569 static struct samsung_cmu_info ccore_cmu_info __initdata = { 570 .mux_clks = ccore_mux_clks, 571 .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks), 572 .gate_clks = ccore_gate_clks, 573 .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks), 574 .nr_clk_ids = CCORE_NR_CLK, 575 .clk_regs = ccore_clk_regs, 576 .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs), 577 }; 578 579 static void __init exynos7_clk_ccore_init(struct device_node *np) 580 { 581 samsung_cmu_register_one(np, &ccore_cmu_info); 582 } 583 584 CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", 585 exynos7_clk_ccore_init); 586 587 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ 588 #define MUX_SEL_PERIC0 0x0200 589 #define ENABLE_PCLK_PERIC0 0x0900 590 #define ENABLE_SCLK_PERIC0 0x0A00 591 592 /* List of parent clocks for Muxes in CMU_PERIC0 */ 593 PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" }; 594 PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" }; 595 596 static unsigned long peric0_clk_regs[] __initdata = { 597 MUX_SEL_PERIC0, 598 ENABLE_PCLK_PERIC0, 599 ENABLE_SCLK_PERIC0, 600 }; 601 602 static struct samsung_mux_clock peric0_mux_clks[] __initdata = { 603 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p, 604 MUX_SEL_PERIC0, 0, 1), 605 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p, 606 MUX_SEL_PERIC0, 16, 1), 607 }; 608 609 static struct samsung_gate_clock peric0_gate_clks[] __initdata = { 610 GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user", 611 ENABLE_PCLK_PERIC0, 8, 0, 0), 612 GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user", 613 ENABLE_PCLK_PERIC0, 9, 0, 0), 614 GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user", 615 ENABLE_PCLK_PERIC0, 10, 0, 0), 616 GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user", 617 ENABLE_PCLK_PERIC0, 11, 0, 0), 618 GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user", 619 ENABLE_PCLK_PERIC0, 12, 0, 0), 620 GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user", 621 ENABLE_PCLK_PERIC0, 13, 0, 0), 622 GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user", 623 ENABLE_PCLK_PERIC0, 14, 0, 0), 624 GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", 625 ENABLE_PCLK_PERIC0, 16, 0, 0), 626 GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user", 627 ENABLE_PCLK_PERIC0, 20, 0, 0), 628 GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user", 629 ENABLE_PCLK_PERIC0, 21, 0, 0), 630 631 GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user", 632 ENABLE_SCLK_PERIC0, 16, 0, 0), 633 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), 634 }; 635 636 static struct samsung_cmu_info peric0_cmu_info __initdata = { 637 .mux_clks = peric0_mux_clks, 638 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 639 .gate_clks = peric0_gate_clks, 640 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), 641 .nr_clk_ids = PERIC0_NR_CLK, 642 .clk_regs = peric0_clk_regs, 643 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 644 }; 645 646 static void __init exynos7_clk_peric0_init(struct device_node *np) 647 { 648 samsung_cmu_register_one(np, &peric0_cmu_info); 649 } 650 651 /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ 652 #define MUX_SEL_PERIC10 0x0200 653 #define MUX_SEL_PERIC11 0x0204 654 #define MUX_SEL_PERIC12 0x0208 655 #define ENABLE_PCLK_PERIC1 0x0900 656 #define ENABLE_SCLK_PERIC10 0x0A00 657 658 CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", 659 exynos7_clk_peric0_init); 660 661 /* List of parent clocks for Muxes in CMU_PERIC1 */ 662 PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" }; 663 PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" }; 664 PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" }; 665 PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" }; 666 PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" }; 667 PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" }; 668 PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" }; 669 PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" }; 670 PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" }; 671 672 static unsigned long peric1_clk_regs[] __initdata = { 673 MUX_SEL_PERIC10, 674 MUX_SEL_PERIC11, 675 MUX_SEL_PERIC12, 676 ENABLE_PCLK_PERIC1, 677 ENABLE_SCLK_PERIC10, 678 }; 679 680 static struct samsung_mux_clock peric1_mux_clks[] __initdata = { 681 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p, 682 MUX_SEL_PERIC10, 0, 1), 683 684 MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p, 685 MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0), 686 MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p, 687 MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0), 688 MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p, 689 MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0), 690 MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p, 691 MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0), 692 MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p, 693 MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0), 694 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p, 695 MUX_SEL_PERIC11, 20, 1), 696 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p, 697 MUX_SEL_PERIC11, 24, 1), 698 MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p, 699 MUX_SEL_PERIC11, 28, 1), 700 }; 701 702 static struct samsung_gate_clock peric1_gate_clks[] __initdata = { 703 GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user", 704 ENABLE_PCLK_PERIC1, 4, 0, 0), 705 GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user", 706 ENABLE_PCLK_PERIC1, 5, 0, 0), 707 GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user", 708 ENABLE_PCLK_PERIC1, 6, 0, 0), 709 GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user", 710 ENABLE_PCLK_PERIC1, 7, 0, 0), 711 GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user", 712 ENABLE_PCLK_PERIC1, 8, 0, 0), 713 GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user", 714 ENABLE_PCLK_PERIC1, 9, 0, 0), 715 GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user", 716 ENABLE_PCLK_PERIC1, 10, 0, 0), 717 GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user", 718 ENABLE_PCLK_PERIC1, 11, 0, 0), 719 GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user", 720 ENABLE_PCLK_PERIC1, 12, 0, 0), 721 GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user", 722 ENABLE_PCLK_PERIC1, 13, 0, 0), 723 GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user", 724 ENABLE_PCLK_PERIC1, 14, 0, 0), 725 GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user", 726 ENABLE_PCLK_PERIC1, 15, 0, 0), 727 GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user", 728 ENABLE_PCLK_PERIC1, 16, 0, 0), 729 GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user", 730 ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0), 731 GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user", 732 ENABLE_PCLK_PERIC1, 18, 0, 0), 733 GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user", 734 ENABLE_PCLK_PERIC1, 19, 0, 0), 735 736 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", 737 ENABLE_SCLK_PERIC10, 9, 0, 0), 738 GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user", 739 ENABLE_SCLK_PERIC10, 10, 0, 0), 740 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user", 741 ENABLE_SCLK_PERIC10, 11, 0, 0), 742 GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user", 743 ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0), 744 GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user", 745 ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0), 746 GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user", 747 ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0), 748 GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user", 749 ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0), 750 GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user", 751 ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0), 752 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1", 753 ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0), 754 GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1", 755 ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0), 756 GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif", 757 ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0), 758 }; 759 760 static struct samsung_cmu_info peric1_cmu_info __initdata = { 761 .mux_clks = peric1_mux_clks, 762 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 763 .gate_clks = peric1_gate_clks, 764 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), 765 .nr_clk_ids = PERIC1_NR_CLK, 766 .clk_regs = peric1_clk_regs, 767 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 768 }; 769 770 static void __init exynos7_clk_peric1_init(struct device_node *np) 771 { 772 samsung_cmu_register_one(np, &peric1_cmu_info); 773 } 774 775 CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", 776 exynos7_clk_peric1_init); 777 778 /* Register Offset definitions for CMU_PERIS (0x10040000) */ 779 #define MUX_SEL_PERIS 0x0200 780 #define ENABLE_PCLK_PERIS 0x0900 781 #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910 782 #define ENABLE_SCLK_PERIS 0x0A00 783 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10 784 785 /* List of parent clocks for Muxes in CMU_PERIS */ 786 PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" }; 787 788 static unsigned long peris_clk_regs[] __initdata = { 789 MUX_SEL_PERIS, 790 ENABLE_PCLK_PERIS, 791 ENABLE_PCLK_PERIS_SECURE_CHIPID, 792 ENABLE_SCLK_PERIS, 793 ENABLE_SCLK_PERIS_SECURE_CHIPID, 794 }; 795 796 static struct samsung_mux_clock peris_mux_clks[] __initdata = { 797 MUX(0, "mout_aclk_peris_66_user", 798 mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1), 799 }; 800 801 static struct samsung_gate_clock peris_gate_clks[] __initdata = { 802 GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user", 803 ENABLE_PCLK_PERIS, 6, 0, 0), 804 GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user", 805 ENABLE_PCLK_PERIS, 10, 0, 0), 806 807 GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user", 808 ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 809 GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll", 810 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 811 812 GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), 813 }; 814 815 static struct samsung_cmu_info peris_cmu_info __initdata = { 816 .mux_clks = peris_mux_clks, 817 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), 818 .gate_clks = peris_gate_clks, 819 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 820 .nr_clk_ids = PERIS_NR_CLK, 821 .clk_regs = peris_clk_regs, 822 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 823 }; 824 825 static void __init exynos7_clk_peris_init(struct device_node *np) 826 { 827 samsung_cmu_register_one(np, &peris_cmu_info); 828 } 829 830 CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", 831 exynos7_clk_peris_init); 832 833 /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */ 834 #define MUX_SEL_FSYS00 0x0200 835 #define MUX_SEL_FSYS01 0x0204 836 #define MUX_SEL_FSYS02 0x0208 837 #define ENABLE_ACLK_FSYS00 0x0800 838 #define ENABLE_ACLK_FSYS01 0x0804 839 #define ENABLE_SCLK_FSYS01 0x0A04 840 #define ENABLE_SCLK_FSYS02 0x0A08 841 #define ENABLE_SCLK_FSYS04 0x0A10 842 843 /* 844 * List of parent clocks for Muxes in CMU_FSYS0 845 */ 846 PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" }; 847 PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" }; 848 849 PNAME(mout_sclk_usbdrd300_p) = { "fin_pll", "sclk_usbdrd300" }; 850 PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p) = { "fin_pll", 851 "phyclk_usbdrd300_udrd30_phyclock" }; 852 PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p) = { "fin_pll", 853 "phyclk_usbdrd300_udrd30_pipe_pclk" }; 854 855 /* fixed rate clocks used in the FSYS0 block */ 856 struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = { 857 FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 858 CLK_IS_ROOT, 60000000), 859 FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 860 CLK_IS_ROOT, 125000000), 861 }; 862 863 static unsigned long fsys0_clk_regs[] __initdata = { 864 MUX_SEL_FSYS00, 865 MUX_SEL_FSYS01, 866 MUX_SEL_FSYS02, 867 ENABLE_ACLK_FSYS00, 868 ENABLE_ACLK_FSYS01, 869 ENABLE_SCLK_FSYS01, 870 ENABLE_SCLK_FSYS02, 871 ENABLE_SCLK_FSYS04, 872 }; 873 874 static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { 875 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p, 876 MUX_SEL_FSYS00, 24, 1), 877 878 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1), 879 MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p, 880 MUX_SEL_FSYS01, 28, 1), 881 882 MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", 883 mout_phyclk_usbdrd300_udrd30_pipe_pclk_p, 884 MUX_SEL_FSYS02, 24, 1), 885 MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user", 886 mout_phyclk_usbdrd300_udrd30_phyclk_p, 887 MUX_SEL_FSYS02, 28, 1), 888 }; 889 890 static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { 891 GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user", 892 ENABLE_ACLK_FSYS00, 3, 0, 0), 893 GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user", 894 ENABLE_ACLK_FSYS00, 4, 0, 0), 895 GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", 896 "mout_aclk_fsys0_200_user", 897 ENABLE_ACLK_FSYS00, 19, 0, 0), 898 899 GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user", 900 ENABLE_ACLK_FSYS01, 29, 0, 0), 901 GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user", 902 ENABLE_ACLK_FSYS01, 31, 0, 0), 903 904 GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk", 905 "mout_sclk_usbdrd300_user", 906 ENABLE_SCLK_FSYS01, 4, 0, 0), 907 GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll", 908 ENABLE_SCLK_FSYS01, 8, 0, 0), 909 910 GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER, 911 "phyclk_usbdrd300_udrd30_pipe_pclk_user", 912 "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", 913 ENABLE_SCLK_FSYS02, 24, 0, 0), 914 GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER, 915 "phyclk_usbdrd300_udrd30_phyclk_user", 916 "mout_phyclk_usbdrd300_udrd30_phyclk_user", 917 ENABLE_SCLK_FSYS02, 28, 0, 0), 918 919 GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy", 920 "fin_pll", 921 ENABLE_SCLK_FSYS04, 28, 0, 0), 922 }; 923 924 static struct samsung_cmu_info fsys0_cmu_info __initdata = { 925 .mux_clks = fsys0_mux_clks, 926 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), 927 .gate_clks = fsys0_gate_clks, 928 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), 929 .nr_clk_ids = FSYS0_NR_CLK, 930 .clk_regs = fsys0_clk_regs, 931 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), 932 }; 933 934 static void __init exynos7_clk_fsys0_init(struct device_node *np) 935 { 936 samsung_cmu_register_one(np, &fsys0_cmu_info); 937 } 938 939 CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", 940 exynos7_clk_fsys0_init); 941 942 /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ 943 #define MUX_SEL_FSYS10 0x0200 944 #define MUX_SEL_FSYS11 0x0204 945 #define ENABLE_ACLK_FSYS1 0x0800 946 947 /* 948 * List of parent clocks for Muxes in CMU_FSYS1 949 */ 950 PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" }; 951 PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" }; 952 PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" }; 953 954 static unsigned long fsys1_clk_regs[] __initdata = { 955 MUX_SEL_FSYS10, 956 MUX_SEL_FSYS11, 957 ENABLE_ACLK_FSYS1, 958 }; 959 960 static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { 961 MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p, 962 MUX_SEL_FSYS10, 28, 1), 963 964 MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1), 965 MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1), 966 }; 967 968 static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { 969 GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user", 970 ENABLE_ACLK_FSYS1, 29, 0, 0), 971 GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user", 972 ENABLE_ACLK_FSYS1, 30, 0, 0), 973 }; 974 975 static struct samsung_cmu_info fsys1_cmu_info __initdata = { 976 .mux_clks = fsys1_mux_clks, 977 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), 978 .gate_clks = fsys1_gate_clks, 979 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), 980 .nr_clk_ids = FSYS1_NR_CLK, 981 .clk_regs = fsys1_clk_regs, 982 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), 983 }; 984 985 static void __init exynos7_clk_fsys1_init(struct device_node *np) 986 { 987 samsung_cmu_register_one(np, &fsys1_cmu_info); 988 } 989 990 CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", 991 exynos7_clk_fsys1_init); 992 993 #define MUX_SEL_MSCL 0x0200 994 #define DIV_MSCL 0x0600 995 #define ENABLE_ACLK_MSCL 0x0800 996 #define ENABLE_PCLK_MSCL 0x0900 997 998 /* List of parent clocks for Muxes in CMU_MSCL */ 999 PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" }; 1000 1001 static unsigned long mscl_clk_regs[] __initdata = { 1002 MUX_SEL_MSCL, 1003 DIV_MSCL, 1004 ENABLE_ACLK_MSCL, 1005 ENABLE_PCLK_MSCL, 1006 }; 1007 1008 static struct samsung_mux_clock mscl_mux_clks[] __initdata = { 1009 MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532", 1010 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1), 1011 }; 1012 static struct samsung_div_clock mscl_div_clks[] __initdata = { 1013 DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532", 1014 DIV_MSCL, 0, 3), 1015 }; 1016 static struct samsung_gate_clock mscl_gate_clks[] __initdata = { 1017 1018 GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532", 1019 ENABLE_ACLK_MSCL, 31, 0, 0), 1020 GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532", 1021 ENABLE_ACLK_MSCL, 30, 0, 0), 1022 GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532", 1023 ENABLE_ACLK_MSCL, 29, 0, 0), 1024 GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532", 1025 ENABLE_ACLK_MSCL, 28, 0, 0), 1026 GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0", 1027 "usermux_aclk_mscl_532", 1028 ENABLE_ACLK_MSCL, 27, 0, 0), 1029 GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1", 1030 "usermux_aclk_mscl_532", 1031 ENABLE_ACLK_MSCL, 26, 0, 0), 1032 GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532", 1033 ENABLE_ACLK_MSCL, 25, 0, 0), 1034 GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532", 1035 ENABLE_ACLK_MSCL, 24, 0, 0), 1036 GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge", 1037 "usermux_aclk_mscl_532", 1038 ENABLE_ACLK_MSCL, 23, 0, 0), 1039 GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532", 1040 ENABLE_ACLK_MSCL, 22, 0, 0), 1041 GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532", 1042 ENABLE_ACLK_MSCL, 21, 0, 0), 1043 GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532", 1044 ENABLE_ACLK_MSCL, 20, 0, 0), 1045 GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532", 1046 ENABLE_ACLK_MSCL, 19, 0, 0), 1047 GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532", 1048 ENABLE_ACLK_MSCL, 18, 0, 0), 1049 GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532", 1050 ENABLE_ACLK_MSCL, 17, 0, 0), 1051 GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532", 1052 ENABLE_ACLK_MSCL, 16, 0, 0), 1053 GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p", 1054 "usermux_aclk_mscl_532", 1055 ENABLE_ACLK_MSCL, 15, 0, 0), 1056 GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p", 1057 "usermux_aclk_mscl_532", 1058 ENABLE_ACLK_MSCL, 14, 0, 0), 1059 1060 GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl", 1061 ENABLE_PCLK_MSCL, 31, 0, 0), 1062 GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl", 1063 ENABLE_PCLK_MSCL, 30, 0, 0), 1064 GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl", 1065 ENABLE_PCLK_MSCL, 29, 0, 0), 1066 GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl", 1067 ENABLE_PCLK_MSCL, 28, 0, 0), 1068 GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl", 1069 ENABLE_PCLK_MSCL, 27, 0, 0), 1070 GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl", 1071 ENABLE_PCLK_MSCL, 26, 0, 0), 1072 GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl", 1073 ENABLE_PCLK_MSCL, 25, 0, 0), 1074 GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl", 1075 ENABLE_PCLK_MSCL, 24, 0, 0), 1076 GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl", 1077 ENABLE_PCLK_MSCL, 23, 0, 0), 1078 GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl", 1079 ENABLE_PCLK_MSCL, 22, 0, 0), 1080 GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl", 1081 ENABLE_PCLK_MSCL, 21, 0, 0), 1082 GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl", 1083 ENABLE_PCLK_MSCL, 20, 0, 0), 1084 }; 1085 1086 static struct samsung_cmu_info mscl_cmu_info __initdata = { 1087 .mux_clks = mscl_mux_clks, 1088 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 1089 .div_clks = mscl_div_clks, 1090 .nr_div_clks = ARRAY_SIZE(mscl_div_clks), 1091 .gate_clks = mscl_gate_clks, 1092 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), 1093 .nr_clk_ids = MSCL_NR_CLK, 1094 .clk_regs = mscl_clk_regs, 1095 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), 1096 }; 1097 1098 static void __init exynos7_clk_mscl_init(struct device_node *np) 1099 { 1100 samsung_cmu_register_one(np, &mscl_cmu_info); 1101 } 1102 1103 CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl", 1104 exynos7_clk_mscl_init); 1105 1106 /* Register Offset definitions for CMU_AUD (0x114C0000) */ 1107 #define MUX_SEL_AUD 0x0200 1108 #define DIV_AUD0 0x0600 1109 #define DIV_AUD1 0x0604 1110 #define ENABLE_ACLK_AUD 0x0800 1111 #define ENABLE_PCLK_AUD 0x0900 1112 #define ENABLE_SCLK_AUD 0x0A00 1113 1114 /* 1115 * List of parent clocks for Muxes in CMU_AUD 1116 */ 1117 PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" }; 1118 PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" }; 1119 1120 static unsigned long aud_clk_regs[] __initdata = { 1121 MUX_SEL_AUD, 1122 DIV_AUD0, 1123 DIV_AUD1, 1124 ENABLE_ACLK_AUD, 1125 ENABLE_PCLK_AUD, 1126 ENABLE_SCLK_AUD, 1127 }; 1128 1129 static struct samsung_mux_clock aud_mux_clks[] __initdata = { 1130 MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1), 1131 MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1), 1132 MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1), 1133 }; 1134 1135 static struct samsung_div_clock aud_div_clks[] __initdata = { 1136 DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4), 1137 DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4), 1138 DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4), 1139 1140 DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4), 1141 DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8), 1142 DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4), 1143 DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5), 1144 DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4), 1145 }; 1146 1147 static struct samsung_gate_clock aud_gate_clks[] __initdata = { 1148 GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm", 1149 ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 1150 GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s", 1151 ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0), 1152 GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0), 1153 GATE(0, "sclk_slimbus", "dout_sclk_slimbus", 1154 ENABLE_SCLK_AUD, 30, 0, 0), 1155 1156 GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0), 1157 GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0), 1158 GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0), 1159 GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0), 1160 GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0), 1161 GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0), 1162 GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud", 1163 ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0), 1164 GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud", 1165 ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 1166 GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0), 1167 GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0), 1168 1169 GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0), 1170 GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud", 1171 ENABLE_ACLK_AUD, 28, 0, 0), 1172 GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0), 1173 }; 1174 1175 static struct samsung_cmu_info aud_cmu_info __initdata = { 1176 .mux_clks = aud_mux_clks, 1177 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 1178 .div_clks = aud_div_clks, 1179 .nr_div_clks = ARRAY_SIZE(aud_div_clks), 1180 .gate_clks = aud_gate_clks, 1181 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 1182 .nr_clk_ids = AUD_NR_CLK, 1183 .clk_regs = aud_clk_regs, 1184 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 1185 }; 1186 1187 static void __init exynos7_clk_aud_init(struct device_node *np) 1188 { 1189 samsung_cmu_register_one(np, &aud_cmu_info); 1190 } 1191 1192 CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud", 1193 exynos7_clk_aud_init); 1194