1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/clkdev.h> 13 #include <linux/clk-provider.h> 14 #include <linux/of.h> 15 16 #include "clk.h" 17 #include <dt-bindings/clock/exynos7-clk.h> 18 19 /* Register Offset definitions for CMU_TOPC (0x10570000) */ 20 #define CC_PLL_LOCK 0x0000 21 #define BUS0_PLL_LOCK 0x0004 22 #define BUS1_DPLL_LOCK 0x0008 23 #define MFC_PLL_LOCK 0x000C 24 #define AUD_PLL_LOCK 0x0010 25 #define CC_PLL_CON0 0x0100 26 #define BUS0_PLL_CON0 0x0110 27 #define BUS1_DPLL_CON0 0x0120 28 #define MFC_PLL_CON0 0x0130 29 #define AUD_PLL_CON0 0x0140 30 #define MUX_SEL_TOPC0 0x0200 31 #define MUX_SEL_TOPC1 0x0204 32 #define MUX_SEL_TOPC2 0x0208 33 #define MUX_SEL_TOPC3 0x020C 34 #define DIV_TOPC0 0x0600 35 #define DIV_TOPC1 0x0604 36 #define DIV_TOPC3 0x060C 37 #define ENABLE_ACLK_TOPC1 0x0804 38 39 static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = { 40 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0), 41 FFACTOR(0, "ffac_topc_bus0_pll_div4", 42 "ffac_topc_bus0_pll_div2", 1, 2, 0), 43 FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0), 44 FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0), 45 FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0), 46 }; 47 48 /* List of parent clocks for Muxes in CMU_TOPC */ 49 PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; 50 PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; 51 PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; 52 PNAME(mout_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; 53 54 PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc", 55 "mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc", 56 "mout_sclk_mfc_pll_cmuc" }; 57 58 PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl", 59 "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"}; 60 PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl", 61 "ffac_topc_bus1_pll_div2"}; 62 PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl", 63 "ffac_topc_cc_pll_div2"}; 64 PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl", 65 "ffac_topc_mfc_pll_div2"}; 66 67 68 PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl", 69 "ffac_topc_bus0_pll_div2"}; 70 71 static unsigned long topc_clk_regs[] __initdata = { 72 CC_PLL_LOCK, 73 BUS0_PLL_LOCK, 74 BUS1_DPLL_LOCK, 75 MFC_PLL_LOCK, 76 AUD_PLL_LOCK, 77 CC_PLL_CON0, 78 BUS0_PLL_CON0, 79 BUS1_DPLL_CON0, 80 MFC_PLL_CON0, 81 AUD_PLL_CON0, 82 MUX_SEL_TOPC0, 83 MUX_SEL_TOPC1, 84 MUX_SEL_TOPC2, 85 MUX_SEL_TOPC3, 86 DIV_TOPC0, 87 DIV_TOPC1, 88 DIV_TOPC3, 89 }; 90 91 static struct samsung_mux_clock topc_mux_clks[] __initdata = { 92 MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1), 93 MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1), 94 MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1), 95 MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1), 96 97 MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p, 98 MUX_SEL_TOPC0, 16, 2), 99 MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p, 100 MUX_SEL_TOPC0, 20, 1), 101 MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p, 102 MUX_SEL_TOPC0, 24, 1), 103 MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p, 104 MUX_SEL_TOPC0, 28, 1), 105 106 MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p, 107 MUX_SEL_TOPC1, 16, 1), 108 109 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), 110 111 MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2), 112 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), 113 }; 114 115 static struct samsung_div_clock topc_div_clks[] __initdata = { 116 DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133", 117 DIV_TOPC0, 4, 4), 118 119 DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532", 120 DIV_TOPC1, 20, 4), 121 DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", 122 DIV_TOPC1, 24, 4), 123 124 DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out", 125 DIV_TOPC3, 0, 3), 126 DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl", 127 DIV_TOPC3, 8, 3), 128 DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl", 129 DIV_TOPC3, 12, 3), 130 DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl", 131 DIV_TOPC3, 16, 3), 132 }; 133 134 static struct samsung_gate_clock topc_gate_clks[] __initdata = { 135 GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532", 136 ENABLE_ACLK_TOPC1, 20, 0, 0), 137 }; 138 139 static struct samsung_pll_clock topc_pll_clks[] __initdata = { 140 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK, 141 BUS0_PLL_CON0, NULL), 142 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK, 143 CC_PLL_CON0, NULL), 144 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK, 145 BUS1_DPLL_CON0, NULL), 146 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK, 147 MFC_PLL_CON0, NULL), 148 PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, 149 AUD_PLL_CON0, NULL), 150 }; 151 152 static struct samsung_cmu_info topc_cmu_info __initdata = { 153 .pll_clks = topc_pll_clks, 154 .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), 155 .mux_clks = topc_mux_clks, 156 .nr_mux_clks = ARRAY_SIZE(topc_mux_clks), 157 .div_clks = topc_div_clks, 158 .nr_div_clks = ARRAY_SIZE(topc_div_clks), 159 .gate_clks = topc_gate_clks, 160 .nr_gate_clks = ARRAY_SIZE(topc_gate_clks), 161 .fixed_factor_clks = topc_fixed_factor_clks, 162 .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks), 163 .nr_clk_ids = TOPC_NR_CLK, 164 .clk_regs = topc_clk_regs, 165 .nr_clk_regs = ARRAY_SIZE(topc_clk_regs), 166 }; 167 168 static void __init exynos7_clk_topc_init(struct device_node *np) 169 { 170 samsung_cmu_register_one(np, &topc_cmu_info); 171 } 172 173 CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", 174 exynos7_clk_topc_init); 175 176 /* Register Offset definitions for CMU_TOP0 (0x105D0000) */ 177 #define MUX_SEL_TOP00 0x0200 178 #define MUX_SEL_TOP01 0x0204 179 #define MUX_SEL_TOP03 0x020C 180 #define MUX_SEL_TOP0_PERIC3 0x023C 181 #define DIV_TOP03 0x060C 182 #define DIV_TOP0_PERIC3 0x063C 183 #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C 184 185 /* List of parent clocks for Muxes in CMU_TOP0 */ 186 PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; 187 PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" }; 188 PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" }; 189 PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" }; 190 191 PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll", 192 "ffac_top0_bus0_pll_div2"}; 193 PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll", 194 "ffac_top0_bus1_pll_div2"}; 195 PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll", 196 "ffac_top0_cc_pll_div2"}; 197 PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll", 198 "ffac_top0_mfc_pll_div2"}; 199 200 PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll", 201 "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll", 202 "mout_top0_half_mfc_pll"}; 203 204 static unsigned long top0_clk_regs[] __initdata = { 205 MUX_SEL_TOP00, 206 MUX_SEL_TOP01, 207 MUX_SEL_TOP03, 208 MUX_SEL_TOP0_PERIC3, 209 DIV_TOP03, 210 DIV_TOP0_PERIC3, 211 ENABLE_SCLK_TOP0_PERIC3, 212 }; 213 214 static struct samsung_mux_clock top0_mux_clks[] __initdata = { 215 MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1), 216 MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1), 217 MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1), 218 MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1), 219 220 MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p, 221 MUX_SEL_TOP01, 4, 1), 222 MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p, 223 MUX_SEL_TOP01, 8, 1), 224 MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p, 225 MUX_SEL_TOP01, 12, 1), 226 MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p, 227 MUX_SEL_TOP01, 16, 1), 228 229 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), 230 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), 231 232 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2), 233 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2), 234 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2), 235 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2), 236 }; 237 238 static struct samsung_div_clock top0_div_clks[] __initdata = { 239 DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66", 240 DIV_TOP03, 12, 6), 241 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", 242 DIV_TOP03, 20, 6), 243 244 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4), 245 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4), 246 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4), 247 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4), 248 }; 249 250 static struct samsung_gate_clock top0_gate_clks[] __initdata = { 251 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3", 252 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0), 253 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2", 254 ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0), 255 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1", 256 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0), 257 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0", 258 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0), 259 }; 260 261 static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = { 262 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0), 263 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0), 264 FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0), 265 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0), 266 }; 267 268 static struct samsung_cmu_info top0_cmu_info __initdata = { 269 .mux_clks = top0_mux_clks, 270 .nr_mux_clks = ARRAY_SIZE(top0_mux_clks), 271 .div_clks = top0_div_clks, 272 .nr_div_clks = ARRAY_SIZE(top0_div_clks), 273 .gate_clks = top0_gate_clks, 274 .nr_gate_clks = ARRAY_SIZE(top0_gate_clks), 275 .fixed_factor_clks = top0_fixed_factor_clks, 276 .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks), 277 .nr_clk_ids = TOP0_NR_CLK, 278 .clk_regs = top0_clk_regs, 279 .nr_clk_regs = ARRAY_SIZE(top0_clk_regs), 280 }; 281 282 static void __init exynos7_clk_top0_init(struct device_node *np) 283 { 284 samsung_cmu_register_one(np, &top0_cmu_info); 285 } 286 287 CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", 288 exynos7_clk_top0_init); 289 290 /* Register Offset definitions for CMU_TOP1 (0x105E0000) */ 291 #define MUX_SEL_TOP10 0x0200 292 #define MUX_SEL_TOP11 0x0204 293 #define MUX_SEL_TOP13 0x020C 294 #define MUX_SEL_TOP1_FSYS0 0x0224 295 #define MUX_SEL_TOP1_FSYS1 0x0228 296 #define DIV_TOP13 0x060C 297 #define DIV_TOP1_FSYS0 0x0624 298 #define DIV_TOP1_FSYS1 0x0628 299 #define ENABLE_ACLK_TOP13 0x080C 300 #define ENABLE_SCLK_TOP1_FSYS0 0x0A24 301 #define ENABLE_SCLK_TOP1_FSYS1 0x0A28 302 303 /* List of parent clocks for Muxes in CMU_TOP1 */ 304 PNAME(mout_top1_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" }; 305 PNAME(mout_top1_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll_b" }; 306 PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" }; 307 PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" }; 308 309 PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll", 310 "ffac_top1_bus0_pll_div2"}; 311 PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll", 312 "ffac_top1_bus1_pll_div2"}; 313 PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll", 314 "ffac_top1_cc_pll_div2"}; 315 PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll", 316 "ffac_top1_mfc_pll_div2"}; 317 318 PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll", 319 "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll", 320 "mout_top1_half_mfc_pll"}; 321 322 static unsigned long top1_clk_regs[] __initdata = { 323 MUX_SEL_TOP10, 324 MUX_SEL_TOP11, 325 MUX_SEL_TOP13, 326 MUX_SEL_TOP1_FSYS0, 327 MUX_SEL_TOP1_FSYS1, 328 DIV_TOP13, 329 DIV_TOP1_FSYS0, 330 DIV_TOP1_FSYS1, 331 ENABLE_ACLK_TOP13, 332 ENABLE_SCLK_TOP1_FSYS0, 333 ENABLE_SCLK_TOP1_FSYS1, 334 }; 335 336 static struct samsung_mux_clock top1_mux_clks[] __initdata = { 337 MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1), 338 MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1), 339 MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p, 340 MUX_SEL_TOP10, 12, 1), 341 MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p, 342 MUX_SEL_TOP10, 16, 1), 343 344 MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p, 345 MUX_SEL_TOP11, 4, 1), 346 MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p, 347 MUX_SEL_TOP11, 8, 1), 348 MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p, 349 MUX_SEL_TOP11, 12, 1), 350 MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p, 351 MUX_SEL_TOP11, 16, 1), 352 353 MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2), 354 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2), 355 356 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2), 357 358 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2), 359 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2), 360 }; 361 362 static struct samsung_div_clock top1_div_clks[] __initdata = { 363 DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200", 364 DIV_TOP13, 24, 4), 365 DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", 366 DIV_TOP13, 28, 4), 367 368 DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2", 369 DIV_TOP1_FSYS0, 24, 4), 370 371 DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1", 372 DIV_TOP1_FSYS1, 24, 4), 373 DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0", 374 DIV_TOP1_FSYS1, 28, 4), 375 }; 376 377 static struct samsung_gate_clock top1_gate_clks[] __initdata = { 378 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", 379 ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0), 380 381 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1", 382 ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0), 383 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0", 384 ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0), 385 }; 386 387 static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = { 388 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0), 389 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0), 390 FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0), 391 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0), 392 }; 393 394 static struct samsung_cmu_info top1_cmu_info __initdata = { 395 .mux_clks = top1_mux_clks, 396 .nr_mux_clks = ARRAY_SIZE(top1_mux_clks), 397 .div_clks = top1_div_clks, 398 .nr_div_clks = ARRAY_SIZE(top1_div_clks), 399 .gate_clks = top1_gate_clks, 400 .nr_gate_clks = ARRAY_SIZE(top1_gate_clks), 401 .fixed_factor_clks = top1_fixed_factor_clks, 402 .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks), 403 .nr_clk_ids = TOP1_NR_CLK, 404 .clk_regs = top1_clk_regs, 405 .nr_clk_regs = ARRAY_SIZE(top1_clk_regs), 406 }; 407 408 static void __init exynos7_clk_top1_init(struct device_node *np) 409 { 410 samsung_cmu_register_one(np, &top1_cmu_info); 411 } 412 413 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", 414 exynos7_clk_top1_init); 415 416 /* Register Offset definitions for CMU_CCORE (0x105B0000) */ 417 #define MUX_SEL_CCORE 0x0200 418 #define DIV_CCORE 0x0600 419 #define ENABLE_ACLK_CCORE0 0x0800 420 #define ENABLE_ACLK_CCORE1 0x0804 421 #define ENABLE_PCLK_CCORE 0x0900 422 423 /* 424 * List of parent clocks for Muxes in CMU_CCORE 425 */ 426 PNAME(mout_aclk_ccore_133_p) = { "fin_pll", "dout_aclk_ccore_133" }; 427 428 static unsigned long ccore_clk_regs[] __initdata = { 429 MUX_SEL_CCORE, 430 ENABLE_PCLK_CCORE, 431 }; 432 433 static struct samsung_mux_clock ccore_mux_clks[] __initdata = { 434 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p, 435 MUX_SEL_CCORE, 1, 1), 436 }; 437 438 static struct samsung_gate_clock ccore_gate_clks[] __initdata = { 439 GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user", 440 ENABLE_PCLK_CCORE, 8, 0, 0), 441 }; 442 443 static struct samsung_cmu_info ccore_cmu_info __initdata = { 444 .mux_clks = ccore_mux_clks, 445 .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks), 446 .gate_clks = ccore_gate_clks, 447 .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks), 448 .nr_clk_ids = CCORE_NR_CLK, 449 .clk_regs = ccore_clk_regs, 450 .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs), 451 }; 452 453 static void __init exynos7_clk_ccore_init(struct device_node *np) 454 { 455 samsung_cmu_register_one(np, &ccore_cmu_info); 456 } 457 458 CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", 459 exynos7_clk_ccore_init); 460 461 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ 462 #define MUX_SEL_PERIC0 0x0200 463 #define ENABLE_PCLK_PERIC0 0x0900 464 #define ENABLE_SCLK_PERIC0 0x0A00 465 466 /* List of parent clocks for Muxes in CMU_PERIC0 */ 467 PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" }; 468 PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" }; 469 470 static unsigned long peric0_clk_regs[] __initdata = { 471 MUX_SEL_PERIC0, 472 ENABLE_PCLK_PERIC0, 473 ENABLE_SCLK_PERIC0, 474 }; 475 476 static struct samsung_mux_clock peric0_mux_clks[] __initdata = { 477 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p, 478 MUX_SEL_PERIC0, 0, 1), 479 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p, 480 MUX_SEL_PERIC0, 16, 1), 481 }; 482 483 static struct samsung_gate_clock peric0_gate_clks[] __initdata = { 484 GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user", 485 ENABLE_PCLK_PERIC0, 8, 0, 0), 486 GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user", 487 ENABLE_PCLK_PERIC0, 9, 0, 0), 488 GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user", 489 ENABLE_PCLK_PERIC0, 10, 0, 0), 490 GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user", 491 ENABLE_PCLK_PERIC0, 11, 0, 0), 492 GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user", 493 ENABLE_PCLK_PERIC0, 12, 0, 0), 494 GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user", 495 ENABLE_PCLK_PERIC0, 13, 0, 0), 496 GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user", 497 ENABLE_PCLK_PERIC0, 14, 0, 0), 498 GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", 499 ENABLE_PCLK_PERIC0, 16, 0, 0), 500 GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user", 501 ENABLE_PCLK_PERIC0, 20, 0, 0), 502 GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user", 503 ENABLE_PCLK_PERIC0, 21, 0, 0), 504 505 GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user", 506 ENABLE_SCLK_PERIC0, 16, 0, 0), 507 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), 508 }; 509 510 static struct samsung_cmu_info peric0_cmu_info __initdata = { 511 .mux_clks = peric0_mux_clks, 512 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 513 .gate_clks = peric0_gate_clks, 514 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), 515 .nr_clk_ids = PERIC0_NR_CLK, 516 .clk_regs = peric0_clk_regs, 517 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 518 }; 519 520 static void __init exynos7_clk_peric0_init(struct device_node *np) 521 { 522 samsung_cmu_register_one(np, &peric0_cmu_info); 523 } 524 525 /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ 526 #define MUX_SEL_PERIC10 0x0200 527 #define MUX_SEL_PERIC11 0x0204 528 #define ENABLE_PCLK_PERIC1 0x0900 529 #define ENABLE_SCLK_PERIC10 0x0A00 530 531 CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", 532 exynos7_clk_peric0_init); 533 534 /* List of parent clocks for Muxes in CMU_PERIC1 */ 535 PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" }; 536 PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" }; 537 PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" }; 538 PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" }; 539 540 static unsigned long peric1_clk_regs[] __initdata = { 541 MUX_SEL_PERIC10, 542 MUX_SEL_PERIC11, 543 ENABLE_PCLK_PERIC1, 544 ENABLE_SCLK_PERIC10, 545 }; 546 547 static struct samsung_mux_clock peric1_mux_clks[] __initdata = { 548 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p, 549 MUX_SEL_PERIC10, 0, 1), 550 551 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p, 552 MUX_SEL_PERIC11, 20, 1), 553 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p, 554 MUX_SEL_PERIC11, 24, 1), 555 MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p, 556 MUX_SEL_PERIC11, 28, 1), 557 }; 558 559 static struct samsung_gate_clock peric1_gate_clks[] __initdata = { 560 GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user", 561 ENABLE_PCLK_PERIC1, 4, 0, 0), 562 GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user", 563 ENABLE_PCLK_PERIC1, 5, 0, 0), 564 GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user", 565 ENABLE_PCLK_PERIC1, 6, 0, 0), 566 GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user", 567 ENABLE_PCLK_PERIC1, 7, 0, 0), 568 GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user", 569 ENABLE_PCLK_PERIC1, 8, 0, 0), 570 GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user", 571 ENABLE_PCLK_PERIC1, 9, 0, 0), 572 GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user", 573 ENABLE_PCLK_PERIC1, 10, 0, 0), 574 GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user", 575 ENABLE_PCLK_PERIC1, 11, 0, 0), 576 577 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", 578 ENABLE_SCLK_PERIC10, 9, 0, 0), 579 GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user", 580 ENABLE_SCLK_PERIC10, 10, 0, 0), 581 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user", 582 ENABLE_SCLK_PERIC10, 11, 0, 0), 583 }; 584 585 static struct samsung_cmu_info peric1_cmu_info __initdata = { 586 .mux_clks = peric1_mux_clks, 587 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 588 .gate_clks = peric1_gate_clks, 589 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), 590 .nr_clk_ids = PERIC1_NR_CLK, 591 .clk_regs = peric1_clk_regs, 592 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 593 }; 594 595 static void __init exynos7_clk_peric1_init(struct device_node *np) 596 { 597 samsung_cmu_register_one(np, &peric1_cmu_info); 598 } 599 600 CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", 601 exynos7_clk_peric1_init); 602 603 /* Register Offset definitions for CMU_PERIS (0x10040000) */ 604 #define MUX_SEL_PERIS 0x0200 605 #define ENABLE_PCLK_PERIS 0x0900 606 #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910 607 #define ENABLE_SCLK_PERIS 0x0A00 608 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10 609 610 /* List of parent clocks for Muxes in CMU_PERIS */ 611 PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" }; 612 613 static unsigned long peris_clk_regs[] __initdata = { 614 MUX_SEL_PERIS, 615 ENABLE_PCLK_PERIS, 616 ENABLE_PCLK_PERIS_SECURE_CHIPID, 617 ENABLE_SCLK_PERIS, 618 ENABLE_SCLK_PERIS_SECURE_CHIPID, 619 }; 620 621 static struct samsung_mux_clock peris_mux_clks[] __initdata = { 622 MUX(0, "mout_aclk_peris_66_user", 623 mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1), 624 }; 625 626 static struct samsung_gate_clock peris_gate_clks[] __initdata = { 627 GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user", 628 ENABLE_PCLK_PERIS, 6, 0, 0), 629 GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user", 630 ENABLE_PCLK_PERIS, 10, 0, 0), 631 632 GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user", 633 ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 634 GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll", 635 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 636 637 GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), 638 }; 639 640 static struct samsung_cmu_info peris_cmu_info __initdata = { 641 .mux_clks = peris_mux_clks, 642 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), 643 .gate_clks = peris_gate_clks, 644 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 645 .nr_clk_ids = PERIS_NR_CLK, 646 .clk_regs = peris_clk_regs, 647 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 648 }; 649 650 static void __init exynos7_clk_peris_init(struct device_node *np) 651 { 652 samsung_cmu_register_one(np, &peris_cmu_info); 653 } 654 655 CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", 656 exynos7_clk_peris_init); 657 658 /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */ 659 #define MUX_SEL_FSYS00 0x0200 660 #define MUX_SEL_FSYS01 0x0204 661 #define ENABLE_ACLK_FSYS01 0x0804 662 663 /* 664 * List of parent clocks for Muxes in CMU_FSYS0 665 */ 666 PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" }; 667 PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" }; 668 669 static unsigned long fsys0_clk_regs[] __initdata = { 670 MUX_SEL_FSYS00, 671 MUX_SEL_FSYS01, 672 ENABLE_ACLK_FSYS01, 673 }; 674 675 static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { 676 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p, 677 MUX_SEL_FSYS00, 24, 1), 678 679 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1), 680 }; 681 682 static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { 683 GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user", 684 ENABLE_ACLK_FSYS01, 31, 0, 0), 685 }; 686 687 static struct samsung_cmu_info fsys0_cmu_info __initdata = { 688 .mux_clks = fsys0_mux_clks, 689 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), 690 .gate_clks = fsys0_gate_clks, 691 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), 692 .nr_clk_ids = TOP1_NR_CLK, 693 .clk_regs = fsys0_clk_regs, 694 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), 695 }; 696 697 static void __init exynos7_clk_fsys0_init(struct device_node *np) 698 { 699 samsung_cmu_register_one(np, &fsys0_cmu_info); 700 } 701 702 CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", 703 exynos7_clk_fsys0_init); 704 705 /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ 706 #define MUX_SEL_FSYS10 0x0200 707 #define MUX_SEL_FSYS11 0x0204 708 #define ENABLE_ACLK_FSYS1 0x0800 709 710 /* 711 * List of parent clocks for Muxes in CMU_FSYS1 712 */ 713 PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" }; 714 PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" }; 715 PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" }; 716 717 static unsigned long fsys1_clk_regs[] __initdata = { 718 MUX_SEL_FSYS10, 719 MUX_SEL_FSYS11, 720 ENABLE_ACLK_FSYS1, 721 }; 722 723 static struct samsung_mux_clock fsys1_mux_clks[] __initdata = { 724 MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p, 725 MUX_SEL_FSYS10, 28, 1), 726 727 MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1), 728 MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1), 729 }; 730 731 static struct samsung_gate_clock fsys1_gate_clks[] __initdata = { 732 GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user", 733 ENABLE_ACLK_FSYS1, 29, 0, 0), 734 GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user", 735 ENABLE_ACLK_FSYS1, 30, 0, 0), 736 }; 737 738 static struct samsung_cmu_info fsys1_cmu_info __initdata = { 739 .mux_clks = fsys1_mux_clks, 740 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), 741 .gate_clks = fsys1_gate_clks, 742 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), 743 .nr_clk_ids = TOP1_NR_CLK, 744 .clk_regs = fsys1_clk_regs, 745 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), 746 }; 747 748 static void __init exynos7_clk_fsys1_init(struct device_node *np) 749 { 750 samsung_cmu_register_one(np, &fsys1_cmu_info); 751 } 752 753 CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", 754 exynos7_clk_fsys1_init); 755 756 #define MUX_SEL_MSCL 0x0200 757 #define DIV_MSCL 0x0600 758 #define ENABLE_ACLK_MSCL 0x0800 759 #define ENABLE_PCLK_MSCL 0x0900 760 761 /* List of parent clocks for Muxes in CMU_MSCL */ 762 PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" }; 763 764 static unsigned long mscl_clk_regs[] __initdata = { 765 MUX_SEL_MSCL, 766 DIV_MSCL, 767 ENABLE_ACLK_MSCL, 768 ENABLE_PCLK_MSCL, 769 }; 770 771 static struct samsung_mux_clock mscl_mux_clks[] __initdata = { 772 MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532", 773 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1), 774 }; 775 static struct samsung_div_clock mscl_div_clks[] __initdata = { 776 DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532", 777 DIV_MSCL, 0, 3), 778 }; 779 static struct samsung_gate_clock mscl_gate_clks[] __initdata = { 780 781 GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532", 782 ENABLE_ACLK_MSCL, 31, 0, 0), 783 GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532", 784 ENABLE_ACLK_MSCL, 30, 0, 0), 785 GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532", 786 ENABLE_ACLK_MSCL, 29, 0, 0), 787 GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532", 788 ENABLE_ACLK_MSCL, 28, 0, 0), 789 GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0", 790 "usermux_aclk_mscl_532", 791 ENABLE_ACLK_MSCL, 27, 0, 0), 792 GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1", 793 "usermux_aclk_mscl_532", 794 ENABLE_ACLK_MSCL, 26, 0, 0), 795 GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532", 796 ENABLE_ACLK_MSCL, 25, 0, 0), 797 GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532", 798 ENABLE_ACLK_MSCL, 24, 0, 0), 799 GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge", 800 "usermux_aclk_mscl_532", 801 ENABLE_ACLK_MSCL, 23, 0, 0), 802 GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532", 803 ENABLE_ACLK_MSCL, 22, 0, 0), 804 GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532", 805 ENABLE_ACLK_MSCL, 21, 0, 0), 806 GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532", 807 ENABLE_ACLK_MSCL, 20, 0, 0), 808 GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532", 809 ENABLE_ACLK_MSCL, 19, 0, 0), 810 GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532", 811 ENABLE_ACLK_MSCL, 18, 0, 0), 812 GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532", 813 ENABLE_ACLK_MSCL, 17, 0, 0), 814 GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532", 815 ENABLE_ACLK_MSCL, 16, 0, 0), 816 GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p", 817 "usermux_aclk_mscl_532", 818 ENABLE_ACLK_MSCL, 15, 0, 0), 819 GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p", 820 "usermux_aclk_mscl_532", 821 ENABLE_ACLK_MSCL, 14, 0, 0), 822 823 GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl", 824 ENABLE_PCLK_MSCL, 31, 0, 0), 825 GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl", 826 ENABLE_PCLK_MSCL, 30, 0, 0), 827 GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl", 828 ENABLE_PCLK_MSCL, 29, 0, 0), 829 GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl", 830 ENABLE_PCLK_MSCL, 28, 0, 0), 831 GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl", 832 ENABLE_PCLK_MSCL, 27, 0, 0), 833 GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl", 834 ENABLE_PCLK_MSCL, 26, 0, 0), 835 GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl", 836 ENABLE_PCLK_MSCL, 25, 0, 0), 837 GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl", 838 ENABLE_PCLK_MSCL, 24, 0, 0), 839 GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl", 840 ENABLE_PCLK_MSCL, 23, 0, 0), 841 GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl", 842 ENABLE_PCLK_MSCL, 22, 0, 0), 843 GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl", 844 ENABLE_PCLK_MSCL, 21, 0, 0), 845 GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl", 846 ENABLE_PCLK_MSCL, 20, 0, 0), 847 }; 848 849 static struct samsung_cmu_info mscl_cmu_info __initdata = { 850 .mux_clks = mscl_mux_clks, 851 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 852 .div_clks = mscl_div_clks, 853 .nr_div_clks = ARRAY_SIZE(mscl_div_clks), 854 .gate_clks = mscl_gate_clks, 855 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), 856 .nr_clk_ids = MSCL_NR_CLK, 857 .clk_regs = mscl_clk_regs, 858 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), 859 }; 860 861 static void __init exynos7_clk_mscl_init(struct device_node *np) 862 { 863 samsung_cmu_register_one(np, &mscl_cmu_info); 864 } 865 866 CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl", 867 exynos7_clk_mscl_init); 868