1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> 5 * Author: Joseph Chen <chenjh@rock-chips.com> 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 14 #include <dt-bindings/clock/rockchip,rk3528-cru.h> 15 16 #include "clk.h" 17 18 #define RK3528_GRF_SOC_STATUS0 0x1a0 19 20 enum rk3528_plls { 21 apll, cpll, gpll, ppll, dpll, 22 }; 23 24 static struct rockchip_pll_rate_table rk3528_pll_rates[] = { 25 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), 26 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), 27 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), 28 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 29 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 30 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 31 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 32 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 33 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */ 34 RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0), 35 RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0), 36 RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */ 37 RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */ 38 RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0), 39 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), 40 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 41 RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0), 42 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), 43 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), 44 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), 45 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), 46 RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0), 47 { /* sentinel */ }, 48 }; 49 50 #define RK3528_DIV_ACLK_M_CORE_MASK 0x1f 51 #define RK3528_DIV_ACLK_M_CORE_SHIFT 11 52 #define RK3528_DIV_PCLK_DBG_MASK 0x1f 53 #define RK3528_DIV_PCLK_DBG_SHIFT 1 54 55 #define RK3528_CLKSEL39(_aclk_m_core) \ 56 { \ 57 .reg = RK3528_CLKSEL_CON(39), \ 58 .val = HIWORD_UPDATE(_aclk_m_core, RK3528_DIV_ACLK_M_CORE_MASK, \ 59 RK3528_DIV_ACLK_M_CORE_SHIFT), \ 60 } 61 62 #define RK3528_CLKSEL40(_pclk_dbg) \ 63 { \ 64 .reg = RK3528_CLKSEL_CON(40), \ 65 .val = HIWORD_UPDATE(_pclk_dbg, RK3528_DIV_PCLK_DBG_MASK, \ 66 RK3528_DIV_PCLK_DBG_SHIFT), \ 67 } 68 69 #define RK3528_CPUCLK_RATE(_prate, _aclk_m_core, _pclk_dbg) \ 70 { \ 71 .prate = _prate, \ 72 .divs = { \ 73 RK3528_CLKSEL39(_aclk_m_core), \ 74 RK3528_CLKSEL40(_pclk_dbg), \ 75 }, \ 76 } 77 78 static struct rockchip_cpuclk_rate_table rk3528_cpuclk_rates[] __initdata = { 79 RK3528_CPUCLK_RATE(1896000000, 1, 13), 80 RK3528_CPUCLK_RATE(1800000000, 1, 12), 81 RK3528_CPUCLK_RATE(1704000000, 1, 11), 82 RK3528_CPUCLK_RATE(1608000000, 1, 11), 83 RK3528_CPUCLK_RATE(1512000000, 1, 11), 84 RK3528_CPUCLK_RATE(1416000000, 1, 9), 85 RK3528_CPUCLK_RATE(1296000000, 1, 8), 86 RK3528_CPUCLK_RATE(1200000000, 1, 8), 87 RK3528_CPUCLK_RATE(1188000000, 1, 8), 88 RK3528_CPUCLK_RATE(1092000000, 1, 7), 89 RK3528_CPUCLK_RATE(1008000000, 1, 6), 90 RK3528_CPUCLK_RATE(1000000000, 1, 6), 91 RK3528_CPUCLK_RATE(996000000, 1, 6), 92 RK3528_CPUCLK_RATE(960000000, 1, 6), 93 RK3528_CPUCLK_RATE(912000000, 1, 6), 94 RK3528_CPUCLK_RATE(816000000, 1, 5), 95 RK3528_CPUCLK_RATE(600000000, 1, 3), 96 RK3528_CPUCLK_RATE(594000000, 1, 3), 97 RK3528_CPUCLK_RATE(408000000, 1, 2), 98 RK3528_CPUCLK_RATE(312000000, 1, 2), 99 RK3528_CPUCLK_RATE(216000000, 1, 1), 100 RK3528_CPUCLK_RATE(96000000, 1, 0), 101 }; 102 103 static const struct rockchip_cpuclk_reg_data rk3528_cpuclk_data = { 104 .core_reg[0] = RK3528_CLKSEL_CON(39), 105 .div_core_shift[0] = 5, 106 .div_core_mask[0] = 0x1f, 107 .num_cores = 1, 108 .mux_core_alt = 1, 109 .mux_core_main = 0, 110 .mux_core_shift = 10, 111 .mux_core_mask = 0x1, 112 }; 113 114 PNAME(mux_pll_p) = { "xin24m" }; 115 PNAME(mux_armclk) = { "apll", "gpll" }; 116 PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" }; 117 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" }; 118 PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" }; 119 PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", 120 "xin24m" }; 121 PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", 122 "xin24m" }; 123 PNAME(mux_200m_100m_24m_p) = { "clk_200m_src", "clk_100m_src", 124 "xin24m" }; 125 PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", 126 "clk_50m_src", "xin24m" }; 127 PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", 128 "clk_100m_src", "xin24m" }; 129 PNAME(mux_339m_200m_100m_24m_p) = { "clk_339m_src", "clk_200m_src", 130 "clk_100m_src", "xin24m" }; 131 PNAME(mux_500m_200m_100m_24m_p) = { "clk_500m_src", "clk_200m_src", 132 "clk_100m_src", "xin24m" }; 133 PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", 134 "clk_100m_src", "xin24m" }; 135 PNAME(mux_600m_300m_200m_24m_p) = { "clk_600m_src", "clk_300m_src", 136 "clk_200m_src", "xin24m" }; 137 PNAME(aclk_gpu_p) = { "aclk_gpu_root", 138 "clk_gpu_pvtpll_src" }; 139 PNAME(aclk_rkvdec_pvtmux_root_p) = { "aclk_rkvdec_root", 140 "clk_rkvdec_pvtpll_src" }; 141 PNAME(clk_i2c2_p) = { "clk_200m_src", "clk_100m_src", 142 "xin24m", "clk_32k" }; 143 PNAME(clk_ref_pcie_inner_phy_p) = { "clk_ppll_100m_src", "xin24m" }; 144 PNAME(dclk_vop0_p) = { "dclk_vop_src0", 145 "clk_hdmiphy_pixel_io" }; 146 PNAME(mclk_i2s0_2ch_sai_src_p) = { "clk_i2s0_2ch_src", 147 "clk_i2s0_2ch_frac", "xin12m" }; 148 PNAME(mclk_i2s1_8ch_sai_src_p) = { "clk_i2s1_8ch_src", 149 "clk_i2s1_8ch_frac", "xin12m" }; 150 PNAME(mclk_i2s2_2ch_sai_src_p) = { "clk_i2s2_2ch_src", 151 "clk_i2s2_2ch_frac", "xin12m" }; 152 PNAME(mclk_i2s3_8ch_sai_src_p) = { "clk_i2s3_8ch_src", 153 "clk_i2s3_8ch_frac", "xin12m" }; 154 PNAME(mclk_sai_i2s0_p) = { "mclk_i2s0_2ch_sai_src", 155 "i2s0_mclkin" }; 156 PNAME(mclk_sai_i2s1_p) = { "mclk_i2s1_8ch_sai_src", 157 "i2s1_mclkin" }; 158 PNAME(mclk_spdif_src_p) = { "clk_spdif_src", "clk_spdif_frac", 159 "xin12m" }; 160 PNAME(sclk_uart0_src_p) = { "clk_uart0_src", "clk_uart0_frac", 161 "xin24m" }; 162 PNAME(sclk_uart1_src_p) = { "clk_uart1_src", "clk_uart1_frac", 163 "xin24m" }; 164 PNAME(sclk_uart2_src_p) = { "clk_uart2_src", "clk_uart2_frac", 165 "xin24m" }; 166 PNAME(sclk_uart3_src_p) = { "clk_uart3_src", "clk_uart3_frac", 167 "xin24m" }; 168 PNAME(sclk_uart4_src_p) = { "clk_uart4_src", "clk_uart4_frac", 169 "xin24m" }; 170 PNAME(sclk_uart5_src_p) = { "clk_uart5_src", "clk_uart5_frac", 171 "xin24m" }; 172 PNAME(sclk_uart6_src_p) = { "clk_uart6_src", "clk_uart6_frac", 173 "xin24m" }; 174 PNAME(sclk_uart7_src_p) = { "clk_uart7_src", "clk_uart7_frac", 175 "xin24m" }; 176 PNAME(clk_32k_p) = { "xin_osc0_div", "clk_pvtm_32k" }; 177 178 static struct rockchip_pll_clock rk3528_pll_clks[] __initdata = { 179 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 180 CLK_IS_CRITICAL, RK3528_PLL_CON(0), 181 RK3528_MODE_CON, 0, 0, 0, rk3528_pll_rates), 182 183 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 184 CLK_IS_CRITICAL, RK3528_PLL_CON(8), 185 RK3528_MODE_CON, 2, 0, 0, rk3528_pll_rates), 186 187 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 188 CLK_IS_CRITICAL, RK3528_PLL_CON(24), 189 RK3528_MODE_CON, 4, 0, 0, rk3528_pll_rates), 190 191 [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p, 192 CLK_IS_CRITICAL, RK3528_PCIE_PLL_CON(32), 193 RK3528_MODE_CON, 6, 0, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates), 194 195 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 196 CLK_IGNORE_UNUSED, RK3528_DDRPHY_PLL_CON(16), 197 RK3528_DDRPHY_MODE_CON, 0, 0, 0, rk3528_pll_rates), 198 }; 199 200 #define MFLAGS CLK_MUX_HIWORD_MASK 201 #define DFLAGS CLK_DIVIDER_HIWORD_MASK 202 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 203 204 static struct rockchip_clk_branch rk3528_uart0_fracmux __initdata = 205 MUX(CLK_UART0, "clk_uart0", sclk_uart0_src_p, CLK_SET_RATE_PARENT, 206 RK3528_CLKSEL_CON(6), 0, 2, MFLAGS); 207 208 static struct rockchip_clk_branch rk3528_uart1_fracmux __initdata = 209 MUX(CLK_UART1, "clk_uart1", sclk_uart1_src_p, CLK_SET_RATE_PARENT, 210 RK3528_CLKSEL_CON(8), 0, 2, MFLAGS); 211 212 static struct rockchip_clk_branch rk3528_uart2_fracmux __initdata = 213 MUX(CLK_UART2, "clk_uart2", sclk_uart2_src_p, CLK_SET_RATE_PARENT, 214 RK3528_CLKSEL_CON(10), 0, 2, MFLAGS); 215 216 static struct rockchip_clk_branch rk3528_uart3_fracmux __initdata = 217 MUX(CLK_UART3, "clk_uart3", sclk_uart3_src_p, CLK_SET_RATE_PARENT, 218 RK3528_CLKSEL_CON(12), 0, 2, MFLAGS); 219 220 static struct rockchip_clk_branch rk3528_uart4_fracmux __initdata = 221 MUX(CLK_UART4, "clk_uart4", sclk_uart4_src_p, CLK_SET_RATE_PARENT, 222 RK3528_CLKSEL_CON(14), 0, 2, MFLAGS); 223 224 static struct rockchip_clk_branch rk3528_uart5_fracmux __initdata = 225 MUX(CLK_UART5, "clk_uart5", sclk_uart5_src_p, CLK_SET_RATE_PARENT, 226 RK3528_CLKSEL_CON(16), 0, 2, MFLAGS); 227 228 static struct rockchip_clk_branch rk3528_uart6_fracmux __initdata = 229 MUX(CLK_UART6, "clk_uart6", sclk_uart6_src_p, CLK_SET_RATE_PARENT, 230 RK3528_CLKSEL_CON(18), 0, 2, MFLAGS); 231 232 static struct rockchip_clk_branch rk3528_uart7_fracmux __initdata = 233 MUX(CLK_UART7, "clk_uart7", sclk_uart7_src_p, CLK_SET_RATE_PARENT, 234 RK3528_CLKSEL_CON(20), 0, 2, MFLAGS); 235 236 static struct rockchip_clk_branch mclk_i2s0_2ch_sai_src_fracmux __initdata = 237 MUX(MCLK_I2S0_2CH_SAI_SRC_PRE, "mclk_i2s0_2ch_sai_src_pre", mclk_i2s0_2ch_sai_src_p, CLK_SET_RATE_PARENT, 238 RK3528_CLKSEL_CON(22), 0, 2, MFLAGS); 239 240 static struct rockchip_clk_branch mclk_i2s1_8ch_sai_src_fracmux __initdata = 241 MUX(MCLK_I2S1_8CH_SAI_SRC_PRE, "mclk_i2s1_8ch_sai_src_pre", mclk_i2s1_8ch_sai_src_p, CLK_SET_RATE_PARENT, 242 RK3528_CLKSEL_CON(26), 0, 2, MFLAGS); 243 244 static struct rockchip_clk_branch mclk_i2s2_2ch_sai_src_fracmux __initdata = 245 MUX(MCLK_I2S2_2CH_SAI_SRC_PRE, "mclk_i2s2_2ch_sai_src_pre", mclk_i2s2_2ch_sai_src_p, CLK_SET_RATE_PARENT, 246 RK3528_CLKSEL_CON(28), 0, 2, MFLAGS); 247 248 static struct rockchip_clk_branch mclk_i2s3_8ch_sai_src_fracmux __initdata = 249 MUX(MCLK_I2S3_8CH_SAI_SRC_PRE, "mclk_i2s3_8ch_sai_src_pre", mclk_i2s3_8ch_sai_src_p, CLK_SET_RATE_PARENT, 250 RK3528_CLKSEL_CON(24), 0, 2, MFLAGS); 251 252 static struct rockchip_clk_branch mclk_spdif_src_fracmux __initdata = 253 MUX(MCLK_SDPDIF_SRC_PRE, "mclk_spdif_src_pre", mclk_spdif_src_p, CLK_SET_RATE_PARENT, 254 RK3528_CLKSEL_CON(32), 0, 2, MFLAGS); 255 256 static struct rockchip_clk_branch rk3528_clk_branches[] __initdata = { 257 /* top */ 258 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 259 260 COMPOSITE(CLK_MATRIX_250M_SRC, "clk_250m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL, 261 RK3528_CLKSEL_CON(1), 15, 1, MFLAGS, 10, 5, DFLAGS, 262 RK3528_CLKGATE_CON(0), 5, GFLAGS), 263 COMPOSITE(CLK_MATRIX_500M_SRC, "clk_500m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL, 264 RK3528_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS, 265 RK3528_CLKGATE_CON(0), 10, GFLAGS), 266 COMPOSITE_NOMUX(CLK_MATRIX_50M_SRC, "clk_50m_src", "cpll", CLK_IS_CRITICAL, 267 RK3528_CLKSEL_CON(0), 2, 5, DFLAGS, 268 RK3528_CLKGATE_CON(0), 1, GFLAGS), 269 COMPOSITE_NOMUX(CLK_MATRIX_100M_SRC, "clk_100m_src", "cpll", CLK_IS_CRITICAL, 270 RK3528_CLKSEL_CON(0), 7, 5, DFLAGS, 271 RK3528_CLKGATE_CON(0), 2, GFLAGS), 272 COMPOSITE_NOMUX(CLK_MATRIX_150M_SRC, "clk_150m_src", "gpll", CLK_IS_CRITICAL, 273 RK3528_CLKSEL_CON(1), 0, 5, DFLAGS, 274 RK3528_CLKGATE_CON(0), 3, GFLAGS), 275 COMPOSITE_NOMUX(CLK_MATRIX_200M_SRC, "clk_200m_src", "gpll", CLK_IS_CRITICAL, 276 RK3528_CLKSEL_CON(1), 5, 5, DFLAGS, 277 RK3528_CLKGATE_CON(0), 4, GFLAGS), 278 COMPOSITE_NOMUX(CLK_MATRIX_300M_SRC, "clk_300m_src", "gpll", CLK_IS_CRITICAL, 279 RK3528_CLKSEL_CON(2), 0, 5, DFLAGS, 280 RK3528_CLKGATE_CON(0), 6, GFLAGS), 281 COMPOSITE_NOMUX_HALFDIV(CLK_MATRIX_339M_SRC, "clk_339m_src", "gpll", CLK_IS_CRITICAL, 282 RK3528_CLKSEL_CON(2), 5, 5, DFLAGS, 283 RK3528_CLKGATE_CON(0), 7, GFLAGS), 284 COMPOSITE_NOMUX(CLK_MATRIX_400M_SRC, "clk_400m_src", "gpll", CLK_IS_CRITICAL, 285 RK3528_CLKSEL_CON(2), 10, 5, DFLAGS, 286 RK3528_CLKGATE_CON(0), 8, GFLAGS), 287 COMPOSITE_NOMUX(CLK_MATRIX_600M_SRC, "clk_600m_src", "gpll", CLK_IS_CRITICAL, 288 RK3528_CLKSEL_CON(4), 0, 5, DFLAGS, 289 RK3528_CLKGATE_CON(0), 11, GFLAGS), 290 COMPOSITE(DCLK_VOP_SRC0, "dclk_vop_src0", mux_gpll_cpll_p, 0, 291 RK3528_CLKSEL_CON(32), 10, 1, MFLAGS, 2, 8, DFLAGS, 292 RK3528_CLKGATE_CON(3), 7, GFLAGS), 293 COMPOSITE(DCLK_VOP_SRC1, "dclk_vop_src1", mux_gpll_cpll_p, 0, 294 RK3528_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 8, DFLAGS, 295 RK3528_CLKGATE_CON(3), 8, GFLAGS), 296 COMPOSITE_NOMUX(CLK_HSM, "clk_hsm", "xin24m", 0, 297 RK3528_CLKSEL_CON(36), 5, 5, DFLAGS, 298 RK3528_CLKGATE_CON(3), 13, GFLAGS), 299 300 COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "gpll", 0, 301 RK3528_CLKSEL_CON(4), 5, 5, DFLAGS, 302 RK3528_CLKGATE_CON(0), 12, GFLAGS), 303 COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT, 304 RK3528_CLKSEL_CON(5), 0, 305 RK3528_CLKGATE_CON(0), 13, GFLAGS, 306 &rk3528_uart0_fracmux), 307 GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0, 308 RK3528_CLKGATE_CON(0), 14, GFLAGS), 309 310 COMPOSITE_NOMUX(CLK_UART1_SRC, "clk_uart1_src", "gpll", 0, 311 RK3528_CLKSEL_CON(6), 2, 5, DFLAGS, 312 RK3528_CLKGATE_CON(0), 15, GFLAGS), 313 COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, 314 RK3528_CLKSEL_CON(7), 0, 315 RK3528_CLKGATE_CON(1), 0, GFLAGS, 316 &rk3528_uart1_fracmux), 317 GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, 318 RK3528_CLKGATE_CON(1), 1, GFLAGS), 319 320 COMPOSITE_NOMUX(CLK_UART2_SRC, "clk_uart2_src", "gpll", 0, 321 RK3528_CLKSEL_CON(8), 2, 5, DFLAGS, 322 RK3528_CLKGATE_CON(1), 2, GFLAGS), 323 COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, 324 RK3528_CLKSEL_CON(9), 0, 325 RK3528_CLKGATE_CON(1), 3, GFLAGS, 326 &rk3528_uart2_fracmux), 327 GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, 328 RK3528_CLKGATE_CON(1), 4, GFLAGS), 329 330 COMPOSITE_NOMUX(CLK_UART3_SRC, "clk_uart3_src", "gpll", 0, 331 RK3528_CLKSEL_CON(10), 2, 5, DFLAGS, 332 RK3528_CLKGATE_CON(1), 5, GFLAGS), 333 COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, 334 RK3528_CLKSEL_CON(11), 0, 335 RK3528_CLKGATE_CON(1), 6, GFLAGS, 336 &rk3528_uart3_fracmux), 337 GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, 338 RK3528_CLKGATE_CON(1), 7, GFLAGS), 339 340 COMPOSITE_NOMUX(CLK_UART4_SRC, "clk_uart4_src", "gpll", 0, 341 RK3528_CLKSEL_CON(12), 2, 5, DFLAGS, 342 RK3528_CLKGATE_CON(1), 8, GFLAGS), 343 COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, 344 RK3528_CLKSEL_CON(13), 0, 345 RK3528_CLKGATE_CON(1), 9, GFLAGS, 346 &rk3528_uart4_fracmux), 347 GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, 348 RK3528_CLKGATE_CON(1), 10, GFLAGS), 349 350 COMPOSITE_NOMUX(CLK_UART5_SRC, "clk_uart5_src", "gpll", 0, 351 RK3528_CLKSEL_CON(14), 2, 5, DFLAGS, 352 RK3528_CLKGATE_CON(1), 11, GFLAGS), 353 COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, 354 RK3528_CLKSEL_CON(15), 0, 355 RK3528_CLKGATE_CON(1), 12, GFLAGS, 356 &rk3528_uart5_fracmux), 357 GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, 358 RK3528_CLKGATE_CON(1), 13, GFLAGS), 359 360 COMPOSITE_NOMUX(CLK_UART6_SRC, "clk_uart6_src", "gpll", 0, 361 RK3528_CLKSEL_CON(16), 2, 5, DFLAGS, 362 RK3528_CLKGATE_CON(1), 14, GFLAGS), 363 COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, 364 RK3528_CLKSEL_CON(17), 0, 365 RK3528_CLKGATE_CON(1), 15, GFLAGS, 366 &rk3528_uart6_fracmux), 367 GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, 368 RK3528_CLKGATE_CON(2), 0, GFLAGS), 369 370 COMPOSITE_NOMUX(CLK_UART7_SRC, "clk_uart7_src", "gpll", 0, 371 RK3528_CLKSEL_CON(18), 2, 5, DFLAGS, 372 RK3528_CLKGATE_CON(2), 1, GFLAGS), 373 COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, 374 RK3528_CLKSEL_CON(19), 0, 375 RK3528_CLKGATE_CON(2), 2, GFLAGS, 376 &rk3528_uart7_fracmux), 377 GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, 378 RK3528_CLKGATE_CON(2), 3, GFLAGS), 379 380 COMPOSITE_NOMUX(CLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", "gpll", 0, 381 RK3528_CLKSEL_CON(20), 8, 5, DFLAGS, 382 RK3528_CLKGATE_CON(2), 5, GFLAGS), 383 COMPOSITE_FRACMUX(CLK_I2S0_2CH_FRAC, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT, 384 RK3528_CLKSEL_CON(21), 0, 385 RK3528_CLKGATE_CON(2), 6, GFLAGS, 386 &mclk_i2s0_2ch_sai_src_fracmux), 387 GATE(MCLK_I2S0_2CH_SAI_SRC, "mclk_i2s0_2ch_sai_src", "mclk_i2s0_2ch_sai_src_pre", 0, 388 RK3528_CLKGATE_CON(2), 7, GFLAGS), 389 390 COMPOSITE_NOMUX(CLK_I2S1_8CH_SRC, "clk_i2s1_8ch_src", "gpll", 0, 391 RK3528_CLKSEL_CON(24), 3, 5, DFLAGS, 392 RK3528_CLKGATE_CON(2), 11, GFLAGS), 393 COMPOSITE_FRACMUX(CLK_I2S1_8CH_FRAC, "clk_i2s1_8ch_frac", "clk_i2s1_8ch_src", CLK_SET_RATE_PARENT, 394 RK3528_CLKSEL_CON(25), 0, 395 RK3528_CLKGATE_CON(2), 12, GFLAGS, 396 &mclk_i2s1_8ch_sai_src_fracmux), 397 GATE(MCLK_I2S1_8CH_SAI_SRC, "mclk_i2s1_8ch_sai_src", "mclk_i2s1_8ch_sai_src_pre", 0, 398 RK3528_CLKGATE_CON(2), 13, GFLAGS), 399 400 COMPOSITE_NOMUX(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", "gpll", 0, 401 RK3528_CLKSEL_CON(26), 3, 5, DFLAGS, 402 RK3528_CLKGATE_CON(2), 14, GFLAGS), 403 COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT, 404 RK3528_CLKSEL_CON(27), 0, 405 RK3528_CLKGATE_CON(2), 15, GFLAGS, 406 &mclk_i2s2_2ch_sai_src_fracmux), 407 GATE(MCLK_I2S2_2CH_SAI_SRC, "mclk_i2s2_2ch_sai_src", "mclk_i2s2_2ch_sai_src_pre", 0, 408 RK3528_CLKGATE_CON(3), 0, GFLAGS), 409 410 COMPOSITE_NOMUX(CLK_I2S3_8CH_SRC, "clk_i2s3_8ch_src", "gpll", 0, 411 RK3528_CLKSEL_CON(22), 3, 5, DFLAGS, 412 RK3528_CLKGATE_CON(2), 8, GFLAGS), 413 COMPOSITE_FRACMUX(CLK_I2S3_8CH_FRAC, "clk_i2s3_8ch_frac", "clk_i2s3_8ch_src", CLK_SET_RATE_PARENT, 414 RK3528_CLKSEL_CON(23), 0, 415 RK3528_CLKGATE_CON(2), 9, GFLAGS, 416 &mclk_i2s3_8ch_sai_src_fracmux), 417 GATE(MCLK_I2S3_8CH_SAI_SRC, "mclk_i2s3_8ch_sai_src", "mclk_i2s3_8ch_sai_src_pre", 0, 418 RK3528_CLKGATE_CON(2), 10, GFLAGS), 419 420 COMPOSITE_NOMUX(CLK_SPDIF_SRC, "clk_spdif_src", "gpll", 0, 421 RK3528_CLKSEL_CON(30), 2, 5, DFLAGS, 422 RK3528_CLKGATE_CON(3), 4, GFLAGS), 423 COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", CLK_SET_RATE_PARENT, 424 RK3528_CLKSEL_CON(31), 0, 425 RK3528_CLKGATE_CON(3), 5, GFLAGS, 426 &mclk_spdif_src_fracmux), 427 GATE(MCLK_SPDIF_SRC, "mclk_spdif_src", "mclk_spdif_src_pre", 0, 428 RK3528_CLKGATE_CON(3), 6, GFLAGS), 429 430 /* bus */ 431 COMPOSITE_NODIV(ACLK_BUS_M_ROOT, "aclk_bus_m_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, 432 RK3528_CLKSEL_CON(43), 12, 2, MFLAGS, 433 RK3528_CLKGATE_CON(8), 7, GFLAGS), 434 GATE(ACLK_GIC, "aclk_gic", "aclk_bus_m_root", CLK_IS_CRITICAL, 435 RK3528_CLKGATE_CON(9), 1, GFLAGS), 436 437 COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL, 438 RK3528_CLKSEL_CON(43), 6, 2, MFLAGS, 439 RK3528_CLKGATE_CON(8), 4, GFLAGS), 440 GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0, 441 RK3528_CLKGATE_CON(9), 2, GFLAGS), 442 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0, 443 RK3528_CLKGATE_CON(9), 4, GFLAGS), 444 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_root", 0, 445 RK3528_CLKGATE_CON(11), 11, GFLAGS), 446 COMPOSITE(ACLK_BUS_VOPGL_ROOT, "aclk_bus_vopgl_root", mux_gpll_cpll_p, CLK_IS_CRITICAL, 447 RK3528_CLKSEL_CON(43), 3, 1, MFLAGS, 0, 3, DFLAGS, 448 RK3528_CLKGATE_CON(8), 0, GFLAGS), 449 COMPOSITE_NODIV(ACLK_BUS_H_ROOT, "aclk_bus_h_root", mux_500m_200m_100m_24m_p, CLK_IS_CRITICAL, 450 RK3528_CLKSEL_CON(43), 4, 2, MFLAGS, 451 RK3528_CLKGATE_CON(8), 2, GFLAGS), 452 GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_bus_h_root", 0, 453 RK3528_CLKGATE_CON(10), 14, GFLAGS), 454 455 COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, 456 RK3528_CLKSEL_CON(43), 8, 2, MFLAGS, 457 RK3528_CLKGATE_CON(8), 5, GFLAGS), 458 459 COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, 460 RK3528_CLKSEL_CON(43), 10, 2, MFLAGS, 461 RK3528_CLKGATE_CON(8), 6, GFLAGS), 462 GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus_root", 0, 463 RK3528_CLKGATE_CON(8), 13, GFLAGS), 464 GATE(PCLK_BUS_GRF, "pclk_bus_grf", "pclk_bus_root", CLK_IS_CRITICAL, 465 RK3528_CLKGATE_CON(8), 15, GFLAGS), 466 GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0, 467 RK3528_CLKGATE_CON(9), 5, GFLAGS), 468 GATE(PCLK_JDBCK_DAP, "pclk_jdbck_dap", "pclk_bus_root", 0, 469 RK3528_CLKGATE_CON(9), 12, GFLAGS), 470 GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_root", 0, 471 RK3528_CLKGATE_CON(9), 15, GFLAGS), 472 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0, 473 RK3528_CLKGATE_CON(10), 7, GFLAGS), 474 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0, 475 RK3528_CLKGATE_CON(11), 4, GFLAGS), 476 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0, 477 RK3528_CLKGATE_CON(11), 7, GFLAGS), 478 GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_bus_root", 0, 479 RK3528_CLKGATE_CON(10), 13, GFLAGS), 480 GATE(PCLK_SCR, "pclk_scr", "pclk_bus_root", 0, 481 RK3528_CLKGATE_CON(11), 10, GFLAGS), 482 GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus_root", CLK_IGNORE_UNUSED, 483 RK3528_CLKGATE_CON(11), 12, GFLAGS), 484 485 COMPOSITE_NODIV(CLK_PWM0, "clk_pwm0", mux_100m_50m_24m_p, 0, 486 RK3528_CLKSEL_CON(44), 6, 2, MFLAGS, 487 RK3528_CLKGATE_CON(11), 5, GFLAGS), 488 COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, 489 RK3528_CLKSEL_CON(44), 8, 2, MFLAGS, 490 RK3528_CLKGATE_CON(11), 8, GFLAGS), 491 492 GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0, 493 RK3528_CLKGATE_CON(11), 9, GFLAGS), 494 GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0, 495 RK3528_CLKGATE_CON(11), 6, GFLAGS), 496 GATE(CLK_JDBCK_DAP, "clk_jdbck_dap", "xin24m", 0, 497 RK3528_CLKGATE_CON(9), 13, GFLAGS), 498 GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0, 499 RK3528_CLKGATE_CON(10), 0, GFLAGS), 500 501 GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0, 502 RK3528_CLKGATE_CON(8), 9, GFLAGS), 503 GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0, 504 RK3528_CLKGATE_CON(9), 6, GFLAGS), 505 GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0, 506 RK3528_CLKGATE_CON(9), 7, GFLAGS), 507 GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0, 508 RK3528_CLKGATE_CON(9), 8, GFLAGS), 509 GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0, 510 RK3528_CLKGATE_CON(9), 9, GFLAGS), 511 GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0, 512 RK3528_CLKGATE_CON(9), 10, GFLAGS), 513 GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0, 514 RK3528_CLKGATE_CON(9), 11, GFLAGS), 515 516 /* pmu */ 517 GATE(HCLK_PMU_ROOT, "hclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED, 518 RK3528_PMU_CLKGATE_CON(0), 1, GFLAGS), 519 GATE(PCLK_PMU_ROOT, "pclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED, 520 RK3528_PMU_CLKGATE_CON(0), 0, GFLAGS), 521 522 GATE(FCLK_MCU, "fclk_mcu", "hclk_pmu_root", 0, 523 RK3528_PMU_CLKGATE_CON(0), 7, GFLAGS), 524 GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", CLK_IS_CRITICAL, 525 RK3528_PMU_CLKGATE_CON(5), 4, GFLAGS), 526 527 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pmu_root", 0, 528 RK3528_PMU_CLKGATE_CON(0), 2, GFLAGS), 529 GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "pclk_pmu_root", 0, 530 RK3528_PMU_CLKGATE_CON(1), 2, GFLAGS), 531 GATE(PCLK_PMU_IOC, "pclk_pmu_ioc", "pclk_pmu_root", CLK_IS_CRITICAL, 532 RK3528_PMU_CLKGATE_CON(1), 5, GFLAGS), 533 GATE(PCLK_PMU_CRU, "pclk_pmu_cru", "pclk_pmu_root", CLK_IS_CRITICAL, 534 RK3528_PMU_CLKGATE_CON(1), 6, GFLAGS), 535 GATE(PCLK_PMU_GRF, "pclk_pmu_grf", "pclk_pmu_root", CLK_IS_CRITICAL, 536 RK3528_PMU_CLKGATE_CON(1), 7, GFLAGS), 537 GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0, 538 RK3528_PMU_CLKGATE_CON(1), 10, GFLAGS), 539 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IS_CRITICAL, 540 RK3528_PMU_CLKGATE_CON(0), 13, GFLAGS), 541 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0, 542 RK3528_PMU_CLKGATE_CON(0), 14, GFLAGS), 543 GATE(PCLK_OSCCHK, "pclk_oscchk", "pclk_pmu_root", 0, 544 RK3528_PMU_CLKGATE_CON(0), 9, GFLAGS), 545 GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0, 546 RK3528_PMU_CLKGATE_CON(1), 12, GFLAGS), 547 GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pmu_root", 0, 548 RK3528_PMU_CLKGATE_CON(1), 15, GFLAGS), 549 GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0, 550 RK3528_PMU_CLKGATE_CON(5), 1, GFLAGS), 551 552 COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", clk_i2c2_p, 0, 553 RK3528_PMU_CLKSEL_CON(0), 0, 2, MFLAGS, 554 RK3528_PMU_CLKGATE_CON(0), 3, GFLAGS), 555 556 GATE(CLK_REFOUT, "clk_refout", "xin24m", 0, 557 RK3528_PMU_CLKGATE_CON(2), 4, GFLAGS), 558 COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, 559 RK3528_PMU_CLKSEL_CON(5), 0, 5, DFLAGS, 560 RK3528_PMU_CLKGATE_CON(5), 0, GFLAGS), 561 562 COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", 0, 563 RK3528_PMU_CLKSEL_CON(1), 0, 564 RK3528_PMU_CLKGATE_CON(1), 0, GFLAGS), 565 /* clk_32k: internal! No path from external osc 32k */ 566 MUX(CLK_DEEPSLOW, "clk_32k", clk_32k_p, CLK_IS_CRITICAL, 567 RK3528_PMU_CLKSEL_CON(2), 0, 1, MFLAGS), 568 GATE(RTC_CLK_MCU, "rtc_clk_mcu", "clk_32k", 0, 569 RK3528_PMU_CLKGATE_CON(0), 8, GFLAGS), 570 GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED, 571 RK3528_PMU_CLKGATE_CON(1), 1, GFLAGS), 572 573 COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, 574 RK3528_PMU_CLKSEL_CON(0), 2, 1, MFLAGS, 575 RK3528_PMU_CLKGATE_CON(0), 15, GFLAGS), 576 COMPOSITE_NODIV(TCLK_PMU_WDT, "tclk_pmu_wdt", mux_24m_32k_p, 0, 577 RK3528_PMU_CLKSEL_CON(2), 1, 1, MFLAGS, 578 RK3528_PMU_CLKGATE_CON(1), 11, GFLAGS), 579 580 /* core */ 581 COMPOSITE_NOMUX(ACLK_M_CORE_BIU, "aclk_m_core", "armclk", CLK_IS_CRITICAL, 582 RK3528_CLKSEL_CON(39), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 583 RK3528_CLKGATE_CON(5), 12, GFLAGS), 584 COMPOSITE_NOMUX(PCLK_DBG, "pclk_dbg", "armclk", CLK_IS_CRITICAL, 585 RK3528_CLKSEL_CON(40), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, 586 RK3528_CLKGATE_CON(5), 13, GFLAGS), 587 GATE(PCLK_CPU_ROOT, "pclk_cpu_root", "pclk_dbg", CLK_IS_CRITICAL, 588 RK3528_CLKGATE_CON(6), 1, GFLAGS), 589 GATE(PCLK_CORE_GRF, "pclk_core_grf", "pclk_cpu_root", CLK_IS_CRITICAL, 590 RK3528_CLKGATE_CON(6), 2, GFLAGS), 591 592 /* ddr */ 593 GATE(CLK_DDRC_SRC, "clk_ddrc_src", "dpll", CLK_IS_CRITICAL, 594 RK3528_DDRPHY_CLKGATE_CON(0), 0, GFLAGS), 595 GATE(CLK_DDR_PHY, "clk_ddr_phy", "dpll", CLK_IS_CRITICAL, 596 RK3528_DDRPHY_CLKGATE_CON(0), 1, GFLAGS), 597 598 COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, 599 RK3528_CLKSEL_CON(90), 0, 2, MFLAGS, 600 RK3528_CLKGATE_CON(45), 0, GFLAGS), 601 GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", CLK_IGNORE_UNUSED, 602 RK3528_CLKGATE_CON(45), 3, GFLAGS), 603 GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED, 604 RK3528_CLKGATE_CON(45), 8, GFLAGS), 605 GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", CLK_IGNORE_UNUSED, 606 RK3528_CLKGATE_CON(45), 4, GFLAGS), 607 608 GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IS_CRITICAL, 609 RK3528_CLKGATE_CON(45), 2, GFLAGS), 610 GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr_root", CLK_IS_CRITICAL, 611 RK3528_CLKGATE_CON(45), 6, GFLAGS), 612 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IS_CRITICAL, 613 RK3528_CLKGATE_CON(45), 9, GFLAGS), 614 615 GATE(ACLK_DDR_UPCTL, "aclk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL, 616 RK3528_CLKGATE_CON(45), 11, GFLAGS), 617 GATE(CLK_DDR_UPCTL, "clk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL, 618 RK3528_CLKGATE_CON(45), 12, GFLAGS), 619 GATE(CLK_DDRMON, "clk_ddrmon", "clk_ddrc_src", CLK_IS_CRITICAL, 620 RK3528_CLKGATE_CON(45), 13, GFLAGS), 621 GATE(ACLK_DDR_SCRAMBLE, "aclk_ddr_scramble", "clk_ddrc_src", CLK_IS_CRITICAL, 622 RK3528_CLKGATE_CON(45), 14, GFLAGS), 623 GATE(ACLK_SPLIT, "aclk_split", "clk_ddrc_src", CLK_IS_CRITICAL, 624 RK3528_CLKGATE_CON(45), 15, GFLAGS), 625 626 /* gpu */ 627 COMPOSITE_NODIV(ACLK_GPU_ROOT, "aclk_gpu_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL, 628 RK3528_CLKSEL_CON(76), 0, 2, MFLAGS, 629 RK3528_CLKGATE_CON(34), 0, GFLAGS), 630 COMPOSITE_NODIV(ACLK_GPU, "aclk_gpu", aclk_gpu_p, CLK_SET_RATE_PARENT, 631 RK3528_CLKSEL_CON(76), 6, 1, MFLAGS, 632 RK3528_CLKGATE_CON(34), 7, GFLAGS), 633 GATE(ACLK_GPU_MALI, "aclk_gpu_mali", "aclk_gpu", 0, 634 RK3528_CLKGATE_CON(34), 8, GFLAGS), 635 COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, 636 RK3528_CLKSEL_CON(76), 4, 2, MFLAGS, 637 RK3528_CLKGATE_CON(34), 2, GFLAGS), 638 639 /* rkvdec */ 640 COMPOSITE_NODIV(ACLK_RKVDEC_ROOT_NDFT, "aclk_rkvdec_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL, 641 RK3528_CLKSEL_CON(88), 6, 2, MFLAGS, 642 RK3528_CLKGATE_CON(44), 3, GFLAGS), 643 COMPOSITE_NODIV(HCLK_RKVDEC_ROOT, "hclk_rkvdec_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, 644 RK3528_CLKSEL_CON(88), 4, 2, MFLAGS, 645 RK3528_CLKGATE_CON(44), 2, GFLAGS), 646 GATE(PCLK_DDRPHY_CRU, "pclk_ddrphy_cru", "hclk_rkvdec_root", CLK_IS_CRITICAL, 647 RK3528_CLKGATE_CON(44), 4, GFLAGS), 648 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0, 649 RK3528_CLKGATE_CON(44), 9, GFLAGS), 650 COMPOSITE_NODIV(CLK_HEVC_CA_RKVDEC, "clk_hevc_ca_rkvdec", mux_600m_300m_200m_24m_p, 0, 651 RK3528_CLKSEL_CON(88), 11, 2, MFLAGS, 652 RK3528_CLKGATE_CON(44), 11, GFLAGS), 653 MUX(ACLK_RKVDEC_PVTMUX_ROOT, "aclk_rkvdec_pvtmux_root", aclk_rkvdec_pvtmux_root_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 654 RK3528_CLKSEL_CON(88), 13, 1, MFLAGS), 655 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pvtmux_root", 0, 656 RK3528_CLKGATE_CON(44), 8, GFLAGS), 657 658 /* rkvenc */ 659 COMPOSITE_NODIV(ACLK_RKVENC_ROOT, "aclk_rkvenc_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, 660 RK3528_CLKSEL_CON(79), 2, 2, MFLAGS, 661 RK3528_CLKGATE_CON(36), 1, GFLAGS), 662 GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_root", 0, 663 RK3528_CLKGATE_CON(36), 7, GFLAGS), 664 665 COMPOSITE_NODIV(PCLK_RKVENC_ROOT, "pclk_rkvenc_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, 666 RK3528_CLKSEL_CON(79), 4, 2, MFLAGS, 667 RK3528_CLKGATE_CON(36), 2, GFLAGS), 668 GATE(PCLK_RKVENC_IOC, "pclk_rkvenc_ioc", "pclk_rkvenc_root", CLK_IS_CRITICAL, 669 RK3528_CLKGATE_CON(37), 10, GFLAGS), 670 GATE(PCLK_RKVENC_GRF, "pclk_rkvenc_grf", "pclk_rkvenc_root", CLK_IS_CRITICAL, 671 RK3528_CLKGATE_CON(38), 6, GFLAGS), 672 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_rkvenc_root", 0, 673 RK3528_CLKGATE_CON(36), 11, GFLAGS), 674 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_rkvenc_root", 0, 675 RK3528_CLKGATE_CON(36), 13, GFLAGS), 676 GATE(PCLK_SPI0, "pclk_spi0", "pclk_rkvenc_root", 0, 677 RK3528_CLKGATE_CON(37), 2, GFLAGS), 678 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_rkvenc_root", 0, 679 RK3528_CLKGATE_CON(37), 8, GFLAGS), 680 GATE(PCLK_UART1, "pclk_uart1", "pclk_rkvenc_root", 0, 681 RK3528_CLKGATE_CON(38), 2, GFLAGS), 682 GATE(PCLK_UART3, "pclk_uart3", "pclk_rkvenc_root", 0, 683 RK3528_CLKGATE_CON(38), 4, GFLAGS), 684 GATE(PCLK_CAN0, "pclk_can0", "pclk_rkvenc_root", 0, 685 RK3528_CLKGATE_CON(38), 7, GFLAGS), 686 GATE(PCLK_CAN1, "pclk_can1", "pclk_rkvenc_root", 0, 687 RK3528_CLKGATE_CON(38), 9, GFLAGS), 688 689 COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mux_150m_100m_24m_p, 0, 690 RK3528_CLKSEL_CON(80), 12, 2, MFLAGS, 691 RK3528_CLKGATE_CON(38), 1, GFLAGS), 692 COMPOSITE(CLK_CAN0, "clk_can0", mux_gpll_cpll_p, 0, 693 RK3528_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS, 694 RK3528_CLKGATE_CON(38), 8, GFLAGS), 695 COMPOSITE(CLK_CAN1, "clk_can1", mux_gpll_cpll_p, 0, 696 RK3528_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS, 697 RK3528_CLKGATE_CON(38), 10, GFLAGS), 698 699 COMPOSITE_NODIV(HCLK_RKVENC_ROOT, "hclk_rkvenc_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, 700 RK3528_CLKSEL_CON(79), 0, 2, MFLAGS, 701 RK3528_CLKGATE_CON(36), 0, GFLAGS), 702 GATE(HCLK_SAI_I2S1, "hclk_sai_i2s1", "hclk_rkvenc_root", 0, 703 RK3528_CLKGATE_CON(36), 9, GFLAGS), 704 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_rkvenc_root", 0, 705 RK3528_CLKGATE_CON(37), 14, GFLAGS), 706 GATE(HCLK_PDM, "hclk_pdm", "hclk_rkvenc_root", 0, 707 RK3528_CLKGATE_CON(38), 0, GFLAGS), 708 GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_root", 0, 709 RK3528_CLKGATE_CON(36), 6, GFLAGS), 710 711 COMPOSITE_NODIV(CLK_CORE_RKVENC, "clk_core_rkvenc", mux_300m_200m_100m_24m_p, 0, 712 RK3528_CLKSEL_CON(79), 6, 2, MFLAGS, 713 RK3528_CLKGATE_CON(36), 8, GFLAGS), 714 COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0, 715 RK3528_CLKSEL_CON(79), 11, 2, MFLAGS, 716 RK3528_CLKGATE_CON(36), 14, GFLAGS), 717 COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0, 718 RK3528_CLKSEL_CON(79), 9, 2, MFLAGS, 719 RK3528_CLKGATE_CON(36), 12, GFLAGS), 720 721 COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0, 722 RK3528_CLKSEL_CON(79), 13, 2, MFLAGS, 723 RK3528_CLKGATE_CON(37), 3, GFLAGS), 724 COMPOSITE_NODIV(MCLK_SAI_I2S1, "mclk_sai_i2s1", mclk_sai_i2s1_p, CLK_SET_RATE_PARENT, 725 RK3528_CLKSEL_CON(79), 8, 1, MFLAGS, 726 RK3528_CLKGATE_CON(36), 10, GFLAGS), 727 GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0, 728 RK3528_CLKGATE_CON(37), 9, GFLAGS), 729 730 /* vo */ 731 COMPOSITE_NODIV(HCLK_VO_ROOT, "hclk_vo_root", mux_150m_100m_24m_p, CLK_IS_CRITICAL, 732 RK3528_CLKSEL_CON(83), 2, 2, MFLAGS, 733 RK3528_CLKGATE_CON(39), 1, GFLAGS), 734 GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0, 735 RK3528_CLKGATE_CON(40), 2, GFLAGS), 736 GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_vo_root", 0, 737 RK3528_CLKGATE_CON(43), 3, GFLAGS), 738 GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vo_root", 0, 739 RK3528_CLKGATE_CON(41), 7, GFLAGS), 740 GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vo_root", 0, 741 RK3528_CLKGATE_CON(39), 10, GFLAGS), 742 GATE(HCLK_CVBS, "hclk_cvbs", "hclk_vo_root", 0, 743 RK3528_CLKGATE_CON(41), 3, GFLAGS), 744 GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_vo_root", 0, 745 RK3528_CLKGATE_CON(43), 4, GFLAGS), 746 GATE(HCLK_SAI_I2S3, "hclk_sai_i2s3", "hclk_vo_root", 0, 747 RK3528_CLKGATE_CON(42), 1, GFLAGS), 748 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo_root", 0, 749 RK3528_CLKGATE_CON(41), 1, GFLAGS), 750 GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0, 751 RK3528_CLKGATE_CON(39), 7, GFLAGS), 752 GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_vo_root", 0, 753 RK3528_CLKGATE_CON(42), 9, GFLAGS), 754 GATE(HCLK_HDCP_KEY, "hclk_hdcp_key", "hclk_vo_root", 0, 755 RK3528_CLKGATE_CON(40), 15, GFLAGS), 756 757 COMPOSITE_NODIV(ACLK_VO_L_ROOT, "aclk_vo_l_root", mux_150m_100m_24m_p, CLK_IS_CRITICAL, 758 RK3528_CLKSEL_CON(84), 1, 2, MFLAGS, 759 RK3528_CLKGATE_CON(41), 8, GFLAGS), 760 GATE(ACLK_MAC_VO, "aclk_gmac0", "aclk_vo_l_root", 0, 761 RK3528_CLKGATE_CON(41), 10, GFLAGS), 762 763 COMPOSITE_NODIV(PCLK_VO_ROOT, "pclk_vo_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, 764 RK3528_CLKSEL_CON(83), 4, 2, MFLAGS, 765 RK3528_CLKGATE_CON(39), 2, GFLAGS), 766 GATE(PCLK_MAC_VO, "pclk_gmac0", "pclk_vo_root", 0, 767 RK3528_CLKGATE_CON(41), 11, GFLAGS), 768 GATE(PCLK_VCDCPHY, "pclk_vcdcphy", "pclk_vo_root", 0, 769 RK3528_CLKGATE_CON(42), 4, GFLAGS), 770 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0, 771 RK3528_CLKGATE_CON(42), 5, GFLAGS), 772 GATE(PCLK_VO_IOC, "pclk_vo_ioc", "pclk_vo_root", CLK_IS_CRITICAL, 773 RK3528_CLKGATE_CON(42), 7, GFLAGS), 774 GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0, 775 RK3528_CLKGATE_CON(42), 11, GFLAGS), 776 GATE(PCLK_UART4, "pclk_uart4", "pclk_vo_root", 0, 777 RK3528_CLKGATE_CON(43), 7, GFLAGS), 778 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_vo_root", 0, 779 RK3528_CLKGATE_CON(43), 9, GFLAGS), 780 GATE(PCLK_I2C7, "pclk_i2c7", "pclk_vo_root", 0, 781 RK3528_CLKGATE_CON(43), 11, GFLAGS), 782 783 GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_vo_root", 0, 784 RK3528_CLKGATE_CON(43), 13, GFLAGS), 785 786 GATE(PCLK_VO_GRF, "pclk_vo_grf", "pclk_vo_root", CLK_IS_CRITICAL, 787 RK3528_CLKGATE_CON(39), 13, GFLAGS), 788 GATE(PCLK_CRU, "pclk_cru", "pclk_vo_root", CLK_IS_CRITICAL, 789 RK3528_CLKGATE_CON(39), 15, GFLAGS), 790 GATE(PCLK_HDMI, "pclk_hdmi", "pclk_vo_root", 0, 791 RK3528_CLKGATE_CON(40), 6, GFLAGS), 792 GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_vo_root", 0, 793 RK3528_CLKGATE_CON(40), 14, GFLAGS), 794 GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo_root", 0, 795 RK3528_CLKGATE_CON(41), 2, GFLAGS), 796 797 COMPOSITE_NODIV(CLK_CORE_VDPP, "clk_core_vdpp", mux_339m_200m_100m_24m_p, 0, 798 RK3528_CLKSEL_CON(83), 10, 2, MFLAGS, 799 RK3528_CLKGATE_CON(39), 12, GFLAGS), 800 COMPOSITE_NODIV(CLK_CORE_RGA2E, "clk_core_rga2e", mux_339m_200m_100m_24m_p, 0, 801 RK3528_CLKSEL_CON(83), 8, 2, MFLAGS, 802 RK3528_CLKGATE_CON(39), 9, GFLAGS), 803 COMPOSITE_NODIV(ACLK_JPEG_ROOT, "aclk_jpeg_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL, 804 RK3528_CLKSEL_CON(84), 9, 2, MFLAGS, 805 RK3528_CLKGATE_CON(41), 15, GFLAGS), 806 GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_root", 0, 807 RK3528_CLKGATE_CON(41), 6, GFLAGS), 808 809 COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL, 810 RK3528_CLKSEL_CON(83), 0, 2, MFLAGS, 811 RK3528_CLKGATE_CON(39), 0, GFLAGS), 812 GATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0, 813 RK3528_CLKGATE_CON(39), 8, GFLAGS), 814 GATE(ACLK_VDPP, "aclk_vdpp", "aclk_vo_root", 0, 815 RK3528_CLKGATE_CON(39), 11, GFLAGS), 816 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo_root", 0, 817 RK3528_CLKGATE_CON(41), 0, GFLAGS), 818 819 COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", mux_gpll_cpll_xin24m_p, 0, 820 RK3528_CLKSEL_CON(85), 6, 2, MFLAGS, 0, 6, DFLAGS, 821 RK3528_CLKGATE_CON(42), 8, GFLAGS), 822 823 COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", mux_gpll_cpll_p, CLK_IS_CRITICAL, 824 RK3528_CLKSEL_CON(83), 15, 1, MFLAGS, 12, 3, DFLAGS, 825 RK3528_CLKGATE_CON(40), 0, GFLAGS), 826 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0, 827 RK3528_CLKGATE_CON(40), 5, GFLAGS), 828 829 COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0, 830 RK3528_CLKSEL_CON(85), 13, 2, MFLAGS, 831 RK3528_CLKGATE_CON(43), 10, GFLAGS), 832 COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_50m_24m_p, 0, 833 RK3528_CLKSEL_CON(86), 0, 2, MFLAGS, 834 RK3528_CLKGATE_CON(43), 12, GFLAGS), 835 GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0, 836 RK3528_CLKGATE_CON(42), 6, GFLAGS), 837 838 GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0, 839 RK3528_CLKGATE_CON(43), 2, GFLAGS), 840 GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0, 841 RK3528_CLKGATE_CON(42), 3, GFLAGS), 842 GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0, 843 RK3528_CLKGATE_CON(43), 14, GFLAGS), 844 GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0, 845 RK3528_CLKGATE_CON(42), 12, GFLAGS), 846 FACTOR(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_sbpi_otpc_ns", 847 0, 1, 2), 848 849 GATE(MCLK_SAI_I2S3, "mclk_sai_i2s3", "mclk_i2s3_8ch_sai_src", 0, 850 RK3528_CLKGATE_CON(42), 2, GFLAGS), 851 COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 852 RK3528_CLKSEL_CON(84), 0, 1, MFLAGS, 853 RK3528_CLKGATE_CON(40), 3, GFLAGS), 854 GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop_src1", CLK_SET_RATE_PARENT, 855 RK3528_CLKGATE_CON(40), 4, GFLAGS), 856 FACTOR_GATE(DCLK_CVBS, "dclk_cvbs", "dclk_vop1", 0, 1, 4, 857 RK3528_CLKGATE_CON(41), 4, GFLAGS), 858 GATE(DCLK_4X_CVBS, "dclk_4x_cvbs", "dclk_vop1", 0, 859 RK3528_CLKGATE_CON(41), 5, GFLAGS), 860 861 FACTOR_GATE(CLK_SFR_HDMI, "clk_sfr_hdmi", "dclk_vop_src1", 0, 1, 4, 862 RK3528_CLKGATE_CON(40), 7, GFLAGS), 863 864 GATE(CLK_SPDIF_HDMI, "clk_spdif_hdmi", "mclk_spdif_src", 0, 865 RK3528_CLKGATE_CON(40), 10, GFLAGS), 866 GATE(MCLK_SPDIF, "mclk_spdif", "mclk_spdif_src", 0, 867 RK3528_CLKGATE_CON(37), 15, GFLAGS), 868 GATE(CLK_CEC_HDMI, "clk_cec_hdmi", "clk_32k", 0, 869 RK3528_CLKGATE_CON(40), 8, GFLAGS), 870 871 /* vpu */ 872 GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0, 873 RK3528_CLKGATE_CON(26), 5, GFLAGS), 874 GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0, 875 RK3528_CLKGATE_CON(27), 1, GFLAGS), 876 GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0, 877 RK3528_CLKGATE_CON(33), 4, GFLAGS), 878 GATE(CLK_PCIE_AUX, "clk_pcie_aux", "xin24m", 0, 879 RK3528_CLKGATE_CON(30), 2, GFLAGS), 880 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, 881 RK3528_CLKGATE_CON(26), 3, GFLAGS), 882 GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0, 883 RK3528_CLKGATE_CON(33), 2, GFLAGS), 884 COMPOSITE(CCLK_SRC_SDIO0, "cclk_src_sdio0", mux_gpll_cpll_xin24m_p, 0, 885 RK3528_CLKSEL_CON(72), 6, 2, MFLAGS, 0, 6, DFLAGS, 886 RK3528_CLKGATE_CON(32), 1, GFLAGS), 887 888 COMPOSITE_NODIV(PCLK_VPU_ROOT, "pclk_vpu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, 889 RK3528_CLKSEL_CON(61), 4, 2, MFLAGS, 890 RK3528_CLKGATE_CON(25), 5, GFLAGS), 891 GATE(PCLK_VPU_GRF, "pclk_vpu_grf", "pclk_vpu_root", CLK_IS_CRITICAL, 892 RK3528_CLKGATE_CON(25), 12, GFLAGS), 893 GATE(PCLK_CRU_PCIE, "pclk_cru_pcie", "pclk_vpu_root", CLK_IS_CRITICAL, 894 RK3528_CLKGATE_CON(25), 11, GFLAGS), 895 GATE(PCLK_UART6, "pclk_uart6", "pclk_vpu_root", 0, 896 RK3528_CLKGATE_CON(27), 11, GFLAGS), 897 GATE(PCLK_CAN2, "pclk_can2", "pclk_vpu_root", 0, 898 RK3528_CLKGATE_CON(32), 7, GFLAGS), 899 GATE(PCLK_SPI1, "pclk_spi1", "pclk_vpu_root", 0, 900 RK3528_CLKGATE_CON(27), 4, GFLAGS), 901 GATE(PCLK_CAN3, "pclk_can3", "pclk_vpu_root", 0, 902 RK3528_CLKGATE_CON(32), 9, GFLAGS), 903 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vpu_root", 0, 904 RK3528_CLKGATE_CON(27), 0, GFLAGS), 905 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vpu_root", 0, 906 RK3528_CLKGATE_CON(26), 4, GFLAGS), 907 GATE(PCLK_SARADC, "pclk_saradc", "pclk_vpu_root", 0, 908 RK3528_CLKGATE_CON(32), 11, GFLAGS), 909 GATE(PCLK_ACODEC, "pclk_acodec", "pclk_vpu_root", 0, 910 RK3528_CLKGATE_CON(26), 13, GFLAGS), 911 GATE(PCLK_UART7, "pclk_uart7", "pclk_vpu_root", 0, 912 RK3528_CLKGATE_CON(27), 13, GFLAGS), 913 GATE(PCLK_UART5, "pclk_uart5", "pclk_vpu_root", 0, 914 RK3528_CLKGATE_CON(27), 9, GFLAGS), 915 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vpu_root", 0, 916 RK3528_CLKGATE_CON(32), 14, GFLAGS), 917 GATE(PCLK_PCIE, "pclk_pcie", "pclk_vpu_root", 0, 918 RK3528_CLKGATE_CON(30), 1, GFLAGS), 919 GATE(PCLK_UART2, "pclk_uart2", "pclk_vpu_root", 0, 920 RK3528_CLKGATE_CON(27), 7, GFLAGS), 921 GATE(PCLK_VPU_IOC, "pclk_vpu_ioc", "pclk_vpu_root", CLK_IS_CRITICAL, 922 RK3528_CLKGATE_CON(26), 8, GFLAGS), 923 GATE(PCLK_PIPE_GRF, "pclk_pipe_grf", "pclk_vpu_root", CLK_IS_CRITICAL, 924 RK3528_CLKGATE_CON(30), 7, GFLAGS), 925 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_vpu_root", 0, 926 RK3528_CLKGATE_CON(28), 1, GFLAGS), 927 GATE(PCLK_PCIE_PHY, "pclk_pcie_phy", "pclk_vpu_root", 0, 928 RK3528_CLKGATE_CON(30), 6, GFLAGS), 929 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_vpu_root", 0, 930 RK3528_CLKGATE_CON(27), 15, GFLAGS), 931 GATE(PCLK_MAC_VPU, "pclk_gmac1", "pclk_vpu_root", CLK_IS_CRITICAL, 932 RK3528_CLKGATE_CON(28), 6, GFLAGS), 933 GATE(PCLK_I2C6, "pclk_i2c6", "pclk_vpu_root", 0, 934 RK3528_CLKGATE_CON(28), 3, GFLAGS), 935 936 COMPOSITE_NODIV(ACLK_VPU_L_ROOT, "aclk_vpu_l_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL, 937 RK3528_CLKSEL_CON(60), 0, 2, MFLAGS, 938 RK3528_CLKGATE_CON(25), 0, GFLAGS), 939 GATE(ACLK_EMMC, "aclk_emmc", "aclk_vpu_l_root", 0, 940 RK3528_CLKGATE_CON(26), 1, GFLAGS), 941 GATE(ACLK_MAC_VPU, "aclk_gmac1", "aclk_vpu_l_root", 0, 942 RK3528_CLKGATE_CON(28), 5, GFLAGS), 943 GATE(ACLK_PCIE, "aclk_pcie", "aclk_vpu_l_root", 0, 944 RK3528_CLKGATE_CON(30), 3, GFLAGS), 945 946 GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_vpu_l_root", 0, 947 RK3528_CLKGATE_CON(33), 1, GFLAGS), 948 949 COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, 950 RK3528_CLKSEL_CON(61), 2, 2, MFLAGS, 951 RK3528_CLKGATE_CON(25), 4, GFLAGS), 952 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_root", 0, 953 RK3528_CLKGATE_CON(25), 10, GFLAGS), 954 GATE(HCLK_SFC, "hclk_sfc", "hclk_vpu_root", 0, 955 RK3528_CLKGATE_CON(25), 13, GFLAGS), 956 GATE(HCLK_EMMC, "hclk_emmc", "hclk_vpu_root", 0, 957 RK3528_CLKGATE_CON(26), 0, GFLAGS), 958 GATE(HCLK_SAI_I2S0, "hclk_sai_i2s0", "hclk_vpu_root", 0, 959 RK3528_CLKGATE_CON(26), 9, GFLAGS), 960 GATE(HCLK_SAI_I2S2, "hclk_sai_i2s2", "hclk_vpu_root", 0, 961 RK3528_CLKGATE_CON(26), 11, GFLAGS), 962 963 GATE(HCLK_PCIE_SLV, "hclk_pcie_slv", "hclk_vpu_root", 0, 964 RK3528_CLKGATE_CON(30), 4, GFLAGS), 965 GATE(HCLK_PCIE_DBI, "hclk_pcie_dbi", "hclk_vpu_root", 0, 966 RK3528_CLKGATE_CON(30), 5, GFLAGS), 967 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_vpu_root", 0, 968 RK3528_CLKGATE_CON(32), 2, GFLAGS), 969 GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_vpu_root", 0, 970 RK3528_CLKGATE_CON(32), 4, GFLAGS), 971 972 COMPOSITE_NOMUX(CLK_GMAC1_VPU_25M, "clk_gmac1_25m", "ppll", 0, 973 RK3528_CLKSEL_CON(60), 2, 8, DFLAGS, 974 RK3528_CLKGATE_CON(25), 1, GFLAGS), 975 COMPOSITE_NOMUX(CLK_PPLL_125M_MATRIX, "clk_ppll_125m_src", "ppll", 0, 976 RK3528_CLKSEL_CON(60), 10, 5, DFLAGS, 977 RK3528_CLKGATE_CON(25), 2, GFLAGS), 978 979 COMPOSITE(CLK_CAN3, "clk_can3", mux_gpll_cpll_p, 0, 980 RK3528_CLKSEL_CON(73), 13, 1, MFLAGS, 7, 6, DFLAGS, 981 RK3528_CLKGATE_CON(32), 10, GFLAGS), 982 COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_50m_24m_p, 0, 983 RK3528_CLKSEL_CON(64), 0, 2, MFLAGS, 984 RK3528_CLKGATE_CON(28), 4, GFLAGS), 985 986 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_gpll_cpll_xin24m_p, 0, 987 RK3528_CLKSEL_CON(61), 12, 2, MFLAGS, 6, 6, DFLAGS, 988 RK3528_CLKGATE_CON(25), 14, GFLAGS), 989 COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", mux_gpll_cpll_xin24m_p, 0, 990 RK3528_CLKSEL_CON(62), 6, 2, MFLAGS, 0, 6, DFLAGS, 991 RK3528_CLKGATE_CON(25), 15, GFLAGS), 992 993 COMPOSITE_NODIV(ACLK_VPU_ROOT, "aclk_vpu_root", 994 mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, 995 RK3528_CLKSEL_CON(61), 0, 2, MFLAGS, 996 RK3528_CLKGATE_CON(25), 3, GFLAGS), 997 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_root", 0, 998 RK3528_CLKGATE_CON(25), 9, GFLAGS), 999 1000 COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0, 1001 RK3528_CLKSEL_CON(63), 10, 2, MFLAGS, 1002 RK3528_CLKGATE_CON(27), 5, GFLAGS), 1003 COMPOSITE(CCLK_SRC_SDIO1, "cclk_src_sdio1", mux_gpll_cpll_xin24m_p, 0, 1004 RK3528_CLKSEL_CON(72), 14, 2, MFLAGS, 8, 6, DFLAGS, 1005 RK3528_CLKGATE_CON(32), 3, GFLAGS), 1006 COMPOSITE(CLK_CAN2, "clk_can2", mux_gpll_cpll_p, 0, 1007 RK3528_CLKSEL_CON(73), 6, 1, MFLAGS, 0, 6, DFLAGS, 1008 RK3528_CLKGATE_CON(32), 8, GFLAGS), 1009 COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0, 1010 RK3528_CLKSEL_CON(74), 3, 5, DFLAGS, 1011 RK3528_CLKGATE_CON(32), 15, GFLAGS), 1012 COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0, 1013 RK3528_CLKSEL_CON(74), 0, 3, DFLAGS, 1014 RK3528_CLKGATE_CON(32), 12, GFLAGS), 1015 COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0, 1016 RK3528_CLKSEL_CON(74), 8, 5, DFLAGS, 1017 RK3528_CLKGATE_CON(33), 0, GFLAGS), 1018 COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", mux_200m_100m_50m_24m_p, 0, 1019 RK3528_CLKSEL_CON(62), 8, 2, MFLAGS, 1020 RK3528_CLKGATE_CON(26), 2, GFLAGS), 1021 COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_i2s2_2ch_sai_src", 0, 1022 RK3528_CLKSEL_CON(63), 0, 8, DFLAGS, 1023 RK3528_CLKGATE_CON(26), 14, GFLAGS), 1024 COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0, 1025 RK3528_CLKSEL_CON(63), 12, 2, MFLAGS, 1026 RK3528_CLKGATE_CON(28), 0, GFLAGS), 1027 COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_50m_24m_p, 0, 1028 RK3528_CLKSEL_CON(63), 14, 2, MFLAGS, 1029 RK3528_CLKGATE_CON(28), 2, GFLAGS), 1030 COMPOSITE_NODIV(MCLK_SAI_I2S0, "mclk_sai_i2s0", mclk_sai_i2s0_p, CLK_SET_RATE_PARENT, 1031 RK3528_CLKSEL_CON(62), 10, 1, MFLAGS, 1032 RK3528_CLKGATE_CON(26), 10, GFLAGS), 1033 GATE(MCLK_SAI_I2S2, "mclk_sai_i2s2", "mclk_i2s2_2ch_sai_src", 0, 1034 RK3528_CLKGATE_CON(26), 12, GFLAGS), 1035 1036 /* pcie */ 1037 COMPOSITE_NOMUX(CLK_PPLL_100M_MATRIX, "clk_ppll_100m_src", "ppll", CLK_IS_CRITICAL, 1038 RK3528_PCIE_CLKSEL_CON(1), 2, 5, DFLAGS, 1039 RK3528_PCIE_CLKGATE_CON(0), 1, GFLAGS), 1040 COMPOSITE_NOMUX(CLK_PPLL_50M_MATRIX, "clk_ppll_50m_src", "ppll", CLK_IS_CRITICAL, 1041 RK3528_PCIE_CLKSEL_CON(1), 7, 5, DFLAGS, 1042 RK3528_PCIE_CLKGATE_CON(0), 2, GFLAGS), 1043 MUX(CLK_REF_PCIE_INNER_PHY, "clk_ref_pcie_inner_phy", clk_ref_pcie_inner_phy_p, 0, 1044 RK3528_PCIE_CLKSEL_CON(1), 13, 1, MFLAGS), 1045 FACTOR(CLK_REF_PCIE_100M_PHY, "clk_ref_pcie_100m_phy", "clk_ppll_100m_src", 1046 0, 1, 1), 1047 1048 /* gmac */ 1049 DIV(CLK_GMAC0_SRC, "clk_gmac0_src", "gmac0", 0, 1050 RK3528_CLKSEL_CON(84), 3, 6, DFLAGS), 1051 GATE(CLK_GMAC0_TX, "clk_gmac0_tx", "clk_gmac0_src", 0, 1052 RK3528_CLKGATE_CON(41), 13, GFLAGS), 1053 GATE(CLK_GMAC0_RX, "clk_gmac0_rx", "clk_gmac0_src", 0, 1054 RK3528_CLKGATE_CON(41), 14, GFLAGS), 1055 GATE(CLK_GMAC0_RMII_50M, "clk_gmac0_rmii_50m", "gmac0", 0, 1056 RK3528_CLKGATE_CON(41), 12, GFLAGS), 1057 1058 FACTOR(CLK_GMAC1_RMII_VPU, "clk_gmac1_50m", "clk_ppll_50m_src", 1059 0, 1, 1), 1060 FACTOR(CLK_GMAC1_SRC_VPU, "clk_gmac1_125m", "clk_ppll_125m_src", 1061 0, 1, 1), 1062 }; 1063 1064 static int __init clk_rk3528_probe(struct platform_device *pdev) 1065 { 1066 struct rockchip_clk_provider *ctx; 1067 struct device *dev = &pdev->dev; 1068 struct device_node *np = dev->of_node; 1069 unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches); 1070 unsigned long nr_clks; 1071 void __iomem *reg_base; 1072 1073 nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches, 1074 nr_branches) + 1; 1075 1076 reg_base = devm_platform_ioremap_resource(pdev, 0); 1077 if (IS_ERR(reg_base)) 1078 return dev_err_probe(dev, PTR_ERR(reg_base), 1079 "could not map cru region"); 1080 1081 ctx = rockchip_clk_init(np, reg_base, nr_clks); 1082 if (IS_ERR(ctx)) 1083 return dev_err_probe(dev, PTR_ERR(ctx), 1084 "rockchip clk init failed"); 1085 1086 rockchip_clk_register_plls(ctx, rk3528_pll_clks, 1087 ARRAY_SIZE(rk3528_pll_clks), 1088 RK3528_GRF_SOC_STATUS0); 1089 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 1090 mux_armclk, ARRAY_SIZE(mux_armclk), 1091 &rk3528_cpuclk_data, rk3528_cpuclk_rates, 1092 ARRAY_SIZE(rk3528_cpuclk_rates)); 1093 rockchip_clk_register_branches(ctx, rk3528_clk_branches, nr_branches); 1094 1095 rk3528_rst_init(np, reg_base); 1096 1097 rockchip_register_restart_notifier(ctx, RK3528_GLB_SRST_FST, NULL); 1098 1099 rockchip_clk_of_add_provider(np, ctx); 1100 1101 return 0; 1102 } 1103 1104 static const struct of_device_id clk_rk3528_match_table[] = { 1105 { .compatible = "rockchip,rk3528-cru" }, 1106 { /* end */ } 1107 }; 1108 1109 static struct platform_driver clk_rk3528_driver = { 1110 .driver = { 1111 .name = "clk-rk3528", 1112 .of_match_table = clk_rk3528_match_table, 1113 .suppress_bind_attrs = true, 1114 }, 1115 }; 1116 builtin_platform_driver_probe(clk_rk3528_driver, clk_rk3528_probe); 1117