1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2014 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 * 6 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 7 * Author: Xing Zheng <zhengxing@rock-chips.com> 8 */ 9 10 #include <asm/div64.h> 11 #include <linux/slab.h> 12 #include <linux/io.h> 13 #include <linux/delay.h> 14 #include <linux/clk-provider.h> 15 #include <linux/iopoll.h> 16 #include <linux/regmap.h> 17 #include <linux/clk.h> 18 #include "clk.h" 19 20 #define PLL_MODE_MASK 0x3 21 #define PLL_MODE_SLOW 0x0 22 #define PLL_MODE_NORM 0x1 23 #define PLL_MODE_DEEP 0x2 24 #define PLL_RK3328_MODE_MASK 0x1 25 26 struct rockchip_clk_pll { 27 struct clk_hw hw; 28 29 struct clk_mux pll_mux; 30 const struct clk_ops *pll_mux_ops; 31 32 struct notifier_block clk_nb; 33 34 void __iomem *reg_base; 35 int lock_offset; 36 unsigned int lock_shift; 37 enum rockchip_pll_type type; 38 u8 flags; 39 const struct rockchip_pll_rate_table *rate_table; 40 unsigned int rate_count; 41 spinlock_t *lock; 42 43 struct rockchip_clk_provider *ctx; 44 }; 45 46 #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw) 47 #define to_rockchip_clk_pll_nb(nb) \ 48 container_of(nb, struct rockchip_clk_pll, clk_nb) 49 50 static const struct rockchip_pll_rate_table *rockchip_get_pll_settings( 51 struct rockchip_clk_pll *pll, unsigned long rate) 52 { 53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; 54 int i; 55 56 for (i = 0; i < pll->rate_count; i++) { 57 if (rate == rate_table[i].rate) 58 return &rate_table[i]; 59 } 60 61 return NULL; 62 } 63 64 static long rockchip_pll_round_rate(struct clk_hw *hw, 65 unsigned long drate, unsigned long *prate) 66 { 67 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; 69 int i; 70 71 /* Assumming rate_table is in descending order */ 72 for (i = 0; i < pll->rate_count; i++) { 73 if (drate >= rate_table[i].rate) 74 return rate_table[i].rate; 75 } 76 77 /* return minimum supported value */ 78 return rate_table[i - 1].rate; 79 } 80 81 /* 82 * Wait for the pll to reach the locked state. 83 * The calling set_rate function is responsible for making sure the 84 * grf regmap is available. 85 */ 86 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) 87 { 88 struct regmap *grf = pll->ctx->grf; 89 unsigned int val; 90 int ret; 91 92 ret = regmap_read_poll_timeout(grf, pll->lock_offset, val, 93 val & BIT(pll->lock_shift), 0, 1000); 94 if (ret) 95 pr_err("%s: timeout waiting for pll to lock\n", __func__); 96 97 return ret; 98 } 99 100 /* 101 * PLL used in RK3036 102 */ 103 104 #define RK3036_PLLCON(i) (i * 0x4) 105 #define RK3036_PLLCON0_FBDIV_MASK 0xfff 106 #define RK3036_PLLCON0_FBDIV_SHIFT 0 107 #define RK3036_PLLCON0_POSTDIV1_MASK 0x7 108 #define RK3036_PLLCON0_POSTDIV1_SHIFT 12 109 #define RK3036_PLLCON1_REFDIV_MASK 0x3f 110 #define RK3036_PLLCON1_REFDIV_SHIFT 0 111 #define RK3036_PLLCON1_POSTDIV2_MASK 0x7 112 #define RK3036_PLLCON1_POSTDIV2_SHIFT 6 113 #define RK3036_PLLCON1_LOCK_STATUS BIT(10) 114 #define RK3036_PLLCON1_DSMPD_MASK 0x1 115 #define RK3036_PLLCON1_DSMPD_SHIFT 12 116 #define RK3036_PLLCON1_PWRDOWN BIT(13) 117 #define RK3036_PLLCON2_FRAC_MASK 0xffffff 118 #define RK3036_PLLCON2_FRAC_SHIFT 0 119 120 static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll) 121 { 122 u32 pllcon; 123 int ret; 124 125 /* 126 * Lock time typical 250, max 500 input clock cycles @24MHz 127 * So define a very safe maximum of 1000us, meaning 24000 cycles. 128 */ 129 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1), 130 pllcon, 131 pllcon & RK3036_PLLCON1_LOCK_STATUS, 132 0, 1000); 133 if (ret) 134 pr_err("%s: timeout waiting for pll to lock\n", __func__); 135 136 return ret; 137 } 138 139 static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll, 140 struct rockchip_pll_rate_table *rate) 141 { 142 u32 pllcon; 143 144 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(0)); 145 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) 146 & RK3036_PLLCON0_FBDIV_MASK); 147 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) 148 & RK3036_PLLCON0_POSTDIV1_MASK); 149 150 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(1)); 151 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) 152 & RK3036_PLLCON1_REFDIV_MASK); 153 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) 154 & RK3036_PLLCON1_POSTDIV2_MASK); 155 rate->dsmpd = ((pllcon >> RK3036_PLLCON1_DSMPD_SHIFT) 156 & RK3036_PLLCON1_DSMPD_MASK); 157 158 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); 159 rate->frac = ((pllcon >> RK3036_PLLCON2_FRAC_SHIFT) 160 & RK3036_PLLCON2_FRAC_MASK); 161 } 162 163 static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw, 164 unsigned long prate) 165 { 166 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 167 struct rockchip_pll_rate_table cur; 168 u64 rate64 = prate; 169 170 rockchip_rk3036_pll_get_params(pll, &cur); 171 172 rate64 *= cur.fbdiv; 173 do_div(rate64, cur.refdiv); 174 175 if (cur.dsmpd == 0) { 176 /* fractional mode */ 177 u64 frac_rate64 = prate * cur.frac; 178 179 do_div(frac_rate64, cur.refdiv); 180 rate64 += frac_rate64 >> 24; 181 } 182 183 do_div(rate64, cur.postdiv1); 184 do_div(rate64, cur.postdiv2); 185 186 return (unsigned long)rate64; 187 } 188 189 static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, 190 const struct rockchip_pll_rate_table *rate) 191 { 192 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; 193 struct clk_mux *pll_mux = &pll->pll_mux; 194 struct rockchip_pll_rate_table cur; 195 u32 pllcon; 196 int rate_change_remuxed = 0; 197 int cur_parent; 198 int ret; 199 200 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 201 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, 202 rate->postdiv2, rate->dsmpd, rate->frac); 203 204 rockchip_rk3036_pll_get_params(pll, &cur); 205 cur.rate = 0; 206 207 if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) { 208 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); 209 if (cur_parent == PLL_MODE_NORM) { 210 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); 211 rate_change_remuxed = 1; 212 } 213 } 214 215 /* update pll values */ 216 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, 217 RK3036_PLLCON0_FBDIV_SHIFT) | 218 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, 219 RK3036_PLLCON0_POSTDIV1_SHIFT), 220 pll->reg_base + RK3036_PLLCON(0)); 221 222 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, 223 RK3036_PLLCON1_REFDIV_SHIFT) | 224 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, 225 RK3036_PLLCON1_POSTDIV2_SHIFT) | 226 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, 227 RK3036_PLLCON1_DSMPD_SHIFT), 228 pll->reg_base + RK3036_PLLCON(1)); 229 230 /* GPLL CON2 is not HIWORD_MASK */ 231 pllcon = readl_relaxed(pll->reg_base + RK3036_PLLCON(2)); 232 pllcon &= ~(RK3036_PLLCON2_FRAC_MASK << RK3036_PLLCON2_FRAC_SHIFT); 233 pllcon |= rate->frac << RK3036_PLLCON2_FRAC_SHIFT; 234 writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2)); 235 236 /* wait for the pll to lock */ 237 ret = rockchip_rk3036_pll_wait_lock(pll); 238 if (ret) { 239 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", 240 __func__); 241 rockchip_rk3036_pll_set_params(pll, &cur); 242 } 243 244 if (rate_change_remuxed) 245 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); 246 247 return ret; 248 } 249 250 static int rockchip_rk3036_pll_set_rate(struct clk_hw *hw, unsigned long drate, 251 unsigned long prate) 252 { 253 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 254 const struct rockchip_pll_rate_table *rate; 255 256 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", 257 __func__, __clk_get_name(hw->clk), drate, prate); 258 259 /* Get required rate settings from table */ 260 rate = rockchip_get_pll_settings(pll, drate); 261 if (!rate) { 262 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 263 drate, __clk_get_name(hw->clk)); 264 return -EINVAL; 265 } 266 267 return rockchip_rk3036_pll_set_params(pll, rate); 268 } 269 270 static int rockchip_rk3036_pll_enable(struct clk_hw *hw) 271 { 272 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 273 274 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), 275 pll->reg_base + RK3036_PLLCON(1)); 276 rockchip_rk3036_pll_wait_lock(pll); 277 278 return 0; 279 } 280 281 static void rockchip_rk3036_pll_disable(struct clk_hw *hw) 282 { 283 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 284 285 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, 286 RK3036_PLLCON1_PWRDOWN, 0), 287 pll->reg_base + RK3036_PLLCON(1)); 288 } 289 290 static int rockchip_rk3036_pll_is_enabled(struct clk_hw *hw) 291 { 292 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 293 u32 pllcon = readl(pll->reg_base + RK3036_PLLCON(1)); 294 295 return !(pllcon & RK3036_PLLCON1_PWRDOWN); 296 } 297 298 static int rockchip_rk3036_pll_init(struct clk_hw *hw) 299 { 300 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 301 const struct rockchip_pll_rate_table *rate; 302 struct rockchip_pll_rate_table cur; 303 unsigned long drate; 304 305 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) 306 return 0; 307 308 drate = clk_hw_get_rate(hw); 309 rate = rockchip_get_pll_settings(pll, drate); 310 311 /* when no rate setting for the current rate, rely on clk_set_rate */ 312 if (!rate) 313 return 0; 314 315 rockchip_rk3036_pll_get_params(pll, &cur); 316 317 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), 318 drate); 319 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 320 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, 321 cur.dsmpd, cur.frac); 322 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 323 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, 324 rate->dsmpd, rate->frac); 325 326 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || 327 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || 328 rate->dsmpd != cur.dsmpd || 329 (!cur.dsmpd && (rate->frac != cur.frac))) { 330 struct clk *parent = clk_get_parent(hw->clk); 331 332 if (!parent) { 333 pr_warn("%s: parent of %s not available\n", 334 __func__, __clk_get_name(hw->clk)); 335 return 0; 336 } 337 338 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", 339 __func__, __clk_get_name(hw->clk)); 340 rockchip_rk3036_pll_set_params(pll, rate); 341 } 342 343 return 0; 344 } 345 346 static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = { 347 .recalc_rate = rockchip_rk3036_pll_recalc_rate, 348 .enable = rockchip_rk3036_pll_enable, 349 .disable = rockchip_rk3036_pll_disable, 350 .is_enabled = rockchip_rk3036_pll_is_enabled, 351 }; 352 353 static const struct clk_ops rockchip_rk3036_pll_clk_ops = { 354 .recalc_rate = rockchip_rk3036_pll_recalc_rate, 355 .round_rate = rockchip_pll_round_rate, 356 .set_rate = rockchip_rk3036_pll_set_rate, 357 .enable = rockchip_rk3036_pll_enable, 358 .disable = rockchip_rk3036_pll_disable, 359 .is_enabled = rockchip_rk3036_pll_is_enabled, 360 .init = rockchip_rk3036_pll_init, 361 }; 362 363 /* 364 * PLL used in RK3066, RK3188 and RK3288 365 */ 366 367 #define RK3066_PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1) 368 369 #define RK3066_PLLCON(i) (i * 0x4) 370 #define RK3066_PLLCON0_OD_MASK 0xf 371 #define RK3066_PLLCON0_OD_SHIFT 0 372 #define RK3066_PLLCON0_NR_MASK 0x3f 373 #define RK3066_PLLCON0_NR_SHIFT 8 374 #define RK3066_PLLCON1_NF_MASK 0x1fff 375 #define RK3066_PLLCON1_NF_SHIFT 0 376 #define RK3066_PLLCON2_NB_MASK 0xfff 377 #define RK3066_PLLCON2_NB_SHIFT 0 378 #define RK3066_PLLCON3_RESET (1 << 5) 379 #define RK3066_PLLCON3_PWRDOWN (1 << 1) 380 #define RK3066_PLLCON3_BYPASS (1 << 0) 381 382 static void rockchip_rk3066_pll_get_params(struct rockchip_clk_pll *pll, 383 struct rockchip_pll_rate_table *rate) 384 { 385 u32 pllcon; 386 387 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); 388 rate->nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) 389 & RK3066_PLLCON0_NR_MASK) + 1; 390 rate->no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) 391 & RK3066_PLLCON0_OD_MASK) + 1; 392 393 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); 394 rate->nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) 395 & RK3066_PLLCON1_NF_MASK) + 1; 396 397 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); 398 rate->nb = ((pllcon >> RK3066_PLLCON2_NB_SHIFT) 399 & RK3066_PLLCON2_NB_MASK) + 1; 400 } 401 402 static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw, 403 unsigned long prate) 404 { 405 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 406 struct rockchip_pll_rate_table cur; 407 u64 rate64 = prate; 408 u32 pllcon; 409 410 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); 411 if (pllcon & RK3066_PLLCON3_BYPASS) { 412 pr_debug("%s: pll %s is bypassed\n", __func__, 413 clk_hw_get_name(hw)); 414 return prate; 415 } 416 417 rockchip_rk3066_pll_get_params(pll, &cur); 418 419 rate64 *= cur.nf; 420 do_div(rate64, cur.nr); 421 do_div(rate64, cur.no); 422 423 return (unsigned long)rate64; 424 } 425 426 static int rockchip_rk3066_pll_set_params(struct rockchip_clk_pll *pll, 427 const struct rockchip_pll_rate_table *rate) 428 { 429 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; 430 struct clk_mux *pll_mux = &pll->pll_mux; 431 struct rockchip_pll_rate_table cur; 432 int rate_change_remuxed = 0; 433 int cur_parent; 434 int ret; 435 436 pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n", 437 __func__, rate->rate, rate->nr, rate->no, rate->nf); 438 439 rockchip_rk3066_pll_get_params(pll, &cur); 440 cur.rate = 0; 441 442 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); 443 if (cur_parent == PLL_MODE_NORM) { 444 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); 445 rate_change_remuxed = 1; 446 } 447 448 /* enter reset mode */ 449 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0), 450 pll->reg_base + RK3066_PLLCON(3)); 451 452 /* update pll values */ 453 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, 454 RK3066_PLLCON0_NR_SHIFT) | 455 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK, 456 RK3066_PLLCON0_OD_SHIFT), 457 pll->reg_base + RK3066_PLLCON(0)); 458 459 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, 460 RK3066_PLLCON1_NF_SHIFT), 461 pll->reg_base + RK3066_PLLCON(1)); 462 writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK, 463 RK3066_PLLCON2_NB_SHIFT), 464 pll->reg_base + RK3066_PLLCON(2)); 465 466 /* leave reset and wait the reset_delay */ 467 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0), 468 pll->reg_base + RK3066_PLLCON(3)); 469 udelay(RK3066_PLL_RESET_DELAY(rate->nr)); 470 471 /* wait for the pll to lock */ 472 ret = rockchip_pll_wait_lock(pll); 473 if (ret) { 474 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", 475 __func__); 476 rockchip_rk3066_pll_set_params(pll, &cur); 477 } 478 479 if (rate_change_remuxed) 480 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); 481 482 return ret; 483 } 484 485 static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate, 486 unsigned long prate) 487 { 488 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 489 const struct rockchip_pll_rate_table *rate; 490 491 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", 492 __func__, clk_hw_get_name(hw), drate, prate); 493 494 /* Get required rate settings from table */ 495 rate = rockchip_get_pll_settings(pll, drate); 496 if (!rate) { 497 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 498 drate, clk_hw_get_name(hw)); 499 return -EINVAL; 500 } 501 502 return rockchip_rk3066_pll_set_params(pll, rate); 503 } 504 505 static int rockchip_rk3066_pll_enable(struct clk_hw *hw) 506 { 507 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 508 509 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0), 510 pll->reg_base + RK3066_PLLCON(3)); 511 rockchip_pll_wait_lock(pll); 512 513 return 0; 514 } 515 516 static void rockchip_rk3066_pll_disable(struct clk_hw *hw) 517 { 518 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 519 520 writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN, 521 RK3066_PLLCON3_PWRDOWN, 0), 522 pll->reg_base + RK3066_PLLCON(3)); 523 } 524 525 static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw) 526 { 527 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 528 u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3)); 529 530 return !(pllcon & RK3066_PLLCON3_PWRDOWN); 531 } 532 533 static int rockchip_rk3066_pll_init(struct clk_hw *hw) 534 { 535 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 536 const struct rockchip_pll_rate_table *rate; 537 struct rockchip_pll_rate_table cur; 538 unsigned long drate; 539 540 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) 541 return 0; 542 543 drate = clk_hw_get_rate(hw); 544 rate = rockchip_get_pll_settings(pll, drate); 545 546 /* when no rate setting for the current rate, rely on clk_set_rate */ 547 if (!rate) 548 return 0; 549 550 rockchip_rk3066_pll_get_params(pll, &cur); 551 552 pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), nb(%d:%d)\n", 553 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, 554 rate->no, cur.no, rate->nf, cur.nf, rate->nb, cur.nb); 555 if (rate->nr != cur.nr || rate->no != cur.no || rate->nf != cur.nf 556 || rate->nb != cur.nb) { 557 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", 558 __func__, clk_hw_get_name(hw)); 559 rockchip_rk3066_pll_set_params(pll, rate); 560 } 561 562 return 0; 563 } 564 565 static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = { 566 .recalc_rate = rockchip_rk3066_pll_recalc_rate, 567 .enable = rockchip_rk3066_pll_enable, 568 .disable = rockchip_rk3066_pll_disable, 569 .is_enabled = rockchip_rk3066_pll_is_enabled, 570 }; 571 572 static const struct clk_ops rockchip_rk3066_pll_clk_ops = { 573 .recalc_rate = rockchip_rk3066_pll_recalc_rate, 574 .round_rate = rockchip_pll_round_rate, 575 .set_rate = rockchip_rk3066_pll_set_rate, 576 .enable = rockchip_rk3066_pll_enable, 577 .disable = rockchip_rk3066_pll_disable, 578 .is_enabled = rockchip_rk3066_pll_is_enabled, 579 .init = rockchip_rk3066_pll_init, 580 }; 581 582 /* 583 * PLL used in RK3399 584 */ 585 586 #define RK3399_PLLCON(i) (i * 0x4) 587 #define RK3399_PLLCON0_FBDIV_MASK 0xfff 588 #define RK3399_PLLCON0_FBDIV_SHIFT 0 589 #define RK3399_PLLCON1_REFDIV_MASK 0x3f 590 #define RK3399_PLLCON1_REFDIV_SHIFT 0 591 #define RK3399_PLLCON1_POSTDIV1_MASK 0x7 592 #define RK3399_PLLCON1_POSTDIV1_SHIFT 8 593 #define RK3399_PLLCON1_POSTDIV2_MASK 0x7 594 #define RK3399_PLLCON1_POSTDIV2_SHIFT 12 595 #define RK3399_PLLCON2_FRAC_MASK 0xffffff 596 #define RK3399_PLLCON2_FRAC_SHIFT 0 597 #define RK3399_PLLCON2_LOCK_STATUS BIT(31) 598 #define RK3399_PLLCON3_PWRDOWN BIT(0) 599 #define RK3399_PLLCON3_DSMPD_MASK 0x1 600 #define RK3399_PLLCON3_DSMPD_SHIFT 3 601 602 static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll) 603 { 604 u32 pllcon; 605 int ret; 606 607 /* 608 * Lock time typical 250, max 500 input clock cycles @24MHz 609 * So define a very safe maximum of 1000us, meaning 24000 cycles. 610 */ 611 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2), 612 pllcon, 613 pllcon & RK3399_PLLCON2_LOCK_STATUS, 614 0, 1000); 615 if (ret) 616 pr_err("%s: timeout waiting for pll to lock\n", __func__); 617 618 return ret; 619 } 620 621 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll, 622 struct rockchip_pll_rate_table *rate) 623 { 624 u32 pllcon; 625 626 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(0)); 627 rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT) 628 & RK3399_PLLCON0_FBDIV_MASK); 629 630 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(1)); 631 rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT) 632 & RK3399_PLLCON1_REFDIV_MASK); 633 rate->postdiv1 = ((pllcon >> RK3399_PLLCON1_POSTDIV1_SHIFT) 634 & RK3399_PLLCON1_POSTDIV1_MASK); 635 rate->postdiv2 = ((pllcon >> RK3399_PLLCON1_POSTDIV2_SHIFT) 636 & RK3399_PLLCON1_POSTDIV2_MASK); 637 638 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); 639 rate->frac = ((pllcon >> RK3399_PLLCON2_FRAC_SHIFT) 640 & RK3399_PLLCON2_FRAC_MASK); 641 642 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(3)); 643 rate->dsmpd = ((pllcon >> RK3399_PLLCON3_DSMPD_SHIFT) 644 & RK3399_PLLCON3_DSMPD_MASK); 645 } 646 647 static unsigned long rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw, 648 unsigned long prate) 649 { 650 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 651 struct rockchip_pll_rate_table cur; 652 u64 rate64 = prate; 653 654 rockchip_rk3399_pll_get_params(pll, &cur); 655 656 rate64 *= cur.fbdiv; 657 do_div(rate64, cur.refdiv); 658 659 if (cur.dsmpd == 0) { 660 /* fractional mode */ 661 u64 frac_rate64 = prate * cur.frac; 662 663 do_div(frac_rate64, cur.refdiv); 664 rate64 += frac_rate64 >> 24; 665 } 666 667 do_div(rate64, cur.postdiv1); 668 do_div(rate64, cur.postdiv2); 669 670 return (unsigned long)rate64; 671 } 672 673 static int rockchip_rk3399_pll_set_params(struct rockchip_clk_pll *pll, 674 const struct rockchip_pll_rate_table *rate) 675 { 676 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; 677 struct clk_mux *pll_mux = &pll->pll_mux; 678 struct rockchip_pll_rate_table cur; 679 u32 pllcon; 680 int rate_change_remuxed = 0; 681 int cur_parent; 682 int ret; 683 684 pr_debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 685 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, 686 rate->postdiv2, rate->dsmpd, rate->frac); 687 688 rockchip_rk3399_pll_get_params(pll, &cur); 689 cur.rate = 0; 690 691 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); 692 if (cur_parent == PLL_MODE_NORM) { 693 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); 694 rate_change_remuxed = 1; 695 } 696 697 /* update pll values */ 698 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK, 699 RK3399_PLLCON0_FBDIV_SHIFT), 700 pll->reg_base + RK3399_PLLCON(0)); 701 702 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3399_PLLCON1_REFDIV_MASK, 703 RK3399_PLLCON1_REFDIV_SHIFT) | 704 HIWORD_UPDATE(rate->postdiv1, RK3399_PLLCON1_POSTDIV1_MASK, 705 RK3399_PLLCON1_POSTDIV1_SHIFT) | 706 HIWORD_UPDATE(rate->postdiv2, RK3399_PLLCON1_POSTDIV2_MASK, 707 RK3399_PLLCON1_POSTDIV2_SHIFT), 708 pll->reg_base + RK3399_PLLCON(1)); 709 710 /* xPLL CON2 is not HIWORD_MASK */ 711 pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2)); 712 pllcon &= ~(RK3399_PLLCON2_FRAC_MASK << RK3399_PLLCON2_FRAC_SHIFT); 713 pllcon |= rate->frac << RK3399_PLLCON2_FRAC_SHIFT; 714 writel_relaxed(pllcon, pll->reg_base + RK3399_PLLCON(2)); 715 716 writel_relaxed(HIWORD_UPDATE(rate->dsmpd, RK3399_PLLCON3_DSMPD_MASK, 717 RK3399_PLLCON3_DSMPD_SHIFT), 718 pll->reg_base + RK3399_PLLCON(3)); 719 720 /* wait for the pll to lock */ 721 ret = rockchip_rk3399_pll_wait_lock(pll); 722 if (ret) { 723 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", 724 __func__); 725 rockchip_rk3399_pll_set_params(pll, &cur); 726 } 727 728 if (rate_change_remuxed) 729 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); 730 731 return ret; 732 } 733 734 static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate, 735 unsigned long prate) 736 { 737 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 738 const struct rockchip_pll_rate_table *rate; 739 740 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", 741 __func__, __clk_get_name(hw->clk), drate, prate); 742 743 /* Get required rate settings from table */ 744 rate = rockchip_get_pll_settings(pll, drate); 745 if (!rate) { 746 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 747 drate, __clk_get_name(hw->clk)); 748 return -EINVAL; 749 } 750 751 return rockchip_rk3399_pll_set_params(pll, rate); 752 } 753 754 static int rockchip_rk3399_pll_enable(struct clk_hw *hw) 755 { 756 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 757 758 writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0), 759 pll->reg_base + RK3399_PLLCON(3)); 760 rockchip_rk3399_pll_wait_lock(pll); 761 762 return 0; 763 } 764 765 static void rockchip_rk3399_pll_disable(struct clk_hw *hw) 766 { 767 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 768 769 writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN, 770 RK3399_PLLCON3_PWRDOWN, 0), 771 pll->reg_base + RK3399_PLLCON(3)); 772 } 773 774 static int rockchip_rk3399_pll_is_enabled(struct clk_hw *hw) 775 { 776 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 777 u32 pllcon = readl(pll->reg_base + RK3399_PLLCON(3)); 778 779 return !(pllcon & RK3399_PLLCON3_PWRDOWN); 780 } 781 782 static int rockchip_rk3399_pll_init(struct clk_hw *hw) 783 { 784 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 785 const struct rockchip_pll_rate_table *rate; 786 struct rockchip_pll_rate_table cur; 787 unsigned long drate; 788 789 if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE)) 790 return 0; 791 792 drate = clk_hw_get_rate(hw); 793 rate = rockchip_get_pll_settings(pll, drate); 794 795 /* when no rate setting for the current rate, rely on clk_set_rate */ 796 if (!rate) 797 return 0; 798 799 rockchip_rk3399_pll_get_params(pll, &cur); 800 801 pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), 802 drate); 803 pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 804 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, 805 cur.dsmpd, cur.frac); 806 pr_debug("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n", 807 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, 808 rate->dsmpd, rate->frac); 809 810 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || 811 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || 812 rate->dsmpd != cur.dsmpd || 813 (!cur.dsmpd && (rate->frac != cur.frac))) { 814 struct clk *parent = clk_get_parent(hw->clk); 815 816 if (!parent) { 817 pr_warn("%s: parent of %s not available\n", 818 __func__, __clk_get_name(hw->clk)); 819 return 0; 820 } 821 822 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", 823 __func__, __clk_get_name(hw->clk)); 824 rockchip_rk3399_pll_set_params(pll, rate); 825 } 826 827 return 0; 828 } 829 830 static const struct clk_ops rockchip_rk3399_pll_clk_norate_ops = { 831 .recalc_rate = rockchip_rk3399_pll_recalc_rate, 832 .enable = rockchip_rk3399_pll_enable, 833 .disable = rockchip_rk3399_pll_disable, 834 .is_enabled = rockchip_rk3399_pll_is_enabled, 835 }; 836 837 static const struct clk_ops rockchip_rk3399_pll_clk_ops = { 838 .recalc_rate = rockchip_rk3399_pll_recalc_rate, 839 .round_rate = rockchip_pll_round_rate, 840 .set_rate = rockchip_rk3399_pll_set_rate, 841 .enable = rockchip_rk3399_pll_enable, 842 .disable = rockchip_rk3399_pll_disable, 843 .is_enabled = rockchip_rk3399_pll_is_enabled, 844 .init = rockchip_rk3399_pll_init, 845 }; 846 847 /* 848 * PLL used in RK3588 849 */ 850 851 #define RK3588_PLLCON(i) (i * 0x4) 852 #define RK3588_PLLCON0_M_MASK 0x3ff 853 #define RK3588_PLLCON0_M_SHIFT 0 854 #define RK3588_PLLCON1_P_MASK 0x3f 855 #define RK3588_PLLCON1_P_SHIFT 0 856 #define RK3588_PLLCON1_S_MASK 0x7 857 #define RK3588_PLLCON1_S_SHIFT 6 858 #define RK3588_PLLCON2_K_MASK 0xffff 859 #define RK3588_PLLCON2_K_SHIFT 0 860 #define RK3588_PLLCON1_PWRDOWN BIT(13) 861 #define RK3588_PLLCON6_LOCK_STATUS BIT(15) 862 863 static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll) 864 { 865 u32 pllcon; 866 int ret; 867 868 /* 869 * Lock time typical 250, max 500 input clock cycles @24MHz 870 * So define a very safe maximum of 1000us, meaning 24000 cycles. 871 */ 872 ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6), 873 pllcon, 874 pllcon & RK3588_PLLCON6_LOCK_STATUS, 875 0, 1000); 876 if (ret) 877 pr_err("%s: timeout waiting for pll to lock\n", __func__); 878 879 return ret; 880 } 881 882 static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll, 883 struct rockchip_pll_rate_table *rate) 884 { 885 u32 pllcon; 886 887 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0)); 888 rate->m = ((pllcon >> RK3588_PLLCON0_M_SHIFT) & RK3588_PLLCON0_M_MASK); 889 890 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1)); 891 rate->p = ((pllcon >> RK3588_PLLCON1_P_SHIFT) & RK3588_PLLCON1_P_MASK); 892 rate->s = ((pllcon >> RK3588_PLLCON1_S_SHIFT) & RK3588_PLLCON1_S_MASK); 893 894 pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2)); 895 rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK); 896 } 897 898 static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) 899 { 900 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 901 struct rockchip_pll_rate_table cur; 902 u64 rate64 = prate, postdiv; 903 904 rockchip_rk3588_pll_get_params(pll, &cur); 905 906 rate64 *= cur.m; 907 do_div(rate64, cur.p); 908 909 if (cur.k) { 910 /* fractional mode */ 911 u64 frac_rate64 = prate * cur.k; 912 913 postdiv = cur.p * 65535; 914 do_div(frac_rate64, postdiv); 915 rate64 += frac_rate64; 916 } 917 rate64 = rate64 >> cur.s; 918 919 if (pll->type == pll_rk3588_ddr) 920 return (unsigned long)rate64 * 2; 921 else 922 return (unsigned long)rate64; 923 } 924 925 static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, 926 const struct rockchip_pll_rate_table *rate) 927 { 928 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; 929 struct clk_mux *pll_mux = &pll->pll_mux; 930 struct rockchip_pll_rate_table cur; 931 int rate_change_remuxed = 0; 932 int cur_parent; 933 int ret; 934 935 pr_debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n", 936 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k); 937 938 rockchip_rk3588_pll_get_params(pll, &cur); 939 cur.rate = 0; 940 941 if (pll->type == pll_rk3588) { 942 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); 943 if (cur_parent == PLL_MODE_NORM) { 944 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); 945 rate_change_remuxed = 1; 946 } 947 } 948 949 /* set pll power down */ 950 writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, 951 RK3588_PLLCON1_PWRDOWN, 0), 952 pll->reg_base + RK3399_PLLCON(1)); 953 954 /* update pll values */ 955 writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, RK3588_PLLCON0_M_SHIFT), 956 pll->reg_base + RK3399_PLLCON(0)); 957 958 writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, RK3588_PLLCON1_P_SHIFT) | 959 HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, RK3588_PLLCON1_S_SHIFT), 960 pll->reg_base + RK3399_PLLCON(1)); 961 962 writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT), 963 pll->reg_base + RK3399_PLLCON(2)); 964 965 /* set pll power up */ 966 writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0), 967 pll->reg_base + RK3588_PLLCON(1)); 968 969 /* wait for the pll to lock */ 970 ret = rockchip_rk3588_pll_wait_lock(pll); 971 if (ret) { 972 pr_warn("%s: pll update unsuccessful, trying to restore old params\n", 973 __func__); 974 rockchip_rk3588_pll_set_params(pll, &cur); 975 } 976 977 if ((pll->type == pll_rk3588) && rate_change_remuxed) 978 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); 979 980 return ret; 981 } 982 983 static int rockchip_rk3588_pll_set_rate(struct clk_hw *hw, unsigned long drate, 984 unsigned long prate) 985 { 986 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 987 const struct rockchip_pll_rate_table *rate; 988 989 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", 990 __func__, __clk_get_name(hw->clk), drate, prate); 991 992 /* Get required rate settings from table */ 993 rate = rockchip_get_pll_settings(pll, drate); 994 if (!rate) { 995 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 996 drate, __clk_get_name(hw->clk)); 997 return -EINVAL; 998 } 999 1000 return rockchip_rk3588_pll_set_params(pll, rate); 1001 } 1002 1003 static int rockchip_rk3588_pll_enable(struct clk_hw *hw) 1004 { 1005 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 1006 1007 writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0), 1008 pll->reg_base + RK3588_PLLCON(1)); 1009 rockchip_rk3588_pll_wait_lock(pll); 1010 1011 return 0; 1012 } 1013 1014 static void rockchip_rk3588_pll_disable(struct clk_hw *hw) 1015 { 1016 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 1017 1018 writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, RK3588_PLLCON1_PWRDOWN, 0), 1019 pll->reg_base + RK3588_PLLCON(1)); 1020 } 1021 1022 static int rockchip_rk3588_pll_is_enabled(struct clk_hw *hw) 1023 { 1024 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); 1025 u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1)); 1026 1027 return !(pllcon & RK3588_PLLCON1_PWRDOWN); 1028 } 1029 1030 static const struct clk_ops rockchip_rk3588_pll_clk_norate_ops = { 1031 .recalc_rate = rockchip_rk3588_pll_recalc_rate, 1032 .enable = rockchip_rk3588_pll_enable, 1033 .disable = rockchip_rk3588_pll_disable, 1034 .is_enabled = rockchip_rk3588_pll_is_enabled, 1035 }; 1036 1037 static const struct clk_ops rockchip_rk3588_pll_clk_ops = { 1038 .recalc_rate = rockchip_rk3588_pll_recalc_rate, 1039 .round_rate = rockchip_pll_round_rate, 1040 .set_rate = rockchip_rk3588_pll_set_rate, 1041 .enable = rockchip_rk3588_pll_enable, 1042 .disable = rockchip_rk3588_pll_disable, 1043 .is_enabled = rockchip_rk3588_pll_is_enabled, 1044 }; 1045 1046 /* 1047 * Common registering of pll clocks 1048 */ 1049 1050 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, 1051 enum rockchip_pll_type pll_type, 1052 const char *name, const char *const *parent_names, 1053 u8 num_parents, int con_offset, int grf_lock_offset, 1054 int lock_shift, int mode_offset, int mode_shift, 1055 struct rockchip_pll_rate_table *rate_table, 1056 unsigned long flags, u8 clk_pll_flags) 1057 { 1058 const char *pll_parents[3]; 1059 struct clk_init_data init; 1060 struct rockchip_clk_pll *pll; 1061 struct clk_mux *pll_mux; 1062 struct clk *pll_clk, *mux_clk; 1063 char pll_name[20]; 1064 1065 if ((pll_type != pll_rk3328 && num_parents != 2) || 1066 (pll_type == pll_rk3328 && num_parents != 1)) { 1067 pr_err("%s: needs two parent clocks\n", __func__); 1068 return ERR_PTR(-EINVAL); 1069 } 1070 1071 /* name the actual pll */ 1072 snprintf(pll_name, sizeof(pll_name), "pll_%s", name); 1073 1074 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1075 if (!pll) 1076 return ERR_PTR(-ENOMEM); 1077 1078 /* create the mux on top of the real pll */ 1079 pll->pll_mux_ops = &clk_mux_ops; 1080 pll_mux = &pll->pll_mux; 1081 pll_mux->reg = ctx->reg_base + mode_offset; 1082 pll_mux->shift = mode_shift; 1083 if (pll_type == pll_rk3328) 1084 pll_mux->mask = PLL_RK3328_MODE_MASK; 1085 else 1086 pll_mux->mask = PLL_MODE_MASK; 1087 pll_mux->flags = 0; 1088 pll_mux->lock = &ctx->lock; 1089 pll_mux->hw.init = &init; 1090 1091 if (pll_type == pll_rk3036 || 1092 pll_type == pll_rk3066 || 1093 pll_type == pll_rk3328 || 1094 pll_type == pll_rk3399 || 1095 pll_type == pll_rk3588) 1096 pll_mux->flags |= CLK_MUX_HIWORD_MASK; 1097 1098 /* the actual muxing is xin24m, pll-output, xin32k */ 1099 pll_parents[0] = parent_names[0]; 1100 pll_parents[1] = pll_name; 1101 pll_parents[2] = parent_names[1]; 1102 1103 init.name = name; 1104 init.flags = CLK_SET_RATE_PARENT; 1105 init.ops = pll->pll_mux_ops; 1106 init.parent_names = pll_parents; 1107 if (pll_type == pll_rk3328) 1108 init.num_parents = 2; 1109 else 1110 init.num_parents = ARRAY_SIZE(pll_parents); 1111 1112 mux_clk = clk_register(NULL, &pll_mux->hw); 1113 if (IS_ERR(mux_clk)) 1114 goto err_mux; 1115 1116 /* now create the actual pll */ 1117 init.name = pll_name; 1118 1119 /* keep all plls untouched for now */ 1120 init.flags = flags | CLK_IGNORE_UNUSED; 1121 1122 init.parent_names = &parent_names[0]; 1123 init.num_parents = 1; 1124 1125 if (rate_table) { 1126 int len; 1127 1128 /* find count of rates in rate_table */ 1129 for (len = 0; rate_table[len].rate != 0; ) 1130 len++; 1131 1132 pll->rate_count = len; 1133 pll->rate_table = kmemdup_array(rate_table, 1134 pll->rate_count, 1135 sizeof(*pll->rate_table), 1136 GFP_KERNEL); 1137 WARN(!pll->rate_table, 1138 "%s: could not allocate rate table for %s\n", 1139 __func__, name); 1140 } 1141 1142 switch (pll_type) { 1143 case pll_rk3036: 1144 case pll_rk3328: 1145 if (!pll->rate_table) 1146 init.ops = &rockchip_rk3036_pll_clk_norate_ops; 1147 else 1148 init.ops = &rockchip_rk3036_pll_clk_ops; 1149 break; 1150 case pll_rk3066: 1151 if (!pll->rate_table || IS_ERR(ctx->grf)) 1152 init.ops = &rockchip_rk3066_pll_clk_norate_ops; 1153 else 1154 init.ops = &rockchip_rk3066_pll_clk_ops; 1155 break; 1156 case pll_rk3399: 1157 if (!pll->rate_table) 1158 init.ops = &rockchip_rk3399_pll_clk_norate_ops; 1159 else 1160 init.ops = &rockchip_rk3399_pll_clk_ops; 1161 break; 1162 case pll_rk3588: 1163 case pll_rk3588_core: 1164 case pll_rk3588_ddr: 1165 if (!pll->rate_table) 1166 init.ops = &rockchip_rk3588_pll_clk_norate_ops; 1167 else 1168 init.ops = &rockchip_rk3588_pll_clk_ops; 1169 init.flags = flags; 1170 break; 1171 default: 1172 pr_warn("%s: Unknown pll type for pll clk %s\n", 1173 __func__, name); 1174 } 1175 1176 pll->hw.init = &init; 1177 pll->type = pll_type; 1178 pll->reg_base = ctx->reg_base + con_offset; 1179 pll->lock_offset = grf_lock_offset; 1180 pll->lock_shift = lock_shift; 1181 pll->flags = clk_pll_flags; 1182 pll->lock = &ctx->lock; 1183 pll->ctx = ctx; 1184 1185 pll_clk = clk_register(NULL, &pll->hw); 1186 if (IS_ERR(pll_clk)) { 1187 pr_err("%s: failed to register pll clock %s : %ld\n", 1188 __func__, name, PTR_ERR(pll_clk)); 1189 goto err_pll; 1190 } 1191 1192 return mux_clk; 1193 1194 err_pll: 1195 kfree(pll->rate_table); 1196 clk_unregister(mux_clk); 1197 mux_clk = pll_clk; 1198 err_mux: 1199 kfree(pll); 1200 return mux_clk; 1201 } 1202