1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,gpucc-sc7180.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap.h" 18 #include "common.h" 19 #include "gdsc.h" 20 21 #define CX_GMU_CBCR_SLEEP_MASK 0xF 22 #define CX_GMU_CBCR_SLEEP_SHIFT 4 23 #define CX_GMU_CBCR_WAKE_MASK 0xF 24 #define CX_GMU_CBCR_WAKE_SHIFT 8 25 26 enum { 27 P_BI_TCXO, 28 P_GPLL0_OUT_MAIN, 29 P_GPLL0_OUT_MAIN_DIV, 30 P_GPU_CC_PLL1_OUT_MAIN, 31 }; 32 33 static const struct pll_vco fabia_vco[] = { 34 { 249600000, 2000000000, 0 }, 35 }; 36 37 static struct clk_alpha_pll gpu_cc_pll1 = { 38 .offset = 0x100, 39 .vco_table = fabia_vco, 40 .num_vco = ARRAY_SIZE(fabia_vco), 41 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 42 .clkr = { 43 .hw.init = &(struct clk_init_data){ 44 .name = "gpu_cc_pll1", 45 .parent_data = &(const struct clk_parent_data){ 46 .fw_name = "bi_tcxo", 47 }, 48 .num_parents = 1, 49 .ops = &clk_alpha_pll_fabia_ops, 50 }, 51 }, 52 }; 53 54 static const struct parent_map gpu_cc_parent_map_0[] = { 55 { P_BI_TCXO, 0 }, 56 { P_GPU_CC_PLL1_OUT_MAIN, 3 }, 57 { P_GPLL0_OUT_MAIN, 5 }, 58 { P_GPLL0_OUT_MAIN_DIV, 6 }, 59 }; 60 61 static const struct clk_parent_data gpu_cc_parent_data_0[] = { 62 { .fw_name = "bi_tcxo" }, 63 { .hw = &gpu_cc_pll1.clkr.hw }, 64 { .fw_name = "gcc_gpu_gpll0_clk_src" }, 65 { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, 66 }; 67 68 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { 69 F(19200000, P_BI_TCXO, 1, 0, 0), 70 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), 71 { } 72 }; 73 74 static struct clk_rcg2 gpu_cc_gmu_clk_src = { 75 .cmd_rcgr = 0x1120, 76 .mnd_width = 0, 77 .hid_width = 5, 78 .parent_map = gpu_cc_parent_map_0, 79 .freq_tbl = ftbl_gpu_cc_gmu_clk_src, 80 .clkr.hw.init = &(struct clk_init_data){ 81 .name = "gpu_cc_gmu_clk_src", 82 .parent_data = gpu_cc_parent_data_0, 83 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), 84 .flags = CLK_SET_RATE_PARENT, 85 .ops = &clk_rcg2_shared_ops, 86 }, 87 }; 88 89 static struct clk_branch gpu_cc_crc_ahb_clk = { 90 .halt_reg = 0x107c, 91 .halt_check = BRANCH_HALT_DELAY, 92 .clkr = { 93 .enable_reg = 0x107c, 94 .enable_mask = BIT(0), 95 .hw.init = &(struct clk_init_data){ 96 .name = "gpu_cc_crc_ahb_clk", 97 .ops = &clk_branch2_ops, 98 }, 99 }, 100 }; 101 102 static struct clk_branch gpu_cc_cx_gmu_clk = { 103 .halt_reg = 0x1098, 104 .halt_check = BRANCH_HALT, 105 .clkr = { 106 .enable_reg = 0x1098, 107 .enable_mask = BIT(0), 108 .hw.init = &(struct clk_init_data){ 109 .name = "gpu_cc_cx_gmu_clk", 110 .parent_hws = (const struct clk_hw*[]) { 111 &gpu_cc_gmu_clk_src.clkr.hw, 112 }, 113 .num_parents = 1, 114 .flags = CLK_SET_RATE_PARENT, 115 .ops = &clk_branch2_ops, 116 }, 117 }, 118 }; 119 120 static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { 121 .halt_reg = 0x108c, 122 .halt_check = BRANCH_HALT_DELAY, 123 .clkr = { 124 .enable_reg = 0x108c, 125 .enable_mask = BIT(0), 126 .hw.init = &(struct clk_init_data){ 127 .name = "gpu_cc_cx_snoc_dvm_clk", 128 .ops = &clk_branch2_ops, 129 }, 130 }, 131 }; 132 133 static struct clk_branch gpu_cc_cxo_aon_clk = { 134 .halt_reg = 0x1004, 135 .halt_check = BRANCH_HALT_DELAY, 136 .clkr = { 137 .enable_reg = 0x1004, 138 .enable_mask = BIT(0), 139 .hw.init = &(struct clk_init_data){ 140 .name = "gpu_cc_cxo_aon_clk", 141 .ops = &clk_branch2_ops, 142 }, 143 }, 144 }; 145 146 static struct clk_branch gpu_cc_cxo_clk = { 147 .halt_reg = 0x109c, 148 .halt_check = BRANCH_HALT, 149 .clkr = { 150 .enable_reg = 0x109c, 151 .enable_mask = BIT(0), 152 .hw.init = &(struct clk_init_data){ 153 .name = "gpu_cc_cxo_clk", 154 .ops = &clk_branch2_ops, 155 }, 156 }, 157 }; 158 159 static struct gdsc cx_gdsc = { 160 .gdscr = 0x106c, 161 .gds_hw_ctrl = 0x1540, 162 .clk_dis_wait_val = 8, 163 .pd = { 164 .name = "cx_gdsc", 165 }, 166 .pwrsts = PWRSTS_OFF_ON, 167 .flags = VOTABLE, 168 }; 169 170 static struct gdsc gx_gdsc = { 171 .gdscr = 0x100c, 172 .clamp_io_ctrl = 0x1508, 173 .pd = { 174 .name = "gx_gdsc", 175 .power_on = gdsc_gx_do_nothing_enable, 176 }, 177 .pwrsts = PWRSTS_OFF_ON, 178 .flags = CLAMP_IO, 179 }; 180 181 static struct gdsc *gpu_cc_sc7180_gdscs[] = { 182 [CX_GDSC] = &cx_gdsc, 183 [GX_GDSC] = &gx_gdsc, 184 }; 185 186 static struct clk_regmap *gpu_cc_sc7180_clocks[] = { 187 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, 188 [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, 189 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, 190 [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, 191 [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, 192 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, 193 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, 194 }; 195 196 static const struct regmap_config gpu_cc_sc7180_regmap_config = { 197 .reg_bits = 32, 198 .reg_stride = 4, 199 .val_bits = 32, 200 .max_register = 0x8008, 201 .fast_io = true, 202 }; 203 204 static const struct qcom_cc_desc gpu_cc_sc7180_desc = { 205 .config = &gpu_cc_sc7180_regmap_config, 206 .clks = gpu_cc_sc7180_clocks, 207 .num_clks = ARRAY_SIZE(gpu_cc_sc7180_clocks), 208 .gdscs = gpu_cc_sc7180_gdscs, 209 .num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs), 210 }; 211 212 static const struct of_device_id gpu_cc_sc7180_match_table[] = { 213 { .compatible = "qcom,sc7180-gpucc" }, 214 { } 215 }; 216 MODULE_DEVICE_TABLE(of, gpu_cc_sc7180_match_table); 217 218 static int gpu_cc_sc7180_probe(struct platform_device *pdev) 219 { 220 struct regmap *regmap; 221 struct alpha_pll_config gpu_cc_pll_config = {}; 222 unsigned int value, mask; 223 224 regmap = qcom_cc_map(pdev, &gpu_cc_sc7180_desc); 225 if (IS_ERR(regmap)) 226 return PTR_ERR(regmap); 227 228 /* 360MHz Configuration */ 229 gpu_cc_pll_config.l = 0x12; 230 gpu_cc_pll_config.alpha = 0xc000; 231 gpu_cc_pll_config.config_ctl_val = 0x20485699; 232 gpu_cc_pll_config.config_ctl_hi_val = 0x00002067; 233 gpu_cc_pll_config.user_ctl_val = 0x00000001; 234 gpu_cc_pll_config.user_ctl_hi_val = 0x00004805; 235 gpu_cc_pll_config.test_ctl_hi_val = 0x40000000; 236 237 clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll_config); 238 239 /* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */ 240 mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT; 241 mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT; 242 value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT; 243 regmap_update_bits(regmap, 0x1098, mask, value); 244 245 return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sc7180_desc, regmap); 246 } 247 248 static struct platform_driver gpu_cc_sc7180_driver = { 249 .probe = gpu_cc_sc7180_probe, 250 .driver = { 251 .name = "sc7180-gpucc", 252 .of_match_table = gpu_cc_sc7180_match_table, 253 }, 254 }; 255 256 module_platform_driver(gpu_cc_sc7180_driver); 257 258 MODULE_DESCRIPTION("QTI GPU_CC SC7180 Driver"); 259 MODULE_LICENSE("GPL v2"); 260