1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/bitops.h> 8 #include <linux/err.h> 9 #include <linux/platform_device.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/clk-provider.h> 13 #include <linux/regmap.h> 14 #include <linux/reset-controller.h> 15 16 #include <dt-bindings/clock/qcom,gcc-msm8974.h> 17 #include <dt-bindings/reset/qcom,gcc-msm8974.h> 18 19 #include "common.h" 20 #include "clk-regmap.h" 21 #include "clk-pll.h" 22 #include "clk-rcg.h" 23 #include "clk-branch.h" 24 #include "reset.h" 25 #include "gdsc.h" 26 27 enum { 28 P_XO, 29 P_GPLL0, 30 P_GPLL1, 31 P_GPLL4, 32 }; 33 34 static struct clk_pll gpll0 = { 35 .l_reg = 0x0004, 36 .m_reg = 0x0008, 37 .n_reg = 0x000c, 38 .config_reg = 0x0014, 39 .mode_reg = 0x0000, 40 .status_reg = 0x001c, 41 .status_bit = 17, 42 .clkr.hw.init = &(struct clk_init_data){ 43 .name = "gpll0", 44 .parent_data = &(const struct clk_parent_data){ 45 .fw_name = "xo", .name = "xo_board", 46 }, 47 .num_parents = 1, 48 .ops = &clk_pll_ops, 49 }, 50 }; 51 52 static struct clk_regmap gpll0_vote = { 53 .enable_reg = 0x1480, 54 .enable_mask = BIT(0), 55 .hw.init = &(struct clk_init_data){ 56 .name = "gpll0_vote", 57 .parent_hws = (const struct clk_hw*[]){ 58 &gpll0.clkr.hw, 59 }, 60 .num_parents = 1, 61 .ops = &clk_pll_vote_ops, 62 }, 63 }; 64 65 static struct clk_pll gpll4 = { 66 .l_reg = 0x1dc4, 67 .m_reg = 0x1dc8, 68 .n_reg = 0x1dcc, 69 .config_reg = 0x1dd4, 70 .mode_reg = 0x1dc0, 71 .status_reg = 0x1ddc, 72 .status_bit = 17, 73 .clkr.hw.init = &(struct clk_init_data){ 74 .name = "gpll4", 75 .parent_data = &(const struct clk_parent_data){ 76 .fw_name = "xo", .name = "xo_board", 77 }, 78 .num_parents = 1, 79 .ops = &clk_pll_ops, 80 }, 81 }; 82 83 static struct clk_regmap gpll4_vote = { 84 .enable_reg = 0x1480, 85 .enable_mask = BIT(4), 86 .hw.init = &(struct clk_init_data){ 87 .name = "gpll4_vote", 88 .parent_hws = (const struct clk_hw*[]){ 89 &gpll4.clkr.hw, 90 }, 91 .num_parents = 1, 92 .ops = &clk_pll_vote_ops, 93 }, 94 }; 95 96 static const struct parent_map gcc_xo_gpll0_map[] = { 97 { P_XO, 0 }, 98 { P_GPLL0, 1 } 99 }; 100 101 static const struct clk_parent_data gcc_xo_gpll0[] = { 102 { .fw_name = "xo", .name = "xo_board" }, 103 { .hw = &gpll0_vote.hw }, 104 }; 105 106 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { 107 { P_XO, 0 }, 108 { P_GPLL0, 1 }, 109 { P_GPLL4, 5 } 110 }; 111 112 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { 113 { .fw_name = "xo", .name = "xo_board" }, 114 { .hw = &gpll0_vote.hw }, 115 { .hw = &gpll4_vote.hw }, 116 }; 117 118 static struct clk_rcg2 config_noc_clk_src = { 119 .cmd_rcgr = 0x0150, 120 .hid_width = 5, 121 .parent_map = gcc_xo_gpll0_map, 122 .clkr.hw.init = &(struct clk_init_data){ 123 .name = "config_noc_clk_src", 124 .parent_data = gcc_xo_gpll0, 125 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 126 .ops = &clk_rcg2_ops, 127 }, 128 }; 129 130 static struct clk_rcg2 periph_noc_clk_src = { 131 .cmd_rcgr = 0x0190, 132 .hid_width = 5, 133 .parent_map = gcc_xo_gpll0_map, 134 .clkr.hw.init = &(struct clk_init_data){ 135 .name = "periph_noc_clk_src", 136 .parent_data = gcc_xo_gpll0, 137 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 138 .ops = &clk_rcg2_ops, 139 }, 140 }; 141 142 static struct clk_rcg2 system_noc_clk_src = { 143 .cmd_rcgr = 0x0120, 144 .hid_width = 5, 145 .parent_map = gcc_xo_gpll0_map, 146 .clkr.hw.init = &(struct clk_init_data){ 147 .name = "system_noc_clk_src", 148 .parent_data = gcc_xo_gpll0, 149 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 150 .ops = &clk_rcg2_ops, 151 }, 152 }; 153 154 static struct clk_pll gpll1 = { 155 .l_reg = 0x0044, 156 .m_reg = 0x0048, 157 .n_reg = 0x004c, 158 .config_reg = 0x0054, 159 .mode_reg = 0x0040, 160 .status_reg = 0x005c, 161 .status_bit = 17, 162 .clkr.hw.init = &(struct clk_init_data){ 163 .name = "gpll1", 164 .parent_data = &(const struct clk_parent_data){ 165 .fw_name = "xo", .name = "xo_board", 166 }, 167 .num_parents = 1, 168 .ops = &clk_pll_ops, 169 }, 170 }; 171 172 static struct clk_regmap gpll1_vote = { 173 .enable_reg = 0x1480, 174 .enable_mask = BIT(1), 175 .hw.init = &(struct clk_init_data){ 176 .name = "gpll1_vote", 177 .parent_hws = (const struct clk_hw*[]){ 178 &gpll1.clkr.hw, 179 }, 180 .num_parents = 1, 181 .ops = &clk_pll_vote_ops, 182 }, 183 }; 184 185 static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = { 186 F(125000000, P_GPLL0, 1, 5, 24), 187 { } 188 }; 189 190 static struct clk_rcg2 usb30_master_clk_src = { 191 .cmd_rcgr = 0x03d4, 192 .mnd_width = 8, 193 .hid_width = 5, 194 .parent_map = gcc_xo_gpll0_map, 195 .freq_tbl = ftbl_gcc_usb30_master_clk, 196 .clkr.hw.init = &(struct clk_init_data){ 197 .name = "usb30_master_clk_src", 198 .parent_data = gcc_xo_gpll0, 199 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 200 .ops = &clk_rcg2_ops, 201 }, 202 }; 203 204 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = { 205 F(19200000, P_XO, 1, 0, 0), 206 F(37500000, P_GPLL0, 16, 0, 0), 207 F(50000000, P_GPLL0, 12, 0, 0), 208 { } 209 }; 210 211 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 212 .cmd_rcgr = 0x0660, 213 .hid_width = 5, 214 .parent_map = gcc_xo_gpll0_map, 215 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 216 .clkr.hw.init = &(struct clk_init_data){ 217 .name = "blsp1_qup1_i2c_apps_clk_src", 218 .parent_data = gcc_xo_gpll0, 219 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 220 .ops = &clk_rcg2_ops, 221 }, 222 }; 223 224 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = { 225 F(960000, P_XO, 10, 1, 2), 226 F(4800000, P_XO, 4, 0, 0), 227 F(9600000, P_XO, 2, 0, 0), 228 F(15000000, P_GPLL0, 10, 1, 4), 229 F(19200000, P_XO, 1, 0, 0), 230 F(25000000, P_GPLL0, 12, 1, 2), 231 F(50000000, P_GPLL0, 12, 0, 0), 232 { } 233 }; 234 235 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 236 .cmd_rcgr = 0x064c, 237 .mnd_width = 8, 238 .hid_width = 5, 239 .parent_map = gcc_xo_gpll0_map, 240 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 241 .clkr.hw.init = &(struct clk_init_data){ 242 .name = "blsp1_qup1_spi_apps_clk_src", 243 .parent_data = gcc_xo_gpll0, 244 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 245 .ops = &clk_rcg2_ops, 246 }, 247 }; 248 249 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 250 .cmd_rcgr = 0x06e0, 251 .hid_width = 5, 252 .parent_map = gcc_xo_gpll0_map, 253 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 254 .clkr.hw.init = &(struct clk_init_data){ 255 .name = "blsp1_qup2_i2c_apps_clk_src", 256 .parent_data = gcc_xo_gpll0, 257 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 258 .ops = &clk_rcg2_ops, 259 }, 260 }; 261 262 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 263 .cmd_rcgr = 0x06cc, 264 .mnd_width = 8, 265 .hid_width = 5, 266 .parent_map = gcc_xo_gpll0_map, 267 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 268 .clkr.hw.init = &(struct clk_init_data){ 269 .name = "blsp1_qup2_spi_apps_clk_src", 270 .parent_data = gcc_xo_gpll0, 271 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 272 .ops = &clk_rcg2_ops, 273 }, 274 }; 275 276 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 277 .cmd_rcgr = 0x0760, 278 .hid_width = 5, 279 .parent_map = gcc_xo_gpll0_map, 280 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 281 .clkr.hw.init = &(struct clk_init_data){ 282 .name = "blsp1_qup3_i2c_apps_clk_src", 283 .parent_data = gcc_xo_gpll0, 284 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 285 .ops = &clk_rcg2_ops, 286 }, 287 }; 288 289 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 290 .cmd_rcgr = 0x074c, 291 .mnd_width = 8, 292 .hid_width = 5, 293 .parent_map = gcc_xo_gpll0_map, 294 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 295 .clkr.hw.init = &(struct clk_init_data){ 296 .name = "blsp1_qup3_spi_apps_clk_src", 297 .parent_data = gcc_xo_gpll0, 298 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 299 .ops = &clk_rcg2_ops, 300 }, 301 }; 302 303 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 304 .cmd_rcgr = 0x07e0, 305 .hid_width = 5, 306 .parent_map = gcc_xo_gpll0_map, 307 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 308 .clkr.hw.init = &(struct clk_init_data){ 309 .name = "blsp1_qup4_i2c_apps_clk_src", 310 .parent_data = gcc_xo_gpll0, 311 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 312 .ops = &clk_rcg2_ops, 313 }, 314 }; 315 316 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 317 .cmd_rcgr = 0x07cc, 318 .mnd_width = 8, 319 .hid_width = 5, 320 .parent_map = gcc_xo_gpll0_map, 321 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 322 .clkr.hw.init = &(struct clk_init_data){ 323 .name = "blsp1_qup4_spi_apps_clk_src", 324 .parent_data = gcc_xo_gpll0, 325 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 326 .ops = &clk_rcg2_ops, 327 }, 328 }; 329 330 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 331 .cmd_rcgr = 0x0860, 332 .hid_width = 5, 333 .parent_map = gcc_xo_gpll0_map, 334 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 335 .clkr.hw.init = &(struct clk_init_data){ 336 .name = "blsp1_qup5_i2c_apps_clk_src", 337 .parent_data = gcc_xo_gpll0, 338 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 339 .ops = &clk_rcg2_ops, 340 }, 341 }; 342 343 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 344 .cmd_rcgr = 0x084c, 345 .mnd_width = 8, 346 .hid_width = 5, 347 .parent_map = gcc_xo_gpll0_map, 348 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 349 .clkr.hw.init = &(struct clk_init_data){ 350 .name = "blsp1_qup5_spi_apps_clk_src", 351 .parent_data = gcc_xo_gpll0, 352 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 353 .ops = &clk_rcg2_ops, 354 }, 355 }; 356 357 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 358 .cmd_rcgr = 0x08e0, 359 .hid_width = 5, 360 .parent_map = gcc_xo_gpll0_map, 361 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 362 .clkr.hw.init = &(struct clk_init_data){ 363 .name = "blsp1_qup6_i2c_apps_clk_src", 364 .parent_data = gcc_xo_gpll0, 365 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 366 .ops = &clk_rcg2_ops, 367 }, 368 }; 369 370 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 371 .cmd_rcgr = 0x08cc, 372 .mnd_width = 8, 373 .hid_width = 5, 374 .parent_map = gcc_xo_gpll0_map, 375 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 376 .clkr.hw.init = &(struct clk_init_data){ 377 .name = "blsp1_qup6_spi_apps_clk_src", 378 .parent_data = gcc_xo_gpll0, 379 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 380 .ops = &clk_rcg2_ops, 381 }, 382 }; 383 384 static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = { 385 F(3686400, P_GPLL0, 1, 96, 15625), 386 F(7372800, P_GPLL0, 1, 192, 15625), 387 F(14745600, P_GPLL0, 1, 384, 15625), 388 F(16000000, P_GPLL0, 5, 2, 15), 389 F(19200000, P_XO, 1, 0, 0), 390 F(24000000, P_GPLL0, 5, 1, 5), 391 F(32000000, P_GPLL0, 1, 4, 75), 392 F(40000000, P_GPLL0, 15, 0, 0), 393 F(46400000, P_GPLL0, 1, 29, 375), 394 F(48000000, P_GPLL0, 12.5, 0, 0), 395 F(51200000, P_GPLL0, 1, 32, 375), 396 F(56000000, P_GPLL0, 1, 7, 75), 397 F(58982400, P_GPLL0, 1, 1536, 15625), 398 F(60000000, P_GPLL0, 10, 0, 0), 399 F(63160000, P_GPLL0, 9.5, 0, 0), 400 { } 401 }; 402 403 static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 404 .cmd_rcgr = 0x068c, 405 .mnd_width = 16, 406 .hid_width = 5, 407 .parent_map = gcc_xo_gpll0_map, 408 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 409 .clkr.hw.init = &(struct clk_init_data){ 410 .name = "blsp1_uart1_apps_clk_src", 411 .parent_data = gcc_xo_gpll0, 412 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 413 .ops = &clk_rcg2_ops, 414 }, 415 }; 416 417 static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 418 .cmd_rcgr = 0x070c, 419 .mnd_width = 16, 420 .hid_width = 5, 421 .parent_map = gcc_xo_gpll0_map, 422 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 423 .clkr.hw.init = &(struct clk_init_data){ 424 .name = "blsp1_uart2_apps_clk_src", 425 .parent_data = gcc_xo_gpll0, 426 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 427 .ops = &clk_rcg2_ops, 428 }, 429 }; 430 431 static struct clk_rcg2 blsp1_uart3_apps_clk_src = { 432 .cmd_rcgr = 0x078c, 433 .mnd_width = 16, 434 .hid_width = 5, 435 .parent_map = gcc_xo_gpll0_map, 436 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 437 .clkr.hw.init = &(struct clk_init_data){ 438 .name = "blsp1_uart3_apps_clk_src", 439 .parent_data = gcc_xo_gpll0, 440 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 441 .ops = &clk_rcg2_ops, 442 }, 443 }; 444 445 static struct clk_rcg2 blsp1_uart4_apps_clk_src = { 446 .cmd_rcgr = 0x080c, 447 .mnd_width = 16, 448 .hid_width = 5, 449 .parent_map = gcc_xo_gpll0_map, 450 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 451 .clkr.hw.init = &(struct clk_init_data){ 452 .name = "blsp1_uart4_apps_clk_src", 453 .parent_data = gcc_xo_gpll0, 454 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 455 .ops = &clk_rcg2_ops, 456 }, 457 }; 458 459 static struct clk_rcg2 blsp1_uart5_apps_clk_src = { 460 .cmd_rcgr = 0x088c, 461 .mnd_width = 16, 462 .hid_width = 5, 463 .parent_map = gcc_xo_gpll0_map, 464 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 465 .clkr.hw.init = &(struct clk_init_data){ 466 .name = "blsp1_uart5_apps_clk_src", 467 .parent_data = gcc_xo_gpll0, 468 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 469 .ops = &clk_rcg2_ops, 470 }, 471 }; 472 473 static struct clk_rcg2 blsp1_uart6_apps_clk_src = { 474 .cmd_rcgr = 0x090c, 475 .mnd_width = 16, 476 .hid_width = 5, 477 .parent_map = gcc_xo_gpll0_map, 478 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 479 .clkr.hw.init = &(struct clk_init_data){ 480 .name = "blsp1_uart6_apps_clk_src", 481 .parent_data = gcc_xo_gpll0, 482 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 483 .ops = &clk_rcg2_ops, 484 }, 485 }; 486 487 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { 488 .cmd_rcgr = 0x09a0, 489 .hid_width = 5, 490 .parent_map = gcc_xo_gpll0_map, 491 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 492 .clkr.hw.init = &(struct clk_init_data){ 493 .name = "blsp2_qup1_i2c_apps_clk_src", 494 .parent_data = gcc_xo_gpll0, 495 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 496 .ops = &clk_rcg2_ops, 497 }, 498 }; 499 500 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { 501 .cmd_rcgr = 0x098c, 502 .mnd_width = 8, 503 .hid_width = 5, 504 .parent_map = gcc_xo_gpll0_map, 505 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 506 .clkr.hw.init = &(struct clk_init_data){ 507 .name = "blsp2_qup1_spi_apps_clk_src", 508 .parent_data = gcc_xo_gpll0, 509 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 510 .ops = &clk_rcg2_ops, 511 }, 512 }; 513 514 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { 515 .cmd_rcgr = 0x0a20, 516 .hid_width = 5, 517 .parent_map = gcc_xo_gpll0_map, 518 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 519 .clkr.hw.init = &(struct clk_init_data){ 520 .name = "blsp2_qup2_i2c_apps_clk_src", 521 .parent_data = gcc_xo_gpll0, 522 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 523 .ops = &clk_rcg2_ops, 524 }, 525 }; 526 527 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { 528 .cmd_rcgr = 0x0a0c, 529 .mnd_width = 8, 530 .hid_width = 5, 531 .parent_map = gcc_xo_gpll0_map, 532 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 533 .clkr.hw.init = &(struct clk_init_data){ 534 .name = "blsp2_qup2_spi_apps_clk_src", 535 .parent_data = gcc_xo_gpll0, 536 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 537 .ops = &clk_rcg2_ops, 538 }, 539 }; 540 541 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { 542 .cmd_rcgr = 0x0aa0, 543 .hid_width = 5, 544 .parent_map = gcc_xo_gpll0_map, 545 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 546 .clkr.hw.init = &(struct clk_init_data){ 547 .name = "blsp2_qup3_i2c_apps_clk_src", 548 .parent_data = gcc_xo_gpll0, 549 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 550 .ops = &clk_rcg2_ops, 551 }, 552 }; 553 554 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { 555 .cmd_rcgr = 0x0a8c, 556 .mnd_width = 8, 557 .hid_width = 5, 558 .parent_map = gcc_xo_gpll0_map, 559 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 560 .clkr.hw.init = &(struct clk_init_data){ 561 .name = "blsp2_qup3_spi_apps_clk_src", 562 .parent_data = gcc_xo_gpll0, 563 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 564 .ops = &clk_rcg2_ops, 565 }, 566 }; 567 568 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { 569 .cmd_rcgr = 0x0b20, 570 .hid_width = 5, 571 .parent_map = gcc_xo_gpll0_map, 572 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 573 .clkr.hw.init = &(struct clk_init_data){ 574 .name = "blsp2_qup4_i2c_apps_clk_src", 575 .parent_data = gcc_xo_gpll0, 576 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 577 .ops = &clk_rcg2_ops, 578 }, 579 }; 580 581 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { 582 .cmd_rcgr = 0x0b0c, 583 .mnd_width = 8, 584 .hid_width = 5, 585 .parent_map = gcc_xo_gpll0_map, 586 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 587 .clkr.hw.init = &(struct clk_init_data){ 588 .name = "blsp2_qup4_spi_apps_clk_src", 589 .parent_data = gcc_xo_gpll0, 590 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 591 .ops = &clk_rcg2_ops, 592 }, 593 }; 594 595 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { 596 .cmd_rcgr = 0x0ba0, 597 .hid_width = 5, 598 .parent_map = gcc_xo_gpll0_map, 599 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 600 .clkr.hw.init = &(struct clk_init_data){ 601 .name = "blsp2_qup5_i2c_apps_clk_src", 602 .parent_data = gcc_xo_gpll0, 603 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 604 .ops = &clk_rcg2_ops, 605 }, 606 }; 607 608 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { 609 .cmd_rcgr = 0x0b8c, 610 .mnd_width = 8, 611 .hid_width = 5, 612 .parent_map = gcc_xo_gpll0_map, 613 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 614 .clkr.hw.init = &(struct clk_init_data){ 615 .name = "blsp2_qup5_spi_apps_clk_src", 616 .parent_data = gcc_xo_gpll0, 617 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 618 .ops = &clk_rcg2_ops, 619 }, 620 }; 621 622 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { 623 .cmd_rcgr = 0x0c20, 624 .hid_width = 5, 625 .parent_map = gcc_xo_gpll0_map, 626 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, 627 .clkr.hw.init = &(struct clk_init_data){ 628 .name = "blsp2_qup6_i2c_apps_clk_src", 629 .parent_data = gcc_xo_gpll0, 630 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 631 .ops = &clk_rcg2_ops, 632 }, 633 }; 634 635 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { 636 .cmd_rcgr = 0x0c0c, 637 .mnd_width = 8, 638 .hid_width = 5, 639 .parent_map = gcc_xo_gpll0_map, 640 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, 641 .clkr.hw.init = &(struct clk_init_data){ 642 .name = "blsp2_qup6_spi_apps_clk_src", 643 .parent_data = gcc_xo_gpll0, 644 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 645 .ops = &clk_rcg2_ops, 646 }, 647 }; 648 649 static struct clk_rcg2 blsp2_uart1_apps_clk_src = { 650 .cmd_rcgr = 0x09cc, 651 .mnd_width = 16, 652 .hid_width = 5, 653 .parent_map = gcc_xo_gpll0_map, 654 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 655 .clkr.hw.init = &(struct clk_init_data){ 656 .name = "blsp2_uart1_apps_clk_src", 657 .parent_data = gcc_xo_gpll0, 658 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 659 .ops = &clk_rcg2_ops, 660 }, 661 }; 662 663 static struct clk_rcg2 blsp2_uart2_apps_clk_src = { 664 .cmd_rcgr = 0x0a4c, 665 .mnd_width = 16, 666 .hid_width = 5, 667 .parent_map = gcc_xo_gpll0_map, 668 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 669 .clkr.hw.init = &(struct clk_init_data){ 670 .name = "blsp2_uart2_apps_clk_src", 671 .parent_data = gcc_xo_gpll0, 672 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 673 .ops = &clk_rcg2_ops, 674 }, 675 }; 676 677 static struct clk_rcg2 blsp2_uart3_apps_clk_src = { 678 .cmd_rcgr = 0x0acc, 679 .mnd_width = 16, 680 .hid_width = 5, 681 .parent_map = gcc_xo_gpll0_map, 682 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 683 .clkr.hw.init = &(struct clk_init_data){ 684 .name = "blsp2_uart3_apps_clk_src", 685 .parent_data = gcc_xo_gpll0, 686 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 687 .ops = &clk_rcg2_ops, 688 }, 689 }; 690 691 static struct clk_rcg2 blsp2_uart4_apps_clk_src = { 692 .cmd_rcgr = 0x0b4c, 693 .mnd_width = 16, 694 .hid_width = 5, 695 .parent_map = gcc_xo_gpll0_map, 696 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 697 .clkr.hw.init = &(struct clk_init_data){ 698 .name = "blsp2_uart4_apps_clk_src", 699 .parent_data = gcc_xo_gpll0, 700 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 701 .ops = &clk_rcg2_ops, 702 }, 703 }; 704 705 static struct clk_rcg2 blsp2_uart5_apps_clk_src = { 706 .cmd_rcgr = 0x0bcc, 707 .mnd_width = 16, 708 .hid_width = 5, 709 .parent_map = gcc_xo_gpll0_map, 710 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 711 .clkr.hw.init = &(struct clk_init_data){ 712 .name = "blsp2_uart5_apps_clk_src", 713 .parent_data = gcc_xo_gpll0, 714 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 715 .ops = &clk_rcg2_ops, 716 }, 717 }; 718 719 static struct clk_rcg2 blsp2_uart6_apps_clk_src = { 720 .cmd_rcgr = 0x0c4c, 721 .mnd_width = 16, 722 .hid_width = 5, 723 .parent_map = gcc_xo_gpll0_map, 724 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, 725 .clkr.hw.init = &(struct clk_init_data){ 726 .name = "blsp2_uart6_apps_clk_src", 727 .parent_data = gcc_xo_gpll0, 728 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 729 .ops = &clk_rcg2_ops, 730 }, 731 }; 732 733 static const struct freq_tbl ftbl_gcc_ce1_clk_msm8226[] = { 734 F(50000000, P_GPLL0, 12, 0, 0), 735 F(100000000, P_GPLL0, 6, 0, 0), 736 { } 737 }; 738 739 static const struct freq_tbl ftbl_gcc_ce1_clk[] = { 740 F(50000000, P_GPLL0, 12, 0, 0), 741 F(75000000, P_GPLL0, 8, 0, 0), 742 F(100000000, P_GPLL0, 6, 0, 0), 743 F(150000000, P_GPLL0, 4, 0, 0), 744 { } 745 }; 746 747 static struct clk_rcg2 ce1_clk_src = { 748 .cmd_rcgr = 0x1050, 749 .hid_width = 5, 750 .parent_map = gcc_xo_gpll0_map, 751 .freq_tbl = ftbl_gcc_ce1_clk, 752 .clkr.hw.init = &(struct clk_init_data){ 753 .name = "ce1_clk_src", 754 .parent_data = gcc_xo_gpll0, 755 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 756 .ops = &clk_rcg2_ops, 757 }, 758 }; 759 760 static const struct freq_tbl ftbl_gcc_ce2_clk[] = { 761 F(50000000, P_GPLL0, 12, 0, 0), 762 F(75000000, P_GPLL0, 8, 0, 0), 763 F(100000000, P_GPLL0, 6, 0, 0), 764 F(150000000, P_GPLL0, 4, 0, 0), 765 { } 766 }; 767 768 static struct clk_rcg2 ce2_clk_src = { 769 .cmd_rcgr = 0x1090, 770 .hid_width = 5, 771 .parent_map = gcc_xo_gpll0_map, 772 .freq_tbl = ftbl_gcc_ce2_clk, 773 .clkr.hw.init = &(struct clk_init_data){ 774 .name = "ce2_clk_src", 775 .parent_data = gcc_xo_gpll0, 776 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 777 .ops = &clk_rcg2_ops, 778 }, 779 }; 780 781 static const struct freq_tbl ftbl_gcc_gp_clk_msm8226[] = { 782 F(19200000, P_XO, 1, 0, 0), 783 { } 784 }; 785 786 static const struct freq_tbl ftbl_gcc_gp_clk[] = { 787 F(4800000, P_XO, 4, 0, 0), 788 F(6000000, P_GPLL0, 10, 1, 10), 789 F(6750000, P_GPLL0, 1, 1, 89), 790 F(8000000, P_GPLL0, 15, 1, 5), 791 F(9600000, P_XO, 2, 0, 0), 792 F(16000000, P_GPLL0, 1, 2, 75), 793 F(19200000, P_XO, 1, 0, 0), 794 F(24000000, P_GPLL0, 5, 1, 5), 795 { } 796 }; 797 798 799 static struct clk_rcg2 gp1_clk_src = { 800 .cmd_rcgr = 0x1904, 801 .mnd_width = 8, 802 .hid_width = 5, 803 .parent_map = gcc_xo_gpll0_map, 804 .freq_tbl = ftbl_gcc_gp_clk, 805 .clkr.hw.init = &(struct clk_init_data){ 806 .name = "gp1_clk_src", 807 .parent_data = gcc_xo_gpll0, 808 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 809 .ops = &clk_rcg2_ops, 810 }, 811 }; 812 813 static struct clk_rcg2 gp2_clk_src = { 814 .cmd_rcgr = 0x1944, 815 .mnd_width = 8, 816 .hid_width = 5, 817 .parent_map = gcc_xo_gpll0_map, 818 .freq_tbl = ftbl_gcc_gp_clk, 819 .clkr.hw.init = &(struct clk_init_data){ 820 .name = "gp2_clk_src", 821 .parent_data = gcc_xo_gpll0, 822 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 823 .ops = &clk_rcg2_ops, 824 }, 825 }; 826 827 static struct clk_rcg2 gp3_clk_src = { 828 .cmd_rcgr = 0x1984, 829 .mnd_width = 8, 830 .hid_width = 5, 831 .parent_map = gcc_xo_gpll0_map, 832 .freq_tbl = ftbl_gcc_gp_clk, 833 .clkr.hw.init = &(struct clk_init_data){ 834 .name = "gp3_clk_src", 835 .parent_data = gcc_xo_gpll0, 836 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 837 .ops = &clk_rcg2_ops, 838 }, 839 }; 840 841 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { 842 F(60000000, P_GPLL0, 10, 0, 0), 843 { } 844 }; 845 846 static struct clk_rcg2 pdm2_clk_src = { 847 .cmd_rcgr = 0x0cd0, 848 .hid_width = 5, 849 .parent_map = gcc_xo_gpll0_map, 850 .freq_tbl = ftbl_gcc_pdm2_clk, 851 .clkr.hw.init = &(struct clk_init_data){ 852 .name = "pdm2_clk_src", 853 .parent_data = gcc_xo_gpll0, 854 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 855 .ops = &clk_rcg2_ops, 856 }, 857 }; 858 859 static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = { 860 F(144000, P_XO, 16, 3, 25), 861 F(400000, P_XO, 12, 1, 4), 862 F(20000000, P_GPLL0, 15, 1, 2), 863 F(25000000, P_GPLL0, 12, 1, 2), 864 F(50000000, P_GPLL0, 12, 0, 0), 865 F(100000000, P_GPLL0, 6, 0, 0), 866 F(200000000, P_GPLL0, 3, 0, 0), 867 { } 868 }; 869 870 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = { 871 F(144000, P_XO, 16, 3, 25), 872 F(400000, P_XO, 12, 1, 4), 873 F(20000000, P_GPLL0, 15, 1, 2), 874 F(25000000, P_GPLL0, 12, 1, 2), 875 F(50000000, P_GPLL0, 12, 0, 0), 876 F(100000000, P_GPLL0, 6, 0, 0), 877 F(192000000, P_GPLL4, 4, 0, 0), 878 F(200000000, P_GPLL0, 3, 0, 0), 879 F(384000000, P_GPLL4, 2, 0, 0), 880 { } 881 }; 882 883 static struct clk_init_data sdcc1_apps_clk_src_init = { 884 .name = "sdcc1_apps_clk_src", 885 .parent_data = gcc_xo_gpll0, 886 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 887 .ops = &clk_rcg2_floor_ops, 888 }; 889 890 static struct clk_rcg2 sdcc1_apps_clk_src = { 891 .cmd_rcgr = 0x04d0, 892 .mnd_width = 8, 893 .hid_width = 5, 894 .parent_map = gcc_xo_gpll0_map, 895 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 896 .clkr.hw.init = &sdcc1_apps_clk_src_init, 897 }; 898 899 static struct clk_rcg2 sdcc2_apps_clk_src = { 900 .cmd_rcgr = 0x0510, 901 .mnd_width = 8, 902 .hid_width = 5, 903 .parent_map = gcc_xo_gpll0_map, 904 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 905 .clkr.hw.init = &(struct clk_init_data){ 906 .name = "sdcc2_apps_clk_src", 907 .parent_data = gcc_xo_gpll0, 908 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 909 .ops = &clk_rcg2_floor_ops, 910 }, 911 }; 912 913 static struct clk_rcg2 sdcc3_apps_clk_src = { 914 .cmd_rcgr = 0x0550, 915 .mnd_width = 8, 916 .hid_width = 5, 917 .parent_map = gcc_xo_gpll0_map, 918 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 919 .clkr.hw.init = &(struct clk_init_data){ 920 .name = "sdcc3_apps_clk_src", 921 .parent_data = gcc_xo_gpll0, 922 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 923 .ops = &clk_rcg2_floor_ops, 924 }, 925 }; 926 927 static struct clk_rcg2 sdcc4_apps_clk_src = { 928 .cmd_rcgr = 0x0590, 929 .mnd_width = 8, 930 .hid_width = 5, 931 .parent_map = gcc_xo_gpll0_map, 932 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, 933 .clkr.hw.init = &(struct clk_init_data){ 934 .name = "sdcc4_apps_clk_src", 935 .parent_data = gcc_xo_gpll0, 936 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 937 .ops = &clk_rcg2_floor_ops, 938 }, 939 }; 940 941 static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = { 942 F(105000, P_XO, 2, 1, 91), 943 { } 944 }; 945 946 static struct clk_rcg2 tsif_ref_clk_src = { 947 .cmd_rcgr = 0x0d90, 948 .mnd_width = 8, 949 .hid_width = 5, 950 .parent_map = gcc_xo_gpll0_map, 951 .freq_tbl = ftbl_gcc_tsif_ref_clk, 952 .clkr.hw.init = &(struct clk_init_data){ 953 .name = "tsif_ref_clk_src", 954 .parent_data = gcc_xo_gpll0, 955 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 956 .ops = &clk_rcg2_ops, 957 }, 958 }; 959 960 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = { 961 F(60000000, P_GPLL0, 10, 0, 0), 962 { } 963 }; 964 965 static struct clk_rcg2 usb30_mock_utmi_clk_src = { 966 .cmd_rcgr = 0x03e8, 967 .hid_width = 5, 968 .parent_map = gcc_xo_gpll0_map, 969 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk, 970 .clkr.hw.init = &(struct clk_init_data){ 971 .name = "usb30_mock_utmi_clk_src", 972 .parent_data = gcc_xo_gpll0, 973 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 974 .ops = &clk_rcg2_ops, 975 }, 976 }; 977 978 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { 979 F(60000000, P_GPLL0, 10, 0, 0), 980 F(75000000, P_GPLL0, 8, 0, 0), 981 { } 982 }; 983 984 static struct clk_rcg2 usb_hs_system_clk_src = { 985 .cmd_rcgr = 0x0490, 986 .hid_width = 5, 987 .parent_map = gcc_xo_gpll0_map, 988 .freq_tbl = ftbl_gcc_usb_hs_system_clk, 989 .clkr.hw.init = &(struct clk_init_data){ 990 .name = "usb_hs_system_clk_src", 991 .parent_data = gcc_xo_gpll0, 992 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 993 .ops = &clk_rcg2_ops, 994 }, 995 }; 996 997 static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = { 998 F(480000000, P_GPLL1, 1, 0, 0), 999 { } 1000 }; 1001 1002 static const struct parent_map usb_hsic_clk_src_map[] = { 1003 { P_XO, 0 }, 1004 { P_GPLL1, 4 } 1005 }; 1006 1007 static struct clk_rcg2 usb_hsic_clk_src = { 1008 .cmd_rcgr = 0x0440, 1009 .hid_width = 5, 1010 .parent_map = usb_hsic_clk_src_map, 1011 .freq_tbl = ftbl_gcc_usb_hsic_clk, 1012 .clkr.hw.init = &(struct clk_init_data){ 1013 .name = "usb_hsic_clk_src", 1014 .parent_data = (const struct clk_parent_data[]){ 1015 { .fw_name = "xo", .name = "xo_board" }, 1016 { .hw = &gpll1_vote.hw }, 1017 }, 1018 .num_parents = 2, 1019 .ops = &clk_rcg2_ops, 1020 }, 1021 }; 1022 1023 static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = { 1024 F(9600000, P_XO, 2, 0, 0), 1025 { } 1026 }; 1027 1028 static struct clk_rcg2 usb_hsic_io_cal_clk_src = { 1029 .cmd_rcgr = 0x0458, 1030 .hid_width = 5, 1031 .parent_map = gcc_xo_gpll0_map, 1032 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk, 1033 .clkr.hw.init = &(struct clk_init_data){ 1034 .name = "usb_hsic_io_cal_clk_src", 1035 .parent_data = gcc_xo_gpll0, 1036 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1037 .ops = &clk_rcg2_ops, 1038 }, 1039 }; 1040 1041 static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = { 1042 F(60000000, P_GPLL0, 10, 0, 0), 1043 F(75000000, P_GPLL0, 8, 0, 0), 1044 { } 1045 }; 1046 1047 static struct clk_rcg2 usb_hsic_system_clk_src = { 1048 .cmd_rcgr = 0x041c, 1049 .hid_width = 5, 1050 .parent_map = gcc_xo_gpll0_map, 1051 .freq_tbl = ftbl_gcc_usb_hsic_system_clk, 1052 .clkr.hw.init = &(struct clk_init_data){ 1053 .name = "usb_hsic_system_clk_src", 1054 .parent_data = gcc_xo_gpll0, 1055 .num_parents = ARRAY_SIZE(gcc_xo_gpll0), 1056 .ops = &clk_rcg2_ops, 1057 }, 1058 }; 1059 1060 static struct clk_regmap gcc_mmss_gpll0_clk_src = { 1061 .enable_reg = 0x1484, 1062 .enable_mask = BIT(26), 1063 .hw.init = &(struct clk_init_data){ 1064 .name = "mmss_gpll0_vote", 1065 .parent_hws = (const struct clk_hw*[]){ 1066 &gpll0_vote.hw, 1067 }, 1068 .num_parents = 1, 1069 .ops = &clk_branch_simple_ops, 1070 }, 1071 }; 1072 1073 static struct clk_branch gcc_bam_dma_ahb_clk = { 1074 .halt_reg = 0x0d44, 1075 .halt_check = BRANCH_HALT_VOTED, 1076 .clkr = { 1077 .enable_reg = 0x1484, 1078 .enable_mask = BIT(12), 1079 .hw.init = &(struct clk_init_data){ 1080 .name = "gcc_bam_dma_ahb_clk", 1081 .parent_hws = (const struct clk_hw*[]){ 1082 &periph_noc_clk_src.clkr.hw, 1083 }, 1084 .num_parents = 1, 1085 .ops = &clk_branch2_ops, 1086 }, 1087 }, 1088 }; 1089 1090 static struct clk_branch gcc_blsp1_ahb_clk = { 1091 .halt_reg = 0x05c4, 1092 .halt_check = BRANCH_HALT_VOTED, 1093 .clkr = { 1094 .enable_reg = 0x1484, 1095 .enable_mask = BIT(17), 1096 .hw.init = &(struct clk_init_data){ 1097 .name = "gcc_blsp1_ahb_clk", 1098 .parent_hws = (const struct clk_hw*[]){ 1099 &periph_noc_clk_src.clkr.hw, 1100 }, 1101 .num_parents = 1, 1102 .ops = &clk_branch2_ops, 1103 }, 1104 }, 1105 }; 1106 1107 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1108 .halt_reg = 0x0648, 1109 .clkr = { 1110 .enable_reg = 0x0648, 1111 .enable_mask = BIT(0), 1112 .hw.init = &(struct clk_init_data){ 1113 .name = "gcc_blsp1_qup1_i2c_apps_clk", 1114 .parent_hws = (const struct clk_hw*[]){ 1115 &blsp1_qup1_i2c_apps_clk_src.clkr.hw, 1116 }, 1117 .num_parents = 1, 1118 .flags = CLK_SET_RATE_PARENT, 1119 .ops = &clk_branch2_ops, 1120 }, 1121 }, 1122 }; 1123 1124 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1125 .halt_reg = 0x0644, 1126 .clkr = { 1127 .enable_reg = 0x0644, 1128 .enable_mask = BIT(0), 1129 .hw.init = &(struct clk_init_data){ 1130 .name = "gcc_blsp1_qup1_spi_apps_clk", 1131 .parent_hws = (const struct clk_hw*[]){ 1132 &blsp1_qup1_spi_apps_clk_src.clkr.hw, 1133 }, 1134 .num_parents = 1, 1135 .flags = CLK_SET_RATE_PARENT, 1136 .ops = &clk_branch2_ops, 1137 }, 1138 }, 1139 }; 1140 1141 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1142 .halt_reg = 0x06c8, 1143 .clkr = { 1144 .enable_reg = 0x06c8, 1145 .enable_mask = BIT(0), 1146 .hw.init = &(struct clk_init_data){ 1147 .name = "gcc_blsp1_qup2_i2c_apps_clk", 1148 .parent_hws = (const struct clk_hw*[]){ 1149 &blsp1_qup2_i2c_apps_clk_src.clkr.hw, 1150 }, 1151 .num_parents = 1, 1152 .flags = CLK_SET_RATE_PARENT, 1153 .ops = &clk_branch2_ops, 1154 }, 1155 }, 1156 }; 1157 1158 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1159 .halt_reg = 0x06c4, 1160 .clkr = { 1161 .enable_reg = 0x06c4, 1162 .enable_mask = BIT(0), 1163 .hw.init = &(struct clk_init_data){ 1164 .name = "gcc_blsp1_qup2_spi_apps_clk", 1165 .parent_hws = (const struct clk_hw*[]){ 1166 &blsp1_qup2_spi_apps_clk_src.clkr.hw, 1167 }, 1168 .num_parents = 1, 1169 .flags = CLK_SET_RATE_PARENT, 1170 .ops = &clk_branch2_ops, 1171 }, 1172 }, 1173 }; 1174 1175 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1176 .halt_reg = 0x0748, 1177 .clkr = { 1178 .enable_reg = 0x0748, 1179 .enable_mask = BIT(0), 1180 .hw.init = &(struct clk_init_data){ 1181 .name = "gcc_blsp1_qup3_i2c_apps_clk", 1182 .parent_hws = (const struct clk_hw*[]){ 1183 &blsp1_qup3_i2c_apps_clk_src.clkr.hw, 1184 }, 1185 .num_parents = 1, 1186 .flags = CLK_SET_RATE_PARENT, 1187 .ops = &clk_branch2_ops, 1188 }, 1189 }, 1190 }; 1191 1192 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1193 .halt_reg = 0x0744, 1194 .clkr = { 1195 .enable_reg = 0x0744, 1196 .enable_mask = BIT(0), 1197 .hw.init = &(struct clk_init_data){ 1198 .name = "gcc_blsp1_qup3_spi_apps_clk", 1199 .parent_hws = (const struct clk_hw*[]){ 1200 &blsp1_qup3_spi_apps_clk_src.clkr.hw, 1201 }, 1202 .num_parents = 1, 1203 .flags = CLK_SET_RATE_PARENT, 1204 .ops = &clk_branch2_ops, 1205 }, 1206 }, 1207 }; 1208 1209 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1210 .halt_reg = 0x07c8, 1211 .clkr = { 1212 .enable_reg = 0x07c8, 1213 .enable_mask = BIT(0), 1214 .hw.init = &(struct clk_init_data){ 1215 .name = "gcc_blsp1_qup4_i2c_apps_clk", 1216 .parent_hws = (const struct clk_hw*[]){ 1217 &blsp1_qup4_i2c_apps_clk_src.clkr.hw, 1218 }, 1219 .num_parents = 1, 1220 .flags = CLK_SET_RATE_PARENT, 1221 .ops = &clk_branch2_ops, 1222 }, 1223 }, 1224 }; 1225 1226 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1227 .halt_reg = 0x07c4, 1228 .clkr = { 1229 .enable_reg = 0x07c4, 1230 .enable_mask = BIT(0), 1231 .hw.init = &(struct clk_init_data){ 1232 .name = "gcc_blsp1_qup4_spi_apps_clk", 1233 .parent_hws = (const struct clk_hw*[]){ 1234 &blsp1_qup4_spi_apps_clk_src.clkr.hw, 1235 }, 1236 .num_parents = 1, 1237 .flags = CLK_SET_RATE_PARENT, 1238 .ops = &clk_branch2_ops, 1239 }, 1240 }, 1241 }; 1242 1243 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1244 .halt_reg = 0x0848, 1245 .clkr = { 1246 .enable_reg = 0x0848, 1247 .enable_mask = BIT(0), 1248 .hw.init = &(struct clk_init_data){ 1249 .name = "gcc_blsp1_qup5_i2c_apps_clk", 1250 .parent_hws = (const struct clk_hw*[]){ 1251 &blsp1_qup5_i2c_apps_clk_src.clkr.hw, 1252 }, 1253 .num_parents = 1, 1254 .flags = CLK_SET_RATE_PARENT, 1255 .ops = &clk_branch2_ops, 1256 }, 1257 }, 1258 }; 1259 1260 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1261 .halt_reg = 0x0844, 1262 .clkr = { 1263 .enable_reg = 0x0844, 1264 .enable_mask = BIT(0), 1265 .hw.init = &(struct clk_init_data){ 1266 .name = "gcc_blsp1_qup5_spi_apps_clk", 1267 .parent_hws = (const struct clk_hw*[]){ 1268 &blsp1_qup5_spi_apps_clk_src.clkr.hw, 1269 }, 1270 .num_parents = 1, 1271 .flags = CLK_SET_RATE_PARENT, 1272 .ops = &clk_branch2_ops, 1273 }, 1274 }, 1275 }; 1276 1277 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1278 .halt_reg = 0x08c8, 1279 .clkr = { 1280 .enable_reg = 0x08c8, 1281 .enable_mask = BIT(0), 1282 .hw.init = &(struct clk_init_data){ 1283 .name = "gcc_blsp1_qup6_i2c_apps_clk", 1284 .parent_hws = (const struct clk_hw*[]){ 1285 &blsp1_qup6_i2c_apps_clk_src.clkr.hw, 1286 }, 1287 .num_parents = 1, 1288 .flags = CLK_SET_RATE_PARENT, 1289 .ops = &clk_branch2_ops, 1290 }, 1291 }, 1292 }; 1293 1294 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1295 .halt_reg = 0x08c4, 1296 .clkr = { 1297 .enable_reg = 0x08c4, 1298 .enable_mask = BIT(0), 1299 .hw.init = &(struct clk_init_data){ 1300 .name = "gcc_blsp1_qup6_spi_apps_clk", 1301 .parent_hws = (const struct clk_hw*[]){ 1302 &blsp1_qup6_spi_apps_clk_src.clkr.hw, 1303 }, 1304 .num_parents = 1, 1305 .flags = CLK_SET_RATE_PARENT, 1306 .ops = &clk_branch2_ops, 1307 }, 1308 }, 1309 }; 1310 1311 static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1312 .halt_reg = 0x0684, 1313 .clkr = { 1314 .enable_reg = 0x0684, 1315 .enable_mask = BIT(0), 1316 .hw.init = &(struct clk_init_data){ 1317 .name = "gcc_blsp1_uart1_apps_clk", 1318 .parent_hws = (const struct clk_hw*[]){ 1319 &blsp1_uart1_apps_clk_src.clkr.hw, 1320 }, 1321 .num_parents = 1, 1322 .flags = CLK_SET_RATE_PARENT, 1323 .ops = &clk_branch2_ops, 1324 }, 1325 }, 1326 }; 1327 1328 static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1329 .halt_reg = 0x0704, 1330 .clkr = { 1331 .enable_reg = 0x0704, 1332 .enable_mask = BIT(0), 1333 .hw.init = &(struct clk_init_data){ 1334 .name = "gcc_blsp1_uart2_apps_clk", 1335 .parent_hws = (const struct clk_hw*[]){ 1336 &blsp1_uart2_apps_clk_src.clkr.hw, 1337 }, 1338 .num_parents = 1, 1339 .flags = CLK_SET_RATE_PARENT, 1340 .ops = &clk_branch2_ops, 1341 }, 1342 }, 1343 }; 1344 1345 static struct clk_branch gcc_blsp1_uart3_apps_clk = { 1346 .halt_reg = 0x0784, 1347 .clkr = { 1348 .enable_reg = 0x0784, 1349 .enable_mask = BIT(0), 1350 .hw.init = &(struct clk_init_data){ 1351 .name = "gcc_blsp1_uart3_apps_clk", 1352 .parent_hws = (const struct clk_hw*[]){ 1353 &blsp1_uart3_apps_clk_src.clkr.hw, 1354 }, 1355 .num_parents = 1, 1356 .flags = CLK_SET_RATE_PARENT, 1357 .ops = &clk_branch2_ops, 1358 }, 1359 }, 1360 }; 1361 1362 static struct clk_branch gcc_blsp1_uart4_apps_clk = { 1363 .halt_reg = 0x0804, 1364 .clkr = { 1365 .enable_reg = 0x0804, 1366 .enable_mask = BIT(0), 1367 .hw.init = &(struct clk_init_data){ 1368 .name = "gcc_blsp1_uart4_apps_clk", 1369 .parent_hws = (const struct clk_hw*[]){ 1370 &blsp1_uart4_apps_clk_src.clkr.hw, 1371 }, 1372 .num_parents = 1, 1373 .flags = CLK_SET_RATE_PARENT, 1374 .ops = &clk_branch2_ops, 1375 }, 1376 }, 1377 }; 1378 1379 static struct clk_branch gcc_blsp1_uart5_apps_clk = { 1380 .halt_reg = 0x0884, 1381 .clkr = { 1382 .enable_reg = 0x0884, 1383 .enable_mask = BIT(0), 1384 .hw.init = &(struct clk_init_data){ 1385 .name = "gcc_blsp1_uart5_apps_clk", 1386 .parent_hws = (const struct clk_hw*[]){ 1387 &blsp1_uart5_apps_clk_src.clkr.hw, 1388 }, 1389 .num_parents = 1, 1390 .flags = CLK_SET_RATE_PARENT, 1391 .ops = &clk_branch2_ops, 1392 }, 1393 }, 1394 }; 1395 1396 static struct clk_branch gcc_blsp1_uart6_apps_clk = { 1397 .halt_reg = 0x0904, 1398 .clkr = { 1399 .enable_reg = 0x0904, 1400 .enable_mask = BIT(0), 1401 .hw.init = &(struct clk_init_data){ 1402 .name = "gcc_blsp1_uart6_apps_clk", 1403 .parent_hws = (const struct clk_hw*[]){ 1404 &blsp1_uart6_apps_clk_src.clkr.hw, 1405 }, 1406 .num_parents = 1, 1407 .flags = CLK_SET_RATE_PARENT, 1408 .ops = &clk_branch2_ops, 1409 }, 1410 }, 1411 }; 1412 1413 static struct clk_branch gcc_blsp2_ahb_clk = { 1414 .halt_reg = 0x0944, 1415 .halt_check = BRANCH_HALT_VOTED, 1416 .clkr = { 1417 .enable_reg = 0x1484, 1418 .enable_mask = BIT(15), 1419 .hw.init = &(struct clk_init_data){ 1420 .name = "gcc_blsp2_ahb_clk", 1421 .parent_hws = (const struct clk_hw*[]){ 1422 &periph_noc_clk_src.clkr.hw, 1423 }, 1424 .num_parents = 1, 1425 .ops = &clk_branch2_ops, 1426 }, 1427 }, 1428 }; 1429 1430 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { 1431 .halt_reg = 0x0988, 1432 .clkr = { 1433 .enable_reg = 0x0988, 1434 .enable_mask = BIT(0), 1435 .hw.init = &(struct clk_init_data){ 1436 .name = "gcc_blsp2_qup1_i2c_apps_clk", 1437 .parent_hws = (const struct clk_hw*[]){ 1438 &blsp2_qup1_i2c_apps_clk_src.clkr.hw, 1439 }, 1440 .num_parents = 1, 1441 .flags = CLK_SET_RATE_PARENT, 1442 .ops = &clk_branch2_ops, 1443 }, 1444 }, 1445 }; 1446 1447 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { 1448 .halt_reg = 0x0984, 1449 .clkr = { 1450 .enable_reg = 0x0984, 1451 .enable_mask = BIT(0), 1452 .hw.init = &(struct clk_init_data){ 1453 .name = "gcc_blsp2_qup1_spi_apps_clk", 1454 .parent_hws = (const struct clk_hw*[]){ 1455 &blsp2_qup1_spi_apps_clk_src.clkr.hw, 1456 }, 1457 .num_parents = 1, 1458 .flags = CLK_SET_RATE_PARENT, 1459 .ops = &clk_branch2_ops, 1460 }, 1461 }, 1462 }; 1463 1464 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { 1465 .halt_reg = 0x0a08, 1466 .clkr = { 1467 .enable_reg = 0x0a08, 1468 .enable_mask = BIT(0), 1469 .hw.init = &(struct clk_init_data){ 1470 .name = "gcc_blsp2_qup2_i2c_apps_clk", 1471 .parent_hws = (const struct clk_hw*[]){ 1472 &blsp2_qup2_i2c_apps_clk_src.clkr.hw, 1473 }, 1474 .num_parents = 1, 1475 .flags = CLK_SET_RATE_PARENT, 1476 .ops = &clk_branch2_ops, 1477 }, 1478 }, 1479 }; 1480 1481 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { 1482 .halt_reg = 0x0a04, 1483 .clkr = { 1484 .enable_reg = 0x0a04, 1485 .enable_mask = BIT(0), 1486 .hw.init = &(struct clk_init_data){ 1487 .name = "gcc_blsp2_qup2_spi_apps_clk", 1488 .parent_hws = (const struct clk_hw*[]){ 1489 &blsp2_qup2_spi_apps_clk_src.clkr.hw, 1490 }, 1491 .num_parents = 1, 1492 .flags = CLK_SET_RATE_PARENT, 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { 1499 .halt_reg = 0x0a88, 1500 .clkr = { 1501 .enable_reg = 0x0a88, 1502 .enable_mask = BIT(0), 1503 .hw.init = &(struct clk_init_data){ 1504 .name = "gcc_blsp2_qup3_i2c_apps_clk", 1505 .parent_hws = (const struct clk_hw*[]){ 1506 &blsp2_qup3_i2c_apps_clk_src.clkr.hw, 1507 }, 1508 .num_parents = 1, 1509 .flags = CLK_SET_RATE_PARENT, 1510 .ops = &clk_branch2_ops, 1511 }, 1512 }, 1513 }; 1514 1515 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { 1516 .halt_reg = 0x0a84, 1517 .clkr = { 1518 .enable_reg = 0x0a84, 1519 .enable_mask = BIT(0), 1520 .hw.init = &(struct clk_init_data){ 1521 .name = "gcc_blsp2_qup3_spi_apps_clk", 1522 .parent_hws = (const struct clk_hw*[]){ 1523 &blsp2_qup3_spi_apps_clk_src.clkr.hw, 1524 }, 1525 .num_parents = 1, 1526 .flags = CLK_SET_RATE_PARENT, 1527 .ops = &clk_branch2_ops, 1528 }, 1529 }, 1530 }; 1531 1532 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { 1533 .halt_reg = 0x0b08, 1534 .clkr = { 1535 .enable_reg = 0x0b08, 1536 .enable_mask = BIT(0), 1537 .hw.init = &(struct clk_init_data){ 1538 .name = "gcc_blsp2_qup4_i2c_apps_clk", 1539 .parent_hws = (const struct clk_hw*[]){ 1540 &blsp2_qup4_i2c_apps_clk_src.clkr.hw, 1541 }, 1542 .num_parents = 1, 1543 .flags = CLK_SET_RATE_PARENT, 1544 .ops = &clk_branch2_ops, 1545 }, 1546 }, 1547 }; 1548 1549 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { 1550 .halt_reg = 0x0b04, 1551 .clkr = { 1552 .enable_reg = 0x0b04, 1553 .enable_mask = BIT(0), 1554 .hw.init = &(struct clk_init_data){ 1555 .name = "gcc_blsp2_qup4_spi_apps_clk", 1556 .parent_hws = (const struct clk_hw*[]){ 1557 &blsp2_qup4_spi_apps_clk_src.clkr.hw, 1558 }, 1559 .num_parents = 1, 1560 .flags = CLK_SET_RATE_PARENT, 1561 .ops = &clk_branch2_ops, 1562 }, 1563 }, 1564 }; 1565 1566 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { 1567 .halt_reg = 0x0b88, 1568 .clkr = { 1569 .enable_reg = 0x0b88, 1570 .enable_mask = BIT(0), 1571 .hw.init = &(struct clk_init_data){ 1572 .name = "gcc_blsp2_qup5_i2c_apps_clk", 1573 .parent_hws = (const struct clk_hw*[]){ 1574 &blsp2_qup5_i2c_apps_clk_src.clkr.hw, 1575 }, 1576 .num_parents = 1, 1577 .flags = CLK_SET_RATE_PARENT, 1578 .ops = &clk_branch2_ops, 1579 }, 1580 }, 1581 }; 1582 1583 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { 1584 .halt_reg = 0x0b84, 1585 .clkr = { 1586 .enable_reg = 0x0b84, 1587 .enable_mask = BIT(0), 1588 .hw.init = &(struct clk_init_data){ 1589 .name = "gcc_blsp2_qup5_spi_apps_clk", 1590 .parent_hws = (const struct clk_hw*[]){ 1591 &blsp2_qup5_spi_apps_clk_src.clkr.hw, 1592 }, 1593 .num_parents = 1, 1594 .flags = CLK_SET_RATE_PARENT, 1595 .ops = &clk_branch2_ops, 1596 }, 1597 }, 1598 }; 1599 1600 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { 1601 .halt_reg = 0x0c08, 1602 .clkr = { 1603 .enable_reg = 0x0c08, 1604 .enable_mask = BIT(0), 1605 .hw.init = &(struct clk_init_data){ 1606 .name = "gcc_blsp2_qup6_i2c_apps_clk", 1607 .parent_hws = (const struct clk_hw*[]){ 1608 &blsp2_qup6_i2c_apps_clk_src.clkr.hw, 1609 }, 1610 .num_parents = 1, 1611 .flags = CLK_SET_RATE_PARENT, 1612 .ops = &clk_branch2_ops, 1613 }, 1614 }, 1615 }; 1616 1617 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { 1618 .halt_reg = 0x0c04, 1619 .clkr = { 1620 .enable_reg = 0x0c04, 1621 .enable_mask = BIT(0), 1622 .hw.init = &(struct clk_init_data){ 1623 .name = "gcc_blsp2_qup6_spi_apps_clk", 1624 .parent_hws = (const struct clk_hw*[]){ 1625 &blsp2_qup6_spi_apps_clk_src.clkr.hw, 1626 }, 1627 .num_parents = 1, 1628 .flags = CLK_SET_RATE_PARENT, 1629 .ops = &clk_branch2_ops, 1630 }, 1631 }, 1632 }; 1633 1634 static struct clk_branch gcc_blsp2_uart1_apps_clk = { 1635 .halt_reg = 0x09c4, 1636 .clkr = { 1637 .enable_reg = 0x09c4, 1638 .enable_mask = BIT(0), 1639 .hw.init = &(struct clk_init_data){ 1640 .name = "gcc_blsp2_uart1_apps_clk", 1641 .parent_hws = (const struct clk_hw*[]){ 1642 &blsp2_uart1_apps_clk_src.clkr.hw, 1643 }, 1644 .num_parents = 1, 1645 .flags = CLK_SET_RATE_PARENT, 1646 .ops = &clk_branch2_ops, 1647 }, 1648 }, 1649 }; 1650 1651 static struct clk_branch gcc_blsp2_uart2_apps_clk = { 1652 .halt_reg = 0x0a44, 1653 .clkr = { 1654 .enable_reg = 0x0a44, 1655 .enable_mask = BIT(0), 1656 .hw.init = &(struct clk_init_data){ 1657 .name = "gcc_blsp2_uart2_apps_clk", 1658 .parent_hws = (const struct clk_hw*[]){ 1659 &blsp2_uart2_apps_clk_src.clkr.hw, 1660 }, 1661 .num_parents = 1, 1662 .flags = CLK_SET_RATE_PARENT, 1663 .ops = &clk_branch2_ops, 1664 }, 1665 }, 1666 }; 1667 1668 static struct clk_branch gcc_blsp2_uart3_apps_clk = { 1669 .halt_reg = 0x0ac4, 1670 .clkr = { 1671 .enable_reg = 0x0ac4, 1672 .enable_mask = BIT(0), 1673 .hw.init = &(struct clk_init_data){ 1674 .name = "gcc_blsp2_uart3_apps_clk", 1675 .parent_hws = (const struct clk_hw*[]){ 1676 &blsp2_uart3_apps_clk_src.clkr.hw, 1677 }, 1678 .num_parents = 1, 1679 .flags = CLK_SET_RATE_PARENT, 1680 .ops = &clk_branch2_ops, 1681 }, 1682 }, 1683 }; 1684 1685 static struct clk_branch gcc_blsp2_uart4_apps_clk = { 1686 .halt_reg = 0x0b44, 1687 .clkr = { 1688 .enable_reg = 0x0b44, 1689 .enable_mask = BIT(0), 1690 .hw.init = &(struct clk_init_data){ 1691 .name = "gcc_blsp2_uart4_apps_clk", 1692 .parent_hws = (const struct clk_hw*[]){ 1693 &blsp2_uart4_apps_clk_src.clkr.hw, 1694 }, 1695 .num_parents = 1, 1696 .flags = CLK_SET_RATE_PARENT, 1697 .ops = &clk_branch2_ops, 1698 }, 1699 }, 1700 }; 1701 1702 static struct clk_branch gcc_blsp2_uart5_apps_clk = { 1703 .halt_reg = 0x0bc4, 1704 .clkr = { 1705 .enable_reg = 0x0bc4, 1706 .enable_mask = BIT(0), 1707 .hw.init = &(struct clk_init_data){ 1708 .name = "gcc_blsp2_uart5_apps_clk", 1709 .parent_hws = (const struct clk_hw*[]){ 1710 &blsp2_uart5_apps_clk_src.clkr.hw, 1711 }, 1712 .num_parents = 1, 1713 .flags = CLK_SET_RATE_PARENT, 1714 .ops = &clk_branch2_ops, 1715 }, 1716 }, 1717 }; 1718 1719 static struct clk_branch gcc_blsp2_uart6_apps_clk = { 1720 .halt_reg = 0x0c44, 1721 .clkr = { 1722 .enable_reg = 0x0c44, 1723 .enable_mask = BIT(0), 1724 .hw.init = &(struct clk_init_data){ 1725 .name = "gcc_blsp2_uart6_apps_clk", 1726 .parent_hws = (const struct clk_hw*[]){ 1727 &blsp2_uart6_apps_clk_src.clkr.hw, 1728 }, 1729 .num_parents = 1, 1730 .flags = CLK_SET_RATE_PARENT, 1731 .ops = &clk_branch2_ops, 1732 }, 1733 }, 1734 }; 1735 1736 static struct clk_branch gcc_boot_rom_ahb_clk = { 1737 .halt_reg = 0x0e04, 1738 .halt_check = BRANCH_HALT_VOTED, 1739 .clkr = { 1740 .enable_reg = 0x1484, 1741 .enable_mask = BIT(10), 1742 .hw.init = &(struct clk_init_data){ 1743 .name = "gcc_boot_rom_ahb_clk", 1744 .parent_hws = (const struct clk_hw*[]){ 1745 &config_noc_clk_src.clkr.hw, 1746 }, 1747 .num_parents = 1, 1748 .ops = &clk_branch2_ops, 1749 }, 1750 }, 1751 }; 1752 1753 static struct clk_branch gcc_ce1_ahb_clk = { 1754 .halt_reg = 0x104c, 1755 .halt_check = BRANCH_HALT_VOTED, 1756 .clkr = { 1757 .enable_reg = 0x1484, 1758 .enable_mask = BIT(3), 1759 .hw.init = &(struct clk_init_data){ 1760 .name = "gcc_ce1_ahb_clk", 1761 .parent_hws = (const struct clk_hw*[]){ 1762 &config_noc_clk_src.clkr.hw, 1763 }, 1764 .num_parents = 1, 1765 .ops = &clk_branch2_ops, 1766 }, 1767 }, 1768 }; 1769 1770 static struct clk_branch gcc_ce1_axi_clk = { 1771 .halt_reg = 0x1048, 1772 .halt_check = BRANCH_HALT_VOTED, 1773 .clkr = { 1774 .enable_reg = 0x1484, 1775 .enable_mask = BIT(4), 1776 .hw.init = &(struct clk_init_data){ 1777 .name = "gcc_ce1_axi_clk", 1778 .parent_hws = (const struct clk_hw*[]){ 1779 &system_noc_clk_src.clkr.hw, 1780 }, 1781 .num_parents = 1, 1782 .ops = &clk_branch2_ops, 1783 }, 1784 }, 1785 }; 1786 1787 static struct clk_branch gcc_ce1_clk = { 1788 .halt_reg = 0x1050, 1789 .halt_check = BRANCH_HALT_VOTED, 1790 .clkr = { 1791 .enable_reg = 0x1484, 1792 .enable_mask = BIT(5), 1793 .hw.init = &(struct clk_init_data){ 1794 .name = "gcc_ce1_clk", 1795 .parent_hws = (const struct clk_hw*[]){ 1796 &ce1_clk_src.clkr.hw, 1797 }, 1798 .num_parents = 1, 1799 .flags = CLK_SET_RATE_PARENT, 1800 .ops = &clk_branch2_ops, 1801 }, 1802 }, 1803 }; 1804 1805 static struct clk_branch gcc_ce2_ahb_clk = { 1806 .halt_reg = 0x108c, 1807 .halt_check = BRANCH_HALT_VOTED, 1808 .clkr = { 1809 .enable_reg = 0x1484, 1810 .enable_mask = BIT(0), 1811 .hw.init = &(struct clk_init_data){ 1812 .name = "gcc_ce2_ahb_clk", 1813 .parent_hws = (const struct clk_hw*[]){ 1814 &config_noc_clk_src.clkr.hw, 1815 }, 1816 .num_parents = 1, 1817 .ops = &clk_branch2_ops, 1818 }, 1819 }, 1820 }; 1821 1822 static struct clk_branch gcc_ce2_axi_clk = { 1823 .halt_reg = 0x1088, 1824 .halt_check = BRANCH_HALT_VOTED, 1825 .clkr = { 1826 .enable_reg = 0x1484, 1827 .enable_mask = BIT(1), 1828 .hw.init = &(struct clk_init_data){ 1829 .name = "gcc_ce2_axi_clk", 1830 .parent_hws = (const struct clk_hw*[]){ 1831 &system_noc_clk_src.clkr.hw, 1832 }, 1833 .num_parents = 1, 1834 .ops = &clk_branch2_ops, 1835 }, 1836 }, 1837 }; 1838 1839 static struct clk_branch gcc_ce2_clk = { 1840 .halt_reg = 0x1090, 1841 .halt_check = BRANCH_HALT_VOTED, 1842 .clkr = { 1843 .enable_reg = 0x1484, 1844 .enable_mask = BIT(2), 1845 .hw.init = &(struct clk_init_data){ 1846 .name = "gcc_ce2_clk", 1847 .parent_hws = (const struct clk_hw*[]){ 1848 &ce2_clk_src.clkr.hw, 1849 }, 1850 .num_parents = 1, 1851 .flags = CLK_SET_RATE_PARENT, 1852 .ops = &clk_branch2_ops, 1853 }, 1854 }, 1855 }; 1856 1857 static struct clk_branch gcc_gp1_clk = { 1858 .halt_reg = 0x1900, 1859 .clkr = { 1860 .enable_reg = 0x1900, 1861 .enable_mask = BIT(0), 1862 .hw.init = &(struct clk_init_data){ 1863 .name = "gcc_gp1_clk", 1864 .parent_hws = (const struct clk_hw*[]){ 1865 &gp1_clk_src.clkr.hw, 1866 }, 1867 .num_parents = 1, 1868 .flags = CLK_SET_RATE_PARENT, 1869 .ops = &clk_branch2_ops, 1870 }, 1871 }, 1872 }; 1873 1874 static struct clk_branch gcc_gp2_clk = { 1875 .halt_reg = 0x1940, 1876 .clkr = { 1877 .enable_reg = 0x1940, 1878 .enable_mask = BIT(0), 1879 .hw.init = &(struct clk_init_data){ 1880 .name = "gcc_gp2_clk", 1881 .parent_hws = (const struct clk_hw*[]){ 1882 &gp2_clk_src.clkr.hw, 1883 }, 1884 .num_parents = 1, 1885 .flags = CLK_SET_RATE_PARENT, 1886 .ops = &clk_branch2_ops, 1887 }, 1888 }, 1889 }; 1890 1891 static struct clk_branch gcc_gp3_clk = { 1892 .halt_reg = 0x1980, 1893 .clkr = { 1894 .enable_reg = 0x1980, 1895 .enable_mask = BIT(0), 1896 .hw.init = &(struct clk_init_data){ 1897 .name = "gcc_gp3_clk", 1898 .parent_hws = (const struct clk_hw*[]){ 1899 &gp3_clk_src.clkr.hw, 1900 }, 1901 .num_parents = 1, 1902 .flags = CLK_SET_RATE_PARENT, 1903 .ops = &clk_branch2_ops, 1904 }, 1905 }, 1906 }; 1907 1908 static struct clk_branch gcc_lpass_q6_axi_clk = { 1909 .halt_reg = 0x11c0, 1910 .clkr = { 1911 .enable_reg = 0x11c0, 1912 .enable_mask = BIT(0), 1913 .hw.init = &(struct clk_init_data){ 1914 .name = "gcc_lpass_q6_axi_clk", 1915 .parent_hws = (const struct clk_hw*[]){ 1916 &system_noc_clk_src.clkr.hw, 1917 }, 1918 .num_parents = 1, 1919 .ops = &clk_branch2_ops, 1920 }, 1921 }, 1922 }; 1923 1924 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { 1925 .halt_reg = 0x024c, 1926 .clkr = { 1927 .enable_reg = 0x024c, 1928 .enable_mask = BIT(0), 1929 .hw.init = &(struct clk_init_data){ 1930 .name = "gcc_mmss_noc_cfg_ahb_clk", 1931 .parent_hws = (const struct clk_hw*[]){ 1932 &config_noc_clk_src.clkr.hw, 1933 }, 1934 .num_parents = 1, 1935 .ops = &clk_branch2_ops, 1936 .flags = CLK_IGNORE_UNUSED, 1937 }, 1938 }, 1939 }; 1940 1941 static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = { 1942 .halt_reg = 0x0248, 1943 .clkr = { 1944 .enable_reg = 0x0248, 1945 .enable_mask = BIT(0), 1946 .hw.init = &(struct clk_init_data){ 1947 .name = "gcc_ocmem_noc_cfg_ahb_clk", 1948 .parent_hws = (const struct clk_hw*[]){ 1949 &config_noc_clk_src.clkr.hw, 1950 }, 1951 .num_parents = 1, 1952 .ops = &clk_branch2_ops, 1953 }, 1954 }, 1955 }; 1956 1957 static struct clk_branch gcc_mss_cfg_ahb_clk = { 1958 .halt_reg = 0x0280, 1959 .clkr = { 1960 .enable_reg = 0x0280, 1961 .enable_mask = BIT(0), 1962 .hw.init = &(struct clk_init_data){ 1963 .name = "gcc_mss_cfg_ahb_clk", 1964 .parent_hws = (const struct clk_hw*[]){ 1965 &config_noc_clk_src.clkr.hw, 1966 }, 1967 .num_parents = 1, 1968 .ops = &clk_branch2_ops, 1969 }, 1970 }, 1971 }; 1972 1973 static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 1974 .halt_reg = 0x0284, 1975 .clkr = { 1976 .enable_reg = 0x0284, 1977 .enable_mask = BIT(0), 1978 .hw.init = &(struct clk_init_data){ 1979 .name = "gcc_mss_q6_bimc_axi_clk", 1980 .parent_hws = (const struct clk_hw*[]){ 1981 &system_noc_clk_src.clkr.hw, 1982 }, 1983 .num_parents = 1, 1984 .ops = &clk_branch2_ops, 1985 }, 1986 }, 1987 }; 1988 1989 static struct clk_branch gcc_pdm2_clk = { 1990 .halt_reg = 0x0ccc, 1991 .clkr = { 1992 .enable_reg = 0x0ccc, 1993 .enable_mask = BIT(0), 1994 .hw.init = &(struct clk_init_data){ 1995 .name = "gcc_pdm2_clk", 1996 .parent_hws = (const struct clk_hw*[]){ 1997 &pdm2_clk_src.clkr.hw, 1998 }, 1999 .num_parents = 1, 2000 .flags = CLK_SET_RATE_PARENT, 2001 .ops = &clk_branch2_ops, 2002 }, 2003 }, 2004 }; 2005 2006 static struct clk_branch gcc_pdm_ahb_clk = { 2007 .halt_reg = 0x0cc4, 2008 .clkr = { 2009 .enable_reg = 0x0cc4, 2010 .enable_mask = BIT(0), 2011 .hw.init = &(struct clk_init_data){ 2012 .name = "gcc_pdm_ahb_clk", 2013 .parent_hws = (const struct clk_hw*[]){ 2014 &periph_noc_clk_src.clkr.hw, 2015 }, 2016 .num_parents = 1, 2017 .ops = &clk_branch2_ops, 2018 }, 2019 }, 2020 }; 2021 2022 static struct clk_branch gcc_pdm_xo4_clk = { 2023 .halt_reg = 0x0cc8, 2024 .clkr = { 2025 .enable_reg = 0x0cc8, 2026 .enable_mask = BIT(0), 2027 .hw.init = &(struct clk_init_data){ 2028 .name = "gcc_pdm_xo4_clk", 2029 .parent_data = &(const struct clk_parent_data){ 2030 .fw_name = "xo", .name = "xo_board", 2031 }, 2032 .num_parents = 1, 2033 .ops = &clk_branch2_ops, 2034 }, 2035 }, 2036 }; 2037 2038 static struct clk_branch gcc_prng_ahb_clk = { 2039 .halt_reg = 0x0d04, 2040 .halt_check = BRANCH_HALT_VOTED, 2041 .clkr = { 2042 .enable_reg = 0x1484, 2043 .enable_mask = BIT(13), 2044 .hw.init = &(struct clk_init_data){ 2045 .name = "gcc_prng_ahb_clk", 2046 .parent_hws = (const struct clk_hw*[]){ 2047 &periph_noc_clk_src.clkr.hw, 2048 }, 2049 .num_parents = 1, 2050 .ops = &clk_branch2_ops, 2051 }, 2052 }, 2053 }; 2054 2055 static struct clk_branch gcc_sdcc1_ahb_clk = { 2056 .halt_reg = 0x04c8, 2057 .clkr = { 2058 .enable_reg = 0x04c8, 2059 .enable_mask = BIT(0), 2060 .hw.init = &(struct clk_init_data){ 2061 .name = "gcc_sdcc1_ahb_clk", 2062 .parent_hws = (const struct clk_hw*[]){ 2063 &periph_noc_clk_src.clkr.hw, 2064 }, 2065 .num_parents = 1, 2066 .ops = &clk_branch2_ops, 2067 }, 2068 }, 2069 }; 2070 2071 static struct clk_branch gcc_sdcc1_apps_clk = { 2072 .halt_reg = 0x04c4, 2073 .clkr = { 2074 .enable_reg = 0x04c4, 2075 .enable_mask = BIT(0), 2076 .hw.init = &(struct clk_init_data){ 2077 .name = "gcc_sdcc1_apps_clk", 2078 .parent_hws = (const struct clk_hw*[]){ 2079 &sdcc1_apps_clk_src.clkr.hw, 2080 }, 2081 .num_parents = 1, 2082 .flags = CLK_SET_RATE_PARENT, 2083 .ops = &clk_branch2_ops, 2084 }, 2085 }, 2086 }; 2087 2088 static struct clk_branch gcc_sdcc1_cdccal_ff_clk = { 2089 .halt_reg = 0x04e8, 2090 .clkr = { 2091 .enable_reg = 0x04e8, 2092 .enable_mask = BIT(0), 2093 .hw.init = &(struct clk_init_data){ 2094 .name = "gcc_sdcc1_cdccal_ff_clk", 2095 .parent_data = (const struct clk_parent_data[]){ 2096 { .fw_name = "xo", .name = "xo_board" } 2097 }, 2098 .num_parents = 1, 2099 .ops = &clk_branch2_ops, 2100 }, 2101 }, 2102 }; 2103 2104 static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = { 2105 .halt_reg = 0x04e4, 2106 .clkr = { 2107 .enable_reg = 0x04e4, 2108 .enable_mask = BIT(0), 2109 .hw.init = &(struct clk_init_data){ 2110 .name = "gcc_sdcc1_cdccal_sleep_clk", 2111 .parent_data = (const struct clk_parent_data[]){ 2112 { .fw_name = "sleep_clk", .name = "sleep_clk" } 2113 }, 2114 .num_parents = 1, 2115 .ops = &clk_branch2_ops, 2116 }, 2117 }, 2118 }; 2119 2120 static struct clk_branch gcc_sdcc2_ahb_clk = { 2121 .halt_reg = 0x0508, 2122 .clkr = { 2123 .enable_reg = 0x0508, 2124 .enable_mask = BIT(0), 2125 .hw.init = &(struct clk_init_data){ 2126 .name = "gcc_sdcc2_ahb_clk", 2127 .parent_hws = (const struct clk_hw*[]){ 2128 &periph_noc_clk_src.clkr.hw, 2129 }, 2130 .num_parents = 1, 2131 .ops = &clk_branch2_ops, 2132 }, 2133 }, 2134 }; 2135 2136 static struct clk_branch gcc_sdcc2_apps_clk = { 2137 .halt_reg = 0x0504, 2138 .clkr = { 2139 .enable_reg = 0x0504, 2140 .enable_mask = BIT(0), 2141 .hw.init = &(struct clk_init_data){ 2142 .name = "gcc_sdcc2_apps_clk", 2143 .parent_hws = (const struct clk_hw*[]){ 2144 &sdcc2_apps_clk_src.clkr.hw, 2145 }, 2146 .num_parents = 1, 2147 .flags = CLK_SET_RATE_PARENT, 2148 .ops = &clk_branch2_ops, 2149 }, 2150 }, 2151 }; 2152 2153 static struct clk_branch gcc_sdcc3_ahb_clk = { 2154 .halt_reg = 0x0548, 2155 .clkr = { 2156 .enable_reg = 0x0548, 2157 .enable_mask = BIT(0), 2158 .hw.init = &(struct clk_init_data){ 2159 .name = "gcc_sdcc3_ahb_clk", 2160 .parent_hws = (const struct clk_hw*[]){ 2161 &periph_noc_clk_src.clkr.hw, 2162 }, 2163 .num_parents = 1, 2164 .ops = &clk_branch2_ops, 2165 }, 2166 }, 2167 }; 2168 2169 static struct clk_branch gcc_sdcc3_apps_clk = { 2170 .halt_reg = 0x0544, 2171 .clkr = { 2172 .enable_reg = 0x0544, 2173 .enable_mask = BIT(0), 2174 .hw.init = &(struct clk_init_data){ 2175 .name = "gcc_sdcc3_apps_clk", 2176 .parent_hws = (const struct clk_hw*[]){ 2177 &sdcc3_apps_clk_src.clkr.hw, 2178 }, 2179 .num_parents = 1, 2180 .flags = CLK_SET_RATE_PARENT, 2181 .ops = &clk_branch2_ops, 2182 }, 2183 }, 2184 }; 2185 2186 static struct clk_branch gcc_sdcc4_ahb_clk = { 2187 .halt_reg = 0x0588, 2188 .clkr = { 2189 .enable_reg = 0x0588, 2190 .enable_mask = BIT(0), 2191 .hw.init = &(struct clk_init_data){ 2192 .name = "gcc_sdcc4_ahb_clk", 2193 .parent_hws = (const struct clk_hw*[]){ 2194 &periph_noc_clk_src.clkr.hw, 2195 }, 2196 .num_parents = 1, 2197 .ops = &clk_branch2_ops, 2198 }, 2199 }, 2200 }; 2201 2202 static struct clk_branch gcc_sdcc4_apps_clk = { 2203 .halt_reg = 0x0584, 2204 .clkr = { 2205 .enable_reg = 0x0584, 2206 .enable_mask = BIT(0), 2207 .hw.init = &(struct clk_init_data){ 2208 .name = "gcc_sdcc4_apps_clk", 2209 .parent_hws = (const struct clk_hw*[]){ 2210 &sdcc4_apps_clk_src.clkr.hw, 2211 }, 2212 .num_parents = 1, 2213 .flags = CLK_SET_RATE_PARENT, 2214 .ops = &clk_branch2_ops, 2215 }, 2216 }, 2217 }; 2218 2219 static struct clk_branch gcc_sys_noc_usb3_axi_clk = { 2220 .halt_reg = 0x0108, 2221 .clkr = { 2222 .enable_reg = 0x0108, 2223 .enable_mask = BIT(0), 2224 .hw.init = &(struct clk_init_data){ 2225 .name = "gcc_sys_noc_usb3_axi_clk", 2226 .parent_hws = (const struct clk_hw*[]){ 2227 &usb30_master_clk_src.clkr.hw, 2228 }, 2229 .num_parents = 1, 2230 .flags = CLK_SET_RATE_PARENT, 2231 .ops = &clk_branch2_ops, 2232 }, 2233 }, 2234 }; 2235 2236 static struct clk_branch gcc_tsif_ahb_clk = { 2237 .halt_reg = 0x0d84, 2238 .clkr = { 2239 .enable_reg = 0x0d84, 2240 .enable_mask = BIT(0), 2241 .hw.init = &(struct clk_init_data){ 2242 .name = "gcc_tsif_ahb_clk", 2243 .parent_hws = (const struct clk_hw*[]){ 2244 &periph_noc_clk_src.clkr.hw, 2245 }, 2246 .num_parents = 1, 2247 .ops = &clk_branch2_ops, 2248 }, 2249 }, 2250 }; 2251 2252 static struct clk_branch gcc_tsif_ref_clk = { 2253 .halt_reg = 0x0d88, 2254 .clkr = { 2255 .enable_reg = 0x0d88, 2256 .enable_mask = BIT(0), 2257 .hw.init = &(struct clk_init_data){ 2258 .name = "gcc_tsif_ref_clk", 2259 .parent_hws = (const struct clk_hw*[]){ 2260 &tsif_ref_clk_src.clkr.hw, 2261 }, 2262 .num_parents = 1, 2263 .flags = CLK_SET_RATE_PARENT, 2264 .ops = &clk_branch2_ops, 2265 }, 2266 }, 2267 }; 2268 2269 static struct clk_branch gcc_usb2a_phy_sleep_clk = { 2270 .halt_reg = 0x04ac, 2271 .clkr = { 2272 .enable_reg = 0x04ac, 2273 .enable_mask = BIT(0), 2274 .hw.init = &(struct clk_init_data){ 2275 .name = "gcc_usb2a_phy_sleep_clk", 2276 .parent_data = &(const struct clk_parent_data){ 2277 .fw_name = "sleep_clk", .name = "sleep_clk", 2278 }, 2279 .num_parents = 1, 2280 .ops = &clk_branch2_ops, 2281 }, 2282 }, 2283 }; 2284 2285 static struct clk_branch gcc_usb2b_phy_sleep_clk = { 2286 .halt_reg = 0x04b4, 2287 .clkr = { 2288 .enable_reg = 0x04b4, 2289 .enable_mask = BIT(0), 2290 .hw.init = &(struct clk_init_data){ 2291 .name = "gcc_usb2b_phy_sleep_clk", 2292 .parent_data = &(const struct clk_parent_data){ 2293 .fw_name = "sleep_clk", .name = "sleep_clk", 2294 }, 2295 .num_parents = 1, 2296 .ops = &clk_branch2_ops, 2297 }, 2298 }, 2299 }; 2300 2301 static struct clk_branch gcc_usb30_master_clk = { 2302 .halt_reg = 0x03c8, 2303 .clkr = { 2304 .enable_reg = 0x03c8, 2305 .enable_mask = BIT(0), 2306 .hw.init = &(struct clk_init_data){ 2307 .name = "gcc_usb30_master_clk", 2308 .parent_hws = (const struct clk_hw*[]){ 2309 &usb30_master_clk_src.clkr.hw, 2310 }, 2311 .num_parents = 1, 2312 .flags = CLK_SET_RATE_PARENT, 2313 .ops = &clk_branch2_ops, 2314 }, 2315 }, 2316 }; 2317 2318 static struct clk_branch gcc_usb30_mock_utmi_clk = { 2319 .halt_reg = 0x03d0, 2320 .clkr = { 2321 .enable_reg = 0x03d0, 2322 .enable_mask = BIT(0), 2323 .hw.init = &(struct clk_init_data){ 2324 .name = "gcc_usb30_mock_utmi_clk", 2325 .parent_hws = (const struct clk_hw*[]){ 2326 &usb30_mock_utmi_clk_src.clkr.hw, 2327 }, 2328 .num_parents = 1, 2329 .flags = CLK_SET_RATE_PARENT, 2330 .ops = &clk_branch2_ops, 2331 }, 2332 }, 2333 }; 2334 2335 static struct clk_branch gcc_usb30_sleep_clk = { 2336 .halt_reg = 0x03cc, 2337 .clkr = { 2338 .enable_reg = 0x03cc, 2339 .enable_mask = BIT(0), 2340 .hw.init = &(struct clk_init_data){ 2341 .name = "gcc_usb30_sleep_clk", 2342 .parent_data = &(const struct clk_parent_data){ 2343 .fw_name = "sleep_clk", .name = "sleep_clk", 2344 }, 2345 .num_parents = 1, 2346 .ops = &clk_branch2_ops, 2347 }, 2348 }, 2349 }; 2350 2351 static struct clk_branch gcc_usb_hs_ahb_clk = { 2352 .halt_reg = 0x0488, 2353 .clkr = { 2354 .enable_reg = 0x0488, 2355 .enable_mask = BIT(0), 2356 .hw.init = &(struct clk_init_data){ 2357 .name = "gcc_usb_hs_ahb_clk", 2358 .parent_hws = (const struct clk_hw*[]){ 2359 &periph_noc_clk_src.clkr.hw, 2360 }, 2361 .num_parents = 1, 2362 .ops = &clk_branch2_ops, 2363 }, 2364 }, 2365 }; 2366 2367 static struct clk_branch gcc_usb_hs_system_clk = { 2368 .halt_reg = 0x0484, 2369 .clkr = { 2370 .enable_reg = 0x0484, 2371 .enable_mask = BIT(0), 2372 .hw.init = &(struct clk_init_data){ 2373 .name = "gcc_usb_hs_system_clk", 2374 .parent_hws = (const struct clk_hw*[]){ 2375 &usb_hs_system_clk_src.clkr.hw, 2376 }, 2377 .num_parents = 1, 2378 .flags = CLK_SET_RATE_PARENT, 2379 .ops = &clk_branch2_ops, 2380 }, 2381 }, 2382 }; 2383 2384 static struct clk_branch gcc_usb_hsic_ahb_clk = { 2385 .halt_reg = 0x0408, 2386 .clkr = { 2387 .enable_reg = 0x0408, 2388 .enable_mask = BIT(0), 2389 .hw.init = &(struct clk_init_data){ 2390 .name = "gcc_usb_hsic_ahb_clk", 2391 .parent_hws = (const struct clk_hw*[]){ 2392 &periph_noc_clk_src.clkr.hw, 2393 }, 2394 .num_parents = 1, 2395 .ops = &clk_branch2_ops, 2396 }, 2397 }, 2398 }; 2399 2400 static struct clk_branch gcc_usb_hsic_clk = { 2401 .halt_reg = 0x0410, 2402 .clkr = { 2403 .enable_reg = 0x0410, 2404 .enable_mask = BIT(0), 2405 .hw.init = &(struct clk_init_data){ 2406 .name = "gcc_usb_hsic_clk", 2407 .parent_hws = (const struct clk_hw*[]){ 2408 &usb_hsic_clk_src.clkr.hw, 2409 }, 2410 .num_parents = 1, 2411 .flags = CLK_SET_RATE_PARENT, 2412 .ops = &clk_branch2_ops, 2413 }, 2414 }, 2415 }; 2416 2417 static struct clk_branch gcc_usb_hsic_io_cal_clk = { 2418 .halt_reg = 0x0414, 2419 .clkr = { 2420 .enable_reg = 0x0414, 2421 .enable_mask = BIT(0), 2422 .hw.init = &(struct clk_init_data){ 2423 .name = "gcc_usb_hsic_io_cal_clk", 2424 .parent_hws = (const struct clk_hw*[]){ 2425 &usb_hsic_io_cal_clk_src.clkr.hw, 2426 }, 2427 .num_parents = 1, 2428 .flags = CLK_SET_RATE_PARENT, 2429 .ops = &clk_branch2_ops, 2430 }, 2431 }, 2432 }; 2433 2434 static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = { 2435 .halt_reg = 0x0418, 2436 .clkr = { 2437 .enable_reg = 0x0418, 2438 .enable_mask = BIT(0), 2439 .hw.init = &(struct clk_init_data){ 2440 .name = "gcc_usb_hsic_io_cal_sleep_clk", 2441 .parent_data = &(const struct clk_parent_data){ 2442 .fw_name = "sleep_clk", .name = "sleep_clk", 2443 }, 2444 .num_parents = 1, 2445 .ops = &clk_branch2_ops, 2446 }, 2447 }, 2448 }; 2449 2450 static struct clk_branch gcc_usb_hsic_system_clk = { 2451 .halt_reg = 0x040c, 2452 .clkr = { 2453 .enable_reg = 0x040c, 2454 .enable_mask = BIT(0), 2455 .hw.init = &(struct clk_init_data){ 2456 .name = "gcc_usb_hsic_system_clk", 2457 .parent_hws = (const struct clk_hw*[]){ 2458 &usb_hsic_system_clk_src.clkr.hw, 2459 }, 2460 .num_parents = 1, 2461 .flags = CLK_SET_RATE_PARENT, 2462 .ops = &clk_branch2_ops, 2463 }, 2464 }, 2465 }; 2466 2467 static struct gdsc usb_hs_hsic_gdsc = { 2468 .gdscr = 0x404, 2469 .pd = { 2470 .name = "usb_hs_hsic", 2471 }, 2472 .pwrsts = PWRSTS_OFF_ON, 2473 }; 2474 2475 static struct clk_regmap *gcc_msm8226_clocks[] = { 2476 [GPLL0] = &gpll0.clkr, 2477 [GPLL0_VOTE] = &gpll0_vote, 2478 [GPLL1] = &gpll1.clkr, 2479 [GPLL1_VOTE] = &gpll1_vote, 2480 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, 2481 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, 2482 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, 2483 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2484 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2485 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2486 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2487 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2488 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2489 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2490 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2491 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2492 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2493 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2494 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2495 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2496 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2497 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2498 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 2499 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 2500 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 2501 [CE1_CLK_SRC] = &ce1_clk_src.clkr, 2502 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2503 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2504 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2505 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2506 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2507 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2508 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, 2509 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 2510 [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr, 2511 [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr, 2512 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr, 2513 [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr, 2514 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2515 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2516 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2517 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2518 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2519 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2520 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2521 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2522 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2523 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2524 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2525 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2526 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2527 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2528 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2529 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2530 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 2531 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 2532 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 2533 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2534 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 2535 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 2536 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 2537 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2538 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2539 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2540 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, 2541 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 2542 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 2543 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2544 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2545 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 2546 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2547 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2548 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2549 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2550 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2551 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, 2552 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, 2553 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, 2554 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 2555 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2556 [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr, 2557 [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr, 2558 [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr, 2559 [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, 2560 }; 2561 2562 static const struct qcom_reset_map gcc_msm8226_resets[] = { 2563 [GCC_USB_HS_HSIC_BCR] = { 0x0400 }, 2564 [GCC_USB_HS_BCR] = { 0x0480 }, 2565 [GCC_USB2A_PHY_BCR] = { 0x04a8 }, 2566 }; 2567 2568 static struct gdsc *gcc_msm8226_gdscs[] = { 2569 [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc, 2570 }; 2571 2572 static const struct regmap_config gcc_msm8226_regmap_config = { 2573 .reg_bits = 32, 2574 .reg_stride = 4, 2575 .val_bits = 32, 2576 .max_register = 0x1a80, 2577 .fast_io = true, 2578 }; 2579 2580 static const struct qcom_cc_desc gcc_msm8226_desc = { 2581 .config = &gcc_msm8226_regmap_config, 2582 .clks = gcc_msm8226_clocks, 2583 .num_clks = ARRAY_SIZE(gcc_msm8226_clocks), 2584 .resets = gcc_msm8226_resets, 2585 .num_resets = ARRAY_SIZE(gcc_msm8226_resets), 2586 .gdscs = gcc_msm8226_gdscs, 2587 .num_gdscs = ARRAY_SIZE(gcc_msm8226_gdscs), 2588 }; 2589 2590 static struct clk_regmap *gcc_msm8974_clocks[] = { 2591 [GPLL0] = &gpll0.clkr, 2592 [GPLL0_VOTE] = &gpll0_vote, 2593 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, 2594 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, 2595 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, 2596 [GPLL1] = &gpll1.clkr, 2597 [GPLL1_VOTE] = &gpll1_vote, 2598 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, 2599 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2600 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2601 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2602 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2603 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2604 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2605 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2606 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2607 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2608 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2609 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2610 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2611 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2612 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2613 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, 2614 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, 2615 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, 2616 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, 2617 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, 2618 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, 2619 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, 2620 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, 2621 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, 2622 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, 2623 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, 2624 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, 2625 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, 2626 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, 2627 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, 2628 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, 2629 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, 2630 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, 2631 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, 2632 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr, 2633 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr, 2634 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr, 2635 [CE1_CLK_SRC] = &ce1_clk_src.clkr, 2636 [CE2_CLK_SRC] = &ce2_clk_src.clkr, 2637 [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2638 [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2639 [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2640 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2641 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2642 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2643 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, 2644 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, 2645 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, 2646 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, 2647 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 2648 [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr, 2649 [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr, 2650 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr, 2651 [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr, 2652 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2653 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2654 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2655 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2656 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2657 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2658 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2659 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2660 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2661 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2662 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2663 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2664 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2665 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2666 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2667 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, 2668 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, 2669 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, 2670 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, 2671 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, 2672 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, 2673 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, 2674 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, 2675 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, 2676 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, 2677 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, 2678 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, 2679 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, 2680 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, 2681 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, 2682 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, 2683 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, 2684 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, 2685 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, 2686 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, 2687 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr, 2688 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr, 2689 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr, 2690 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2691 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, 2692 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, 2693 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, 2694 [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr, 2695 [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr, 2696 [GCC_CE2_CLK] = &gcc_ce2_clk.clkr, 2697 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2698 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2699 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2700 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, 2701 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, 2702 [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr, 2703 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 2704 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 2705 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2706 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2707 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2708 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2709 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2710 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2711 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2712 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, 2713 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, 2714 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 2715 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 2716 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, 2717 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, 2718 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, 2719 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, 2720 [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr, 2721 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, 2722 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2723 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2724 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 2725 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2726 [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr, 2727 [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr, 2728 [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr, 2729 [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr, 2730 [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, 2731 [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src, 2732 [GPLL4] = NULL, 2733 [GPLL4_VOTE] = NULL, 2734 [GCC_SDCC1_CDCCAL_SLEEP_CLK] = NULL, 2735 [GCC_SDCC1_CDCCAL_FF_CLK] = NULL, 2736 }; 2737 2738 static const struct qcom_reset_map gcc_msm8974_resets[] = { 2739 [GCC_SYSTEM_NOC_BCR] = { 0x0100 }, 2740 [GCC_CONFIG_NOC_BCR] = { 0x0140 }, 2741 [GCC_PERIPH_NOC_BCR] = { 0x0180 }, 2742 [GCC_IMEM_BCR] = { 0x0200 }, 2743 [GCC_MMSS_BCR] = { 0x0240 }, 2744 [GCC_QDSS_BCR] = { 0x0300 }, 2745 [GCC_USB_30_BCR] = { 0x03c0 }, 2746 [GCC_USB3_PHY_BCR] = { 0x03fc }, 2747 [GCC_USB_HS_HSIC_BCR] = { 0x0400 }, 2748 [GCC_USB_HS_BCR] = { 0x0480 }, 2749 [GCC_USB2A_PHY_BCR] = { 0x04a8 }, 2750 [GCC_USB2B_PHY_BCR] = { 0x04b0 }, 2751 [GCC_SDCC1_BCR] = { 0x04c0 }, 2752 [GCC_SDCC2_BCR] = { 0x0500 }, 2753 [GCC_SDCC3_BCR] = { 0x0540 }, 2754 [GCC_SDCC4_BCR] = { 0x0580 }, 2755 [GCC_BLSP1_BCR] = { 0x05c0 }, 2756 [GCC_BLSP1_QUP1_BCR] = { 0x0640 }, 2757 [GCC_BLSP1_UART1_BCR] = { 0x0680 }, 2758 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 }, 2759 [GCC_BLSP1_UART2_BCR] = { 0x0700 }, 2760 [GCC_BLSP1_QUP3_BCR] = { 0x0740 }, 2761 [GCC_BLSP1_UART3_BCR] = { 0x0780 }, 2762 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 }, 2763 [GCC_BLSP1_UART4_BCR] = { 0x0800 }, 2764 [GCC_BLSP1_QUP5_BCR] = { 0x0840 }, 2765 [GCC_BLSP1_UART5_BCR] = { 0x0880 }, 2766 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 }, 2767 [GCC_BLSP1_UART6_BCR] = { 0x0900 }, 2768 [GCC_BLSP2_BCR] = { 0x0940 }, 2769 [GCC_BLSP2_QUP1_BCR] = { 0x0980 }, 2770 [GCC_BLSP2_UART1_BCR] = { 0x09c0 }, 2771 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 }, 2772 [GCC_BLSP2_UART2_BCR] = { 0x0a40 }, 2773 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 }, 2774 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 }, 2775 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 }, 2776 [GCC_BLSP2_UART4_BCR] = { 0x0b40 }, 2777 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 }, 2778 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 }, 2779 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 }, 2780 [GCC_BLSP2_UART6_BCR] = { 0x0c40 }, 2781 [GCC_PDM_BCR] = { 0x0cc0 }, 2782 [GCC_BAM_DMA_BCR] = { 0x0d40 }, 2783 [GCC_TSIF_BCR] = { 0x0d80 }, 2784 [GCC_TCSR_BCR] = { 0x0dc0 }, 2785 [GCC_BOOT_ROM_BCR] = { 0x0e00 }, 2786 [GCC_MSG_RAM_BCR] = { 0x0e40 }, 2787 [GCC_TLMM_BCR] = { 0x0e80 }, 2788 [GCC_MPM_BCR] = { 0x0ec0 }, 2789 [GCC_SEC_CTRL_BCR] = { 0x0f40 }, 2790 [GCC_SPMI_BCR] = { 0x0fc0 }, 2791 [GCC_SPDM_BCR] = { 0x1000 }, 2792 [GCC_CE1_BCR] = { 0x1040 }, 2793 [GCC_CE2_BCR] = { 0x1080 }, 2794 [GCC_BIMC_BCR] = { 0x1100 }, 2795 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 }, 2796 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 }, 2797 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 }, 2798 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 }, 2799 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 }, 2800 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 }, 2801 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 }, 2802 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 }, 2803 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 }, 2804 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 }, 2805 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 }, 2806 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 }, 2807 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 }, 2808 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 }, 2809 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 }, 2810 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 }, 2811 [GCC_DEHR_BCR] = { 0x1300 }, 2812 [GCC_RBCPR_BCR] = { 0x1380 }, 2813 [GCC_MSS_RESTART] = { 0x1680 }, 2814 [GCC_LPASS_RESTART] = { 0x16c0 }, 2815 [GCC_WCSS_RESTART] = { 0x1700 }, 2816 [GCC_VENUS_RESTART] = { 0x1740 }, 2817 }; 2818 2819 static struct gdsc *gcc_msm8974_gdscs[] = { 2820 [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc, 2821 }; 2822 2823 static const struct regmap_config gcc_msm8974_regmap_config = { 2824 .reg_bits = 32, 2825 .reg_stride = 4, 2826 .val_bits = 32, 2827 .max_register = 0x1fc0, 2828 .fast_io = true, 2829 }; 2830 2831 static const struct qcom_cc_desc gcc_msm8974_desc = { 2832 .config = &gcc_msm8974_regmap_config, 2833 .clks = gcc_msm8974_clocks, 2834 .num_clks = ARRAY_SIZE(gcc_msm8974_clocks), 2835 .resets = gcc_msm8974_resets, 2836 .num_resets = ARRAY_SIZE(gcc_msm8974_resets), 2837 .gdscs = gcc_msm8974_gdscs, 2838 .num_gdscs = ARRAY_SIZE(gcc_msm8974_gdscs), 2839 }; 2840 2841 static const struct of_device_id gcc_msm8974_match_table[] = { 2842 { .compatible = "qcom,gcc-msm8226", .data = &gcc_msm8226_desc }, 2843 { .compatible = "qcom,gcc-msm8974", .data = &gcc_msm8974_desc }, 2844 { .compatible = "qcom,gcc-msm8974pro", .data = &gcc_msm8974_desc }, 2845 { .compatible = "qcom,gcc-msm8974pro-ac", .data = &gcc_msm8974_desc }, 2846 { } 2847 }; 2848 MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table); 2849 2850 static void msm8226_clock_override(void) 2851 { 2852 ce1_clk_src.freq_tbl = ftbl_gcc_ce1_clk_msm8226; 2853 gp1_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226; 2854 gp2_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226; 2855 gp3_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226; 2856 } 2857 2858 static void msm8974_pro_clock_override(void) 2859 { 2860 sdcc1_apps_clk_src_init.parent_data = gcc_xo_gpll0_gpll4; 2861 sdcc1_apps_clk_src_init.num_parents = 3; 2862 sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro; 2863 sdcc1_apps_clk_src.parent_map = gcc_xo_gpll0_gpll4_map; 2864 2865 gcc_msm8974_clocks[GPLL4] = &gpll4.clkr; 2866 gcc_msm8974_clocks[GPLL4_VOTE] = &gpll4_vote; 2867 gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_SLEEP_CLK] = 2868 &gcc_sdcc1_cdccal_sleep_clk.clkr; 2869 gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_FF_CLK] = 2870 &gcc_sdcc1_cdccal_ff_clk.clkr; 2871 } 2872 2873 static int gcc_msm8974_probe(struct platform_device *pdev) 2874 { 2875 int ret; 2876 struct device *dev = &pdev->dev; 2877 const void *data = device_get_match_data(dev); 2878 2879 if (!of_device_is_compatible(dev->of_node, "qcom,gcc-msm8974")) { 2880 if (data == &gcc_msm8226_desc) 2881 msm8226_clock_override(); 2882 else 2883 msm8974_pro_clock_override(); 2884 } 2885 2886 ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000); 2887 if (ret) 2888 return ret; 2889 2890 ret = qcom_cc_register_sleep_clk(dev); 2891 if (ret) 2892 return ret; 2893 2894 return qcom_cc_probe(pdev, &gcc_msm8974_desc); 2895 } 2896 2897 static struct platform_driver gcc_msm8974_driver = { 2898 .probe = gcc_msm8974_probe, 2899 .driver = { 2900 .name = "gcc-msm8974", 2901 .of_match_table = gcc_msm8974_match_table, 2902 }, 2903 }; 2904 2905 static int __init gcc_msm8974_init(void) 2906 { 2907 return platform_driver_register(&gcc_msm8974_driver); 2908 } 2909 core_initcall(gcc_msm8974_init); 2910 2911 static void __exit gcc_msm8974_exit(void) 2912 { 2913 platform_driver_unregister(&gcc_msm8974_driver); 2914 } 2915 module_exit(gcc_msm8974_exit); 2916 2917 MODULE_DESCRIPTION("QCOM GCC MSM8974 Driver"); 2918 MODULE_LICENSE("GPL v2"); 2919 MODULE_ALIAS("platform:gcc-msm8974"); 2920