1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023, Linaro Ltd. 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/err.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 #include <linux/pm_runtime.h> 14 15 #include <dt-bindings/clock/qcom,sm8550-dispcc.h> 16 17 #include "common.h" 18 #include "clk-alpha-pll.h" 19 #include "clk-branch.h" 20 #include "clk-pll.h" 21 #include "clk-rcg.h" 22 #include "clk-regmap.h" 23 #include "clk-regmap-divider.h" 24 #include "clk-regmap-mux.h" 25 #include "reset.h" 26 #include "gdsc.h" 27 28 /* Need to match the order of clocks in DT binding */ 29 enum { 30 DT_BI_TCXO, 31 DT_BI_TCXO_AO, 32 DT_AHB_CLK, 33 DT_SLEEP_CLK, 34 35 DT_DSI0_PHY_PLL_OUT_BYTECLK, 36 DT_DSI0_PHY_PLL_OUT_DSICLK, 37 DT_DSI1_PHY_PLL_OUT_BYTECLK, 38 DT_DSI1_PHY_PLL_OUT_DSICLK, 39 40 DT_DP0_PHY_PLL_LINK_CLK, 41 DT_DP0_PHY_PLL_VCO_DIV_CLK, 42 DT_DP1_PHY_PLL_LINK_CLK, 43 DT_DP1_PHY_PLL_VCO_DIV_CLK, 44 DT_DP2_PHY_PLL_LINK_CLK, 45 DT_DP2_PHY_PLL_VCO_DIV_CLK, 46 DT_DP3_PHY_PLL_LINK_CLK, 47 DT_DP3_PHY_PLL_VCO_DIV_CLK, 48 }; 49 50 #define DISP_CC_MISC_CMD 0xF000 51 52 enum { 53 P_BI_TCXO, 54 P_DISP_CC_PLL0_OUT_MAIN, 55 P_DISP_CC_PLL1_OUT_EVEN, 56 P_DISP_CC_PLL1_OUT_MAIN, 57 P_DP0_PHY_PLL_LINK_CLK, 58 P_DP0_PHY_PLL_VCO_DIV_CLK, 59 P_DP1_PHY_PLL_LINK_CLK, 60 P_DP1_PHY_PLL_VCO_DIV_CLK, 61 P_DP2_PHY_PLL_LINK_CLK, 62 P_DP2_PHY_PLL_VCO_DIV_CLK, 63 P_DP3_PHY_PLL_LINK_CLK, 64 P_DP3_PHY_PLL_VCO_DIV_CLK, 65 P_DSI0_PHY_PLL_OUT_BYTECLK, 66 P_DSI0_PHY_PLL_OUT_DSICLK, 67 P_DSI1_PHY_PLL_OUT_BYTECLK, 68 P_DSI1_PHY_PLL_OUT_DSICLK, 69 P_SLEEP_CLK, 70 }; 71 72 static struct pll_vco lucid_ole_vco[] = { 73 { 249600000, 2000000000, 0 }, 74 }; 75 76 static struct alpha_pll_config disp_cc_pll0_config = { 77 .l = 0xd, 78 .alpha = 0x6492, 79 .config_ctl_val = 0x20485699, 80 .config_ctl_hi_val = 0x00182261, 81 .config_ctl_hi1_val = 0x82aa299c, 82 .test_ctl_val = 0x00000000, 83 .test_ctl_hi_val = 0x00000003, 84 .test_ctl_hi1_val = 0x00009000, 85 .test_ctl_hi2_val = 0x00000034, 86 .user_ctl_val = 0x00000000, 87 .user_ctl_hi_val = 0x00000005, 88 }; 89 90 static struct clk_alpha_pll disp_cc_pll0 = { 91 .offset = 0x0, 92 .vco_table = lucid_ole_vco, 93 .num_vco = ARRAY_SIZE(lucid_ole_vco), 94 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 95 .clkr = { 96 .hw.init = &(const struct clk_init_data) { 97 .name = "disp_cc_pll0", 98 .parent_data = &(const struct clk_parent_data) { 99 .index = DT_BI_TCXO, 100 }, 101 .num_parents = 1, 102 .ops = &clk_alpha_pll_reset_lucid_ole_ops, 103 }, 104 }, 105 }; 106 107 static struct alpha_pll_config disp_cc_pll1_config = { 108 .l = 0x1f, 109 .alpha = 0x4000, 110 .config_ctl_val = 0x20485699, 111 .config_ctl_hi_val = 0x00182261, 112 .config_ctl_hi1_val = 0x82aa299c, 113 .test_ctl_val = 0x00000000, 114 .test_ctl_hi_val = 0x00000003, 115 .test_ctl_hi1_val = 0x00009000, 116 .test_ctl_hi2_val = 0x00000034, 117 .user_ctl_val = 0x00000000, 118 .user_ctl_hi_val = 0x00000005, 119 }; 120 121 static struct clk_alpha_pll disp_cc_pll1 = { 122 .offset = 0x1000, 123 .vco_table = lucid_ole_vco, 124 .num_vco = ARRAY_SIZE(lucid_ole_vco), 125 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 126 .clkr = { 127 .hw.init = &(const struct clk_init_data) { 128 .name = "disp_cc_pll1", 129 .parent_data = &(const struct clk_parent_data) { 130 .index = DT_BI_TCXO, 131 }, 132 .num_parents = 1, 133 .ops = &clk_alpha_pll_reset_lucid_ole_ops, 134 }, 135 }, 136 }; 137 138 static const struct parent_map disp_cc_parent_map_0[] = { 139 { P_BI_TCXO, 0 }, 140 }; 141 142 static const struct clk_parent_data disp_cc_parent_data_0[] = { 143 { .index = DT_BI_TCXO }, 144 }; 145 146 static const struct clk_parent_data disp_cc_parent_data_0_ao[] = { 147 { .index = DT_BI_TCXO_AO }, 148 }; 149 150 static const struct parent_map disp_cc_parent_map_1[] = { 151 { P_BI_TCXO, 0 }, 152 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 153 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 154 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 155 }; 156 157 static const struct clk_parent_data disp_cc_parent_data_1[] = { 158 { .index = DT_BI_TCXO }, 159 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 160 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 161 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 162 }; 163 164 static const struct parent_map disp_cc_parent_map_2[] = { 165 { P_BI_TCXO, 0 }, 166 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 167 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 168 { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 169 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 170 }; 171 172 static const struct clk_parent_data disp_cc_parent_data_2[] = { 173 { .index = DT_BI_TCXO }, 174 { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 175 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 176 { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 177 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 178 }; 179 180 static const struct parent_map disp_cc_parent_map_3[] = { 181 { P_BI_TCXO, 0 }, 182 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 183 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 184 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 185 }; 186 187 static const struct clk_parent_data disp_cc_parent_data_3[] = { 188 { .index = DT_BI_TCXO }, 189 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 190 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 191 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 192 }; 193 194 static const struct parent_map disp_cc_parent_map_4[] = { 195 { P_BI_TCXO, 0 }, 196 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 197 { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 198 { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 199 { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 200 { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 201 }; 202 203 static const struct clk_parent_data disp_cc_parent_data_4[] = { 204 { .index = DT_BI_TCXO }, 205 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 206 { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 207 { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 208 { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 209 { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 210 }; 211 212 static const struct parent_map disp_cc_parent_map_5[] = { 213 { P_BI_TCXO, 0 }, 214 { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 215 { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 216 }; 217 218 static const struct clk_parent_data disp_cc_parent_data_5[] = { 219 { .index = DT_BI_TCXO }, 220 { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 221 { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 222 }; 223 224 static const struct parent_map disp_cc_parent_map_6[] = { 225 { P_BI_TCXO, 0 }, 226 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 227 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 228 }; 229 230 static const struct clk_parent_data disp_cc_parent_data_6[] = { 231 { .index = DT_BI_TCXO }, 232 { .hw = &disp_cc_pll1.clkr.hw }, 233 { .hw = &disp_cc_pll1.clkr.hw }, 234 }; 235 236 static const struct parent_map disp_cc_parent_map_7[] = { 237 { P_BI_TCXO, 0 }, 238 { P_DP0_PHY_PLL_LINK_CLK, 1 }, 239 { P_DP1_PHY_PLL_LINK_CLK, 2 }, 240 { P_DP2_PHY_PLL_LINK_CLK, 3 }, 241 { P_DP3_PHY_PLL_LINK_CLK, 4 }, 242 }; 243 244 static const struct clk_parent_data disp_cc_parent_data_7[] = { 245 { .index = DT_BI_TCXO }, 246 { .index = DT_DP0_PHY_PLL_LINK_CLK }, 247 { .index = DT_DP1_PHY_PLL_LINK_CLK }, 248 { .index = DT_DP2_PHY_PLL_LINK_CLK }, 249 { .index = DT_DP3_PHY_PLL_LINK_CLK }, 250 }; 251 252 static const struct parent_map disp_cc_parent_map_8[] = { 253 { P_BI_TCXO, 0 }, 254 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 255 { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 256 { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 257 }; 258 259 static const struct clk_parent_data disp_cc_parent_data_8[] = { 260 { .index = DT_BI_TCXO }, 261 { .hw = &disp_cc_pll0.clkr.hw }, 262 { .hw = &disp_cc_pll1.clkr.hw }, 263 { .hw = &disp_cc_pll1.clkr.hw }, 264 }; 265 266 static const struct parent_map disp_cc_parent_map_9[] = { 267 { P_SLEEP_CLK, 0 }, 268 }; 269 270 static const struct clk_parent_data disp_cc_parent_data_9[] = { 271 { .index = DT_SLEEP_CLK }, 272 }; 273 274 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 275 F(19200000, P_BI_TCXO, 1, 0, 0), 276 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), 277 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), 278 { } 279 }; 280 281 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 282 .cmd_rcgr = 0x82e8, 283 .mnd_width = 0, 284 .hid_width = 5, 285 .parent_map = disp_cc_parent_map_6, 286 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 287 .clkr.hw.init = &(const struct clk_init_data) { 288 .name = "disp_cc_mdss_ahb_clk_src", 289 .parent_data = disp_cc_parent_data_6, 290 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 291 .flags = CLK_SET_RATE_PARENT, 292 .ops = &clk_rcg2_shared_ops, 293 }, 294 }; 295 296 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { 297 F(19200000, P_BI_TCXO, 1, 0, 0), 298 { } 299 }; 300 301 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 302 .cmd_rcgr = 0x8108, 303 .mnd_width = 0, 304 .hid_width = 5, 305 .parent_map = disp_cc_parent_map_2, 306 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 307 .clkr.hw.init = &(const struct clk_init_data) { 308 .name = "disp_cc_mdss_byte0_clk_src", 309 .parent_data = disp_cc_parent_data_2, 310 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 311 .flags = CLK_SET_RATE_PARENT, 312 .ops = &clk_byte2_ops, 313 }, 314 }; 315 316 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 317 .cmd_rcgr = 0x8124, 318 .mnd_width = 0, 319 .hid_width = 5, 320 .parent_map = disp_cc_parent_map_2, 321 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 322 .clkr.hw.init = &(const struct clk_init_data) { 323 .name = "disp_cc_mdss_byte1_clk_src", 324 .parent_data = disp_cc_parent_data_2, 325 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 326 .flags = CLK_SET_RATE_PARENT, 327 .ops = &clk_byte2_ops, 328 }, 329 }; 330 331 static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { 332 .cmd_rcgr = 0x81bc, 333 .mnd_width = 0, 334 .hid_width = 5, 335 .parent_map = disp_cc_parent_map_0, 336 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 337 .clkr.hw.init = &(const struct clk_init_data) { 338 .name = "disp_cc_mdss_dptx0_aux_clk_src", 339 .parent_data = disp_cc_parent_data_0, 340 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 341 .flags = CLK_SET_RATE_PARENT, 342 .ops = &clk_rcg2_ops, 343 }, 344 }; 345 346 static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { 347 .cmd_rcgr = 0x8170, 348 .mnd_width = 0, 349 .hid_width = 5, 350 .parent_map = disp_cc_parent_map_7, 351 .clkr.hw.init = &(const struct clk_init_data) { 352 .name = "disp_cc_mdss_dptx0_link_clk_src", 353 .parent_data = disp_cc_parent_data_7, 354 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 355 .flags = CLK_SET_RATE_PARENT, 356 .ops = &clk_byte2_ops, 357 }, 358 }; 359 360 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { 361 .cmd_rcgr = 0x818c, 362 .mnd_width = 16, 363 .hid_width = 5, 364 .parent_map = disp_cc_parent_map_4, 365 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 366 .clkr.hw.init = &(const struct clk_init_data) { 367 .name = "disp_cc_mdss_dptx0_pixel0_clk_src", 368 .parent_data = disp_cc_parent_data_4, 369 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 370 .flags = CLK_SET_RATE_PARENT, 371 .ops = &clk_dp_ops, 372 }, 373 }; 374 375 static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { 376 .cmd_rcgr = 0x81a4, 377 .mnd_width = 16, 378 .hid_width = 5, 379 .parent_map = disp_cc_parent_map_4, 380 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 381 .clkr.hw.init = &(const struct clk_init_data) { 382 .name = "disp_cc_mdss_dptx0_pixel1_clk_src", 383 .parent_data = disp_cc_parent_data_4, 384 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 385 .flags = CLK_SET_RATE_PARENT, 386 .ops = &clk_dp_ops, 387 }, 388 }; 389 390 static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { 391 .cmd_rcgr = 0x8220, 392 .mnd_width = 0, 393 .hid_width = 5, 394 .parent_map = disp_cc_parent_map_0, 395 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 396 .clkr.hw.init = &(const struct clk_init_data) { 397 .name = "disp_cc_mdss_dptx1_aux_clk_src", 398 .parent_data = disp_cc_parent_data_0, 399 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 400 .flags = CLK_SET_RATE_PARENT, 401 .ops = &clk_rcg2_ops, 402 }, 403 }; 404 405 static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { 406 .cmd_rcgr = 0x8204, 407 .mnd_width = 0, 408 .hid_width = 5, 409 .parent_map = disp_cc_parent_map_3, 410 .clkr.hw.init = &(const struct clk_init_data) { 411 .name = "disp_cc_mdss_dptx1_link_clk_src", 412 .parent_data = disp_cc_parent_data_3, 413 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 414 .flags = CLK_SET_RATE_PARENT, 415 .ops = &clk_byte2_ops, 416 }, 417 }; 418 419 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = { 420 .cmd_rcgr = 0x81d4, 421 .mnd_width = 16, 422 .hid_width = 5, 423 .parent_map = disp_cc_parent_map_1, 424 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 425 .clkr.hw.init = &(const struct clk_init_data) { 426 .name = "disp_cc_mdss_dptx1_pixel0_clk_src", 427 .parent_data = disp_cc_parent_data_1, 428 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 429 .flags = CLK_SET_RATE_PARENT, 430 .ops = &clk_dp_ops, 431 }, 432 }; 433 434 static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = { 435 .cmd_rcgr = 0x81ec, 436 .mnd_width = 16, 437 .hid_width = 5, 438 .parent_map = disp_cc_parent_map_1, 439 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 440 .clkr.hw.init = &(const struct clk_init_data) { 441 .name = "disp_cc_mdss_dptx1_pixel1_clk_src", 442 .parent_data = disp_cc_parent_data_1, 443 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 444 .flags = CLK_SET_RATE_PARENT, 445 .ops = &clk_dp_ops, 446 }, 447 }; 448 449 static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { 450 .cmd_rcgr = 0x8284, 451 .mnd_width = 0, 452 .hid_width = 5, 453 .parent_map = disp_cc_parent_map_0, 454 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 455 .clkr.hw.init = &(const struct clk_init_data) { 456 .name = "disp_cc_mdss_dptx2_aux_clk_src", 457 .parent_data = disp_cc_parent_data_0, 458 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 459 .flags = CLK_SET_RATE_PARENT, 460 .ops = &clk_rcg2_ops, 461 }, 462 }; 463 464 static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { 465 .cmd_rcgr = 0x8238, 466 .mnd_width = 0, 467 .hid_width = 5, 468 .parent_map = disp_cc_parent_map_3, 469 .clkr.hw.init = &(const struct clk_init_data) { 470 .name = "disp_cc_mdss_dptx2_link_clk_src", 471 .parent_data = disp_cc_parent_data_3, 472 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 473 .flags = CLK_SET_RATE_PARENT, 474 .ops = &clk_byte2_ops, 475 }, 476 }; 477 478 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = { 479 .cmd_rcgr = 0x8254, 480 .mnd_width = 16, 481 .hid_width = 5, 482 .parent_map = disp_cc_parent_map_1, 483 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 484 .clkr.hw.init = &(const struct clk_init_data) { 485 .name = "disp_cc_mdss_dptx2_pixel0_clk_src", 486 .parent_data = disp_cc_parent_data_1, 487 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 488 .flags = CLK_SET_RATE_PARENT, 489 .ops = &clk_dp_ops, 490 }, 491 }; 492 493 static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = { 494 .cmd_rcgr = 0x826c, 495 .mnd_width = 16, 496 .hid_width = 5, 497 .parent_map = disp_cc_parent_map_1, 498 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 499 .clkr.hw.init = &(const struct clk_init_data) { 500 .name = "disp_cc_mdss_dptx2_pixel1_clk_src", 501 .parent_data = disp_cc_parent_data_1, 502 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 503 .flags = CLK_SET_RATE_PARENT, 504 .ops = &clk_dp_ops, 505 }, 506 }; 507 508 static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { 509 .cmd_rcgr = 0x82d0, 510 .mnd_width = 0, 511 .hid_width = 5, 512 .parent_map = disp_cc_parent_map_0, 513 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 514 .clkr.hw.init = &(const struct clk_init_data) { 515 .name = "disp_cc_mdss_dptx3_aux_clk_src", 516 .parent_data = disp_cc_parent_data_0, 517 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 518 .flags = CLK_SET_RATE_PARENT, 519 .ops = &clk_rcg2_ops, 520 }, 521 }; 522 523 static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { 524 .cmd_rcgr = 0x82b4, 525 .mnd_width = 0, 526 .hid_width = 5, 527 .parent_map = disp_cc_parent_map_3, 528 .clkr.hw.init = &(const struct clk_init_data) { 529 .name = "disp_cc_mdss_dptx3_link_clk_src", 530 .parent_data = disp_cc_parent_data_3, 531 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 532 .flags = CLK_SET_RATE_PARENT, 533 .ops = &clk_byte2_ops, 534 }, 535 }; 536 537 static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = { 538 .cmd_rcgr = 0x829c, 539 .mnd_width = 16, 540 .hid_width = 5, 541 .parent_map = disp_cc_parent_map_1, 542 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 543 .clkr.hw.init = &(const struct clk_init_data) { 544 .name = "disp_cc_mdss_dptx3_pixel0_clk_src", 545 .parent_data = disp_cc_parent_data_1, 546 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 547 .flags = CLK_SET_RATE_PARENT, 548 .ops = &clk_dp_ops, 549 }, 550 }; 551 552 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 553 .cmd_rcgr = 0x8140, 554 .mnd_width = 0, 555 .hid_width = 5, 556 .parent_map = disp_cc_parent_map_5, 557 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 558 .clkr.hw.init = &(const struct clk_init_data) { 559 .name = "disp_cc_mdss_esc0_clk_src", 560 .parent_data = disp_cc_parent_data_5, 561 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 562 .flags = CLK_SET_RATE_PARENT, 563 .ops = &clk_rcg2_shared_ops, 564 }, 565 }; 566 567 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 568 .cmd_rcgr = 0x8158, 569 .mnd_width = 0, 570 .hid_width = 5, 571 .parent_map = disp_cc_parent_map_5, 572 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 573 .clkr.hw.init = &(const struct clk_init_data) { 574 .name = "disp_cc_mdss_esc1_clk_src", 575 .parent_data = disp_cc_parent_data_5, 576 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 577 .flags = CLK_SET_RATE_PARENT, 578 .ops = &clk_rcg2_shared_ops, 579 }, 580 }; 581 582 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 583 F(19200000, P_BI_TCXO, 1, 0, 0), 584 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 585 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 586 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 587 F(172000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 588 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 589 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 590 F(375000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 591 F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 592 { } 593 }; 594 595 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sar2130p[] = { 596 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 597 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 598 F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 599 { } 600 }; 601 602 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src_sm8650[] = { 603 F(19200000, P_BI_TCXO, 1, 0, 0), 604 F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 605 F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 606 F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 607 F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 608 F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 609 F(402000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 610 F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 611 { } 612 }; 613 614 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 615 .cmd_rcgr = 0x80d8, 616 .mnd_width = 0, 617 .hid_width = 5, 618 .parent_map = disp_cc_parent_map_8, 619 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 620 .clkr.hw.init = &(const struct clk_init_data) { 621 .name = "disp_cc_mdss_mdp_clk_src", 622 .parent_data = disp_cc_parent_data_8, 623 .num_parents = ARRAY_SIZE(disp_cc_parent_data_8), 624 .flags = CLK_SET_RATE_PARENT, 625 .ops = &clk_rcg2_shared_ops, 626 }, 627 }; 628 629 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 630 .cmd_rcgr = 0x80a8, 631 .mnd_width = 8, 632 .hid_width = 5, 633 .parent_map = disp_cc_parent_map_2, 634 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 635 .clkr.hw.init = &(const struct clk_init_data) { 636 .name = "disp_cc_mdss_pclk0_clk_src", 637 .parent_data = disp_cc_parent_data_2, 638 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 639 .flags = CLK_SET_RATE_PARENT, 640 .ops = &clk_pixel_ops, 641 }, 642 }; 643 644 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 645 .cmd_rcgr = 0x80c0, 646 .mnd_width = 8, 647 .hid_width = 5, 648 .parent_map = disp_cc_parent_map_2, 649 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 650 .clkr.hw.init = &(const struct clk_init_data) { 651 .name = "disp_cc_mdss_pclk1_clk_src", 652 .parent_data = disp_cc_parent_data_2, 653 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 654 .flags = CLK_SET_RATE_PARENT, 655 .ops = &clk_pixel_ops, 656 }, 657 }; 658 659 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 660 .cmd_rcgr = 0x80f0, 661 .mnd_width = 0, 662 .hid_width = 5, 663 .parent_map = disp_cc_parent_map_0, 664 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 665 .clkr.hw.init = &(const struct clk_init_data) { 666 .name = "disp_cc_mdss_vsync_clk_src", 667 .parent_data = disp_cc_parent_data_0, 668 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 669 .flags = CLK_SET_RATE_PARENT, 670 .ops = &clk_rcg2_ops, 671 }, 672 }; 673 674 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { 675 F(32000, P_SLEEP_CLK, 1, 0, 0), 676 { } 677 }; 678 679 static struct clk_rcg2 disp_cc_sleep_clk_src = { 680 .cmd_rcgr = 0xe05c, 681 .mnd_width = 0, 682 .hid_width = 5, 683 .parent_map = disp_cc_parent_map_9, 684 .freq_tbl = ftbl_disp_cc_sleep_clk_src, 685 .clkr.hw.init = &(const struct clk_init_data) { 686 .name = "disp_cc_sleep_clk_src", 687 .parent_data = disp_cc_parent_data_9, 688 .num_parents = ARRAY_SIZE(disp_cc_parent_data_9), 689 .flags = CLK_SET_RATE_PARENT, 690 .ops = &clk_rcg2_ops, 691 }, 692 }; 693 694 static struct clk_rcg2 disp_cc_xo_clk_src = { 695 .cmd_rcgr = 0xe03c, 696 .mnd_width = 0, 697 .hid_width = 5, 698 .parent_map = disp_cc_parent_map_0, 699 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 700 .clkr.hw.init = &(const struct clk_init_data) { 701 .name = "disp_cc_xo_clk_src", 702 .parent_data = disp_cc_parent_data_0_ao, 703 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao), 704 .flags = CLK_SET_RATE_PARENT, 705 .ops = &clk_rcg2_ops, 706 }, 707 }; 708 709 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 710 .reg = 0x8120, 711 .shift = 0, 712 .width = 4, 713 .clkr.hw.init = &(const struct clk_init_data) { 714 .name = "disp_cc_mdss_byte0_div_clk_src", 715 .parent_hws = (const struct clk_hw*[]) { 716 &disp_cc_mdss_byte0_clk_src.clkr.hw, 717 }, 718 .num_parents = 1, 719 .ops = &clk_regmap_div_ops, 720 }, 721 }; 722 723 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 724 .reg = 0x813c, 725 .shift = 0, 726 .width = 4, 727 .clkr.hw.init = &(const struct clk_init_data) { 728 .name = "disp_cc_mdss_byte1_div_clk_src", 729 .parent_hws = (const struct clk_hw*[]) { 730 &disp_cc_mdss_byte1_clk_src.clkr.hw, 731 }, 732 .num_parents = 1, 733 .ops = &clk_regmap_div_ops, 734 }, 735 }; 736 737 static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { 738 .reg = 0x8188, 739 .shift = 0, 740 .width = 4, 741 .clkr.hw.init = &(const struct clk_init_data) { 742 .name = "disp_cc_mdss_dptx0_link_div_clk_src", 743 .parent_hws = (const struct clk_hw*[]) { 744 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 745 }, 746 .num_parents = 1, 747 .flags = CLK_SET_RATE_PARENT, 748 .ops = &clk_regmap_div_ro_ops, 749 }, 750 }; 751 752 static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { 753 .reg = 0x821c, 754 .shift = 0, 755 .width = 4, 756 .clkr.hw.init = &(const struct clk_init_data) { 757 .name = "disp_cc_mdss_dptx1_link_div_clk_src", 758 .parent_hws = (const struct clk_hw*[]) { 759 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 760 }, 761 .num_parents = 1, 762 .flags = CLK_SET_RATE_PARENT, 763 .ops = &clk_regmap_div_ro_ops, 764 }, 765 }; 766 767 static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { 768 .reg = 0x8250, 769 .shift = 0, 770 .width = 4, 771 .clkr.hw.init = &(const struct clk_init_data) { 772 .name = "disp_cc_mdss_dptx2_link_div_clk_src", 773 .parent_hws = (const struct clk_hw*[]) { 774 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 775 }, 776 .num_parents = 1, 777 .flags = CLK_SET_RATE_PARENT, 778 .ops = &clk_regmap_div_ro_ops, 779 }, 780 }; 781 782 static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { 783 .reg = 0x82cc, 784 .shift = 0, 785 .width = 4, 786 .clkr.hw.init = &(const struct clk_init_data) { 787 .name = "disp_cc_mdss_dptx3_link_div_clk_src", 788 .parent_hws = (const struct clk_hw*[]) { 789 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 790 }, 791 .num_parents = 1, 792 .flags = CLK_SET_RATE_PARENT, 793 .ops = &clk_regmap_div_ro_ops, 794 }, 795 }; 796 797 static struct clk_branch disp_cc_mdss_accu_clk = { 798 .halt_reg = 0xe058, 799 .halt_check = BRANCH_HALT_VOTED, 800 .clkr = { 801 .enable_reg = 0xe058, 802 .enable_mask = BIT(0), 803 .hw.init = &(const struct clk_init_data) { 804 .name = "disp_cc_mdss_accu_clk", 805 .parent_hws = (const struct clk_hw*[]) { 806 &disp_cc_xo_clk_src.clkr.hw, 807 }, 808 .num_parents = 1, 809 .flags = CLK_SET_RATE_PARENT, 810 .ops = &clk_branch2_ops, 811 }, 812 }, 813 }; 814 815 static struct clk_branch disp_cc_mdss_ahb1_clk = { 816 .halt_reg = 0xa020, 817 .halt_check = BRANCH_HALT, 818 .clkr = { 819 .enable_reg = 0xa020, 820 .enable_mask = BIT(0), 821 .hw.init = &(const struct clk_init_data) { 822 .name = "disp_cc_mdss_ahb1_clk", 823 .parent_hws = (const struct clk_hw*[]) { 824 &disp_cc_mdss_ahb_clk_src.clkr.hw, 825 }, 826 .num_parents = 1, 827 .flags = CLK_SET_RATE_PARENT, 828 .ops = &clk_branch2_ops, 829 }, 830 }, 831 }; 832 833 static struct clk_branch disp_cc_mdss_ahb_clk = { 834 .halt_reg = 0x80a4, 835 .halt_check = BRANCH_HALT, 836 .clkr = { 837 .enable_reg = 0x80a4, 838 .enable_mask = BIT(0), 839 .hw.init = &(const struct clk_init_data) { 840 .name = "disp_cc_mdss_ahb_clk", 841 .parent_hws = (const struct clk_hw*[]) { 842 &disp_cc_mdss_ahb_clk_src.clkr.hw, 843 }, 844 .num_parents = 1, 845 .flags = CLK_SET_RATE_PARENT, 846 .ops = &clk_branch2_ops, 847 }, 848 }, 849 }; 850 851 static struct clk_branch disp_cc_mdss_byte0_clk = { 852 .halt_reg = 0x8028, 853 .halt_check = BRANCH_HALT, 854 .clkr = { 855 .enable_reg = 0x8028, 856 .enable_mask = BIT(0), 857 .hw.init = &(const struct clk_init_data) { 858 .name = "disp_cc_mdss_byte0_clk", 859 .parent_hws = (const struct clk_hw*[]) { 860 &disp_cc_mdss_byte0_clk_src.clkr.hw, 861 }, 862 .num_parents = 1, 863 .flags = CLK_SET_RATE_PARENT, 864 .ops = &clk_branch2_ops, 865 }, 866 }, 867 }; 868 869 static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 870 .halt_reg = 0x802c, 871 .halt_check = BRANCH_HALT, 872 .clkr = { 873 .enable_reg = 0x802c, 874 .enable_mask = BIT(0), 875 .hw.init = &(const struct clk_init_data) { 876 .name = "disp_cc_mdss_byte0_intf_clk", 877 .parent_hws = (const struct clk_hw*[]) { 878 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 879 }, 880 .num_parents = 1, 881 .flags = CLK_SET_RATE_PARENT, 882 .ops = &clk_branch2_ops, 883 }, 884 }, 885 }; 886 887 static struct clk_branch disp_cc_mdss_byte1_clk = { 888 .halt_reg = 0x8030, 889 .halt_check = BRANCH_HALT, 890 .clkr = { 891 .enable_reg = 0x8030, 892 .enable_mask = BIT(0), 893 .hw.init = &(const struct clk_init_data) { 894 .name = "disp_cc_mdss_byte1_clk", 895 .parent_hws = (const struct clk_hw*[]) { 896 &disp_cc_mdss_byte1_clk_src.clkr.hw, 897 }, 898 .num_parents = 1, 899 .flags = CLK_SET_RATE_PARENT, 900 .ops = &clk_branch2_ops, 901 }, 902 }, 903 }; 904 905 static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 906 .halt_reg = 0x8034, 907 .halt_check = BRANCH_HALT, 908 .clkr = { 909 .enable_reg = 0x8034, 910 .enable_mask = BIT(0), 911 .hw.init = &(const struct clk_init_data) { 912 .name = "disp_cc_mdss_byte1_intf_clk", 913 .parent_hws = (const struct clk_hw*[]) { 914 &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 915 }, 916 .num_parents = 1, 917 .flags = CLK_SET_RATE_PARENT, 918 .ops = &clk_branch2_ops, 919 }, 920 }, 921 }; 922 923 static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { 924 .halt_reg = 0x8058, 925 .halt_check = BRANCH_HALT, 926 .clkr = { 927 .enable_reg = 0x8058, 928 .enable_mask = BIT(0), 929 .hw.init = &(const struct clk_init_data) { 930 .name = "disp_cc_mdss_dptx0_aux_clk", 931 .parent_hws = (const struct clk_hw*[]) { 932 &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, 933 }, 934 .num_parents = 1, 935 .flags = CLK_SET_RATE_PARENT, 936 .ops = &clk_branch2_ops, 937 }, 938 }, 939 }; 940 941 static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = { 942 .halt_reg = 0x804c, 943 .halt_check = BRANCH_HALT, 944 .clkr = { 945 .enable_reg = 0x804c, 946 .enable_mask = BIT(0), 947 .hw.init = &(const struct clk_init_data) { 948 .name = "disp_cc_mdss_dptx0_crypto_clk", 949 .parent_hws = (const struct clk_hw*[]) { 950 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 951 }, 952 .num_parents = 1, 953 .flags = CLK_SET_RATE_PARENT, 954 .ops = &clk_branch2_ops, 955 }, 956 }, 957 }; 958 959 static struct clk_branch disp_cc_mdss_dptx0_link_clk = { 960 .halt_reg = 0x8040, 961 .halt_check = BRANCH_HALT, 962 .clkr = { 963 .enable_reg = 0x8040, 964 .enable_mask = BIT(0), 965 .hw.init = &(const struct clk_init_data) { 966 .name = "disp_cc_mdss_dptx0_link_clk", 967 .parent_hws = (const struct clk_hw*[]) { 968 &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 969 }, 970 .num_parents = 1, 971 .flags = CLK_SET_RATE_PARENT, 972 .ops = &clk_branch2_ops, 973 }, 974 }, 975 }; 976 977 static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { 978 .halt_reg = 0x8048, 979 .halt_check = BRANCH_HALT, 980 .clkr = { 981 .enable_reg = 0x8048, 982 .enable_mask = BIT(0), 983 .hw.init = &(const struct clk_init_data) { 984 .name = "disp_cc_mdss_dptx0_link_intf_clk", 985 .parent_hws = (const struct clk_hw*[]) { 986 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 987 }, 988 .num_parents = 1, 989 .flags = CLK_SET_RATE_PARENT, 990 .ops = &clk_branch2_ops, 991 }, 992 }, 993 }; 994 995 static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { 996 .halt_reg = 0x8050, 997 .halt_check = BRANCH_HALT, 998 .clkr = { 999 .enable_reg = 0x8050, 1000 .enable_mask = BIT(0), 1001 .hw.init = &(const struct clk_init_data) { 1002 .name = "disp_cc_mdss_dptx0_pixel0_clk", 1003 .parent_hws = (const struct clk_hw*[]) { 1004 &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 1005 }, 1006 .num_parents = 1, 1007 .flags = CLK_SET_RATE_PARENT, 1008 .ops = &clk_branch2_ops, 1009 }, 1010 }, 1011 }; 1012 1013 static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { 1014 .halt_reg = 0x8054, 1015 .halt_check = BRANCH_HALT, 1016 .clkr = { 1017 .enable_reg = 0x8054, 1018 .enable_mask = BIT(0), 1019 .hw.init = &(const struct clk_init_data) { 1020 .name = "disp_cc_mdss_dptx0_pixel1_clk", 1021 .parent_hws = (const struct clk_hw*[]) { 1022 &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1023 }, 1024 .num_parents = 1, 1025 .flags = CLK_SET_RATE_PARENT, 1026 .ops = &clk_branch2_ops, 1027 }, 1028 }, 1029 }; 1030 1031 static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { 1032 .halt_reg = 0x8044, 1033 .halt_check = BRANCH_HALT, 1034 .clkr = { 1035 .enable_reg = 0x8044, 1036 .enable_mask = BIT(0), 1037 .hw.init = &(const struct clk_init_data) { 1038 .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", 1039 .parent_hws = (const struct clk_hw*[]) { 1040 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1041 }, 1042 .num_parents = 1, 1043 .flags = CLK_SET_RATE_PARENT, 1044 .ops = &clk_branch2_ops, 1045 }, 1046 }, 1047 }; 1048 1049 static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { 1050 .halt_reg = 0x8074, 1051 .halt_check = BRANCH_HALT, 1052 .clkr = { 1053 .enable_reg = 0x8074, 1054 .enable_mask = BIT(0), 1055 .hw.init = &(const struct clk_init_data) { 1056 .name = "disp_cc_mdss_dptx1_aux_clk", 1057 .parent_hws = (const struct clk_hw*[]) { 1058 &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1059 }, 1060 .num_parents = 1, 1061 .flags = CLK_SET_RATE_PARENT, 1062 .ops = &clk_branch2_ops, 1063 }, 1064 }, 1065 }; 1066 1067 static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = { 1068 .halt_reg = 0x8070, 1069 .halt_check = BRANCH_HALT, 1070 .clkr = { 1071 .enable_reg = 0x8070, 1072 .enable_mask = BIT(0), 1073 .hw.init = &(const struct clk_init_data) { 1074 .name = "disp_cc_mdss_dptx1_crypto_clk", 1075 .parent_hws = (const struct clk_hw*[]) { 1076 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1077 }, 1078 .num_parents = 1, 1079 .flags = CLK_SET_RATE_PARENT, 1080 .ops = &clk_branch2_ops, 1081 }, 1082 }, 1083 }; 1084 1085 static struct clk_branch disp_cc_mdss_dptx1_link_clk = { 1086 .halt_reg = 0x8064, 1087 .halt_check = BRANCH_HALT, 1088 .clkr = { 1089 .enable_reg = 0x8064, 1090 .enable_mask = BIT(0), 1091 .hw.init = &(const struct clk_init_data) { 1092 .name = "disp_cc_mdss_dptx1_link_clk", 1093 .parent_hws = (const struct clk_hw*[]) { 1094 &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1095 }, 1096 .num_parents = 1, 1097 .flags = CLK_SET_RATE_PARENT, 1098 .ops = &clk_branch2_ops, 1099 }, 1100 }, 1101 }; 1102 1103 static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { 1104 .halt_reg = 0x806c, 1105 .halt_check = BRANCH_HALT, 1106 .clkr = { 1107 .enable_reg = 0x806c, 1108 .enable_mask = BIT(0), 1109 .hw.init = &(const struct clk_init_data) { 1110 .name = "disp_cc_mdss_dptx1_link_intf_clk", 1111 .parent_hws = (const struct clk_hw*[]) { 1112 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1113 }, 1114 .num_parents = 1, 1115 .flags = CLK_SET_RATE_PARENT, 1116 .ops = &clk_branch2_ops, 1117 }, 1118 }, 1119 }; 1120 1121 static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { 1122 .halt_reg = 0x805c, 1123 .halt_check = BRANCH_HALT, 1124 .clkr = { 1125 .enable_reg = 0x805c, 1126 .enable_mask = BIT(0), 1127 .hw.init = &(const struct clk_init_data) { 1128 .name = "disp_cc_mdss_dptx1_pixel0_clk", 1129 .parent_hws = (const struct clk_hw*[]) { 1130 &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1131 }, 1132 .num_parents = 1, 1133 .flags = CLK_SET_RATE_PARENT, 1134 .ops = &clk_branch2_ops, 1135 }, 1136 }, 1137 }; 1138 1139 static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { 1140 .halt_reg = 0x8060, 1141 .halt_check = BRANCH_HALT, 1142 .clkr = { 1143 .enable_reg = 0x8060, 1144 .enable_mask = BIT(0), 1145 .hw.init = &(const struct clk_init_data) { 1146 .name = "disp_cc_mdss_dptx1_pixel1_clk", 1147 .parent_hws = (const struct clk_hw*[]) { 1148 &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1149 }, 1150 .num_parents = 1, 1151 .flags = CLK_SET_RATE_PARENT, 1152 .ops = &clk_branch2_ops, 1153 }, 1154 }, 1155 }; 1156 1157 static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { 1158 .halt_reg = 0x8068, 1159 .halt_check = BRANCH_HALT, 1160 .clkr = { 1161 .enable_reg = 0x8068, 1162 .enable_mask = BIT(0), 1163 .hw.init = &(const struct clk_init_data) { 1164 .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", 1165 .parent_hws = (const struct clk_hw*[]) { 1166 &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1167 }, 1168 .num_parents = 1, 1169 .flags = CLK_SET_RATE_PARENT, 1170 .ops = &clk_branch2_ops, 1171 }, 1172 }, 1173 }; 1174 1175 static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { 1176 .halt_reg = 0x808c, 1177 .halt_check = BRANCH_HALT, 1178 .clkr = { 1179 .enable_reg = 0x808c, 1180 .enable_mask = BIT(0), 1181 .hw.init = &(const struct clk_init_data) { 1182 .name = "disp_cc_mdss_dptx2_aux_clk", 1183 .parent_hws = (const struct clk_hw*[]) { 1184 &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, 1185 }, 1186 .num_parents = 1, 1187 .flags = CLK_SET_RATE_PARENT, 1188 .ops = &clk_branch2_ops, 1189 }, 1190 }, 1191 }; 1192 1193 static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = { 1194 .halt_reg = 0x8088, 1195 .halt_check = BRANCH_HALT, 1196 .clkr = { 1197 .enable_reg = 0x8088, 1198 .enable_mask = BIT(0), 1199 .hw.init = &(const struct clk_init_data) { 1200 .name = "disp_cc_mdss_dptx2_crypto_clk", 1201 .parent_hws = (const struct clk_hw*[]) { 1202 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1203 }, 1204 .num_parents = 1, 1205 .flags = CLK_SET_RATE_PARENT, 1206 .ops = &clk_branch2_ops, 1207 }, 1208 }, 1209 }; 1210 1211 static struct clk_branch disp_cc_mdss_dptx2_link_clk = { 1212 .halt_reg = 0x8080, 1213 .halt_check = BRANCH_HALT, 1214 .clkr = { 1215 .enable_reg = 0x8080, 1216 .enable_mask = BIT(0), 1217 .hw.init = &(const struct clk_init_data) { 1218 .name = "disp_cc_mdss_dptx2_link_clk", 1219 .parent_hws = (const struct clk_hw*[]) { 1220 &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1221 }, 1222 .num_parents = 1, 1223 .flags = CLK_SET_RATE_PARENT, 1224 .ops = &clk_branch2_ops, 1225 }, 1226 }, 1227 }; 1228 1229 static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { 1230 .halt_reg = 0x8084, 1231 .halt_check = BRANCH_HALT, 1232 .clkr = { 1233 .enable_reg = 0x8084, 1234 .enable_mask = BIT(0), 1235 .hw.init = &(const struct clk_init_data) { 1236 .name = "disp_cc_mdss_dptx2_link_intf_clk", 1237 .parent_hws = (const struct clk_hw*[]) { 1238 &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 1239 }, 1240 .num_parents = 1, 1241 .flags = CLK_SET_RATE_PARENT, 1242 .ops = &clk_branch2_ops, 1243 }, 1244 }, 1245 }; 1246 1247 static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { 1248 .halt_reg = 0x8078, 1249 .halt_check = BRANCH_HALT, 1250 .clkr = { 1251 .enable_reg = 0x8078, 1252 .enable_mask = BIT(0), 1253 .hw.init = &(const struct clk_init_data) { 1254 .name = "disp_cc_mdss_dptx2_pixel0_clk", 1255 .parent_hws = (const struct clk_hw*[]) { 1256 &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 1257 }, 1258 .num_parents = 1, 1259 .flags = CLK_SET_RATE_PARENT, 1260 .ops = &clk_branch2_ops, 1261 }, 1262 }, 1263 }; 1264 1265 static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { 1266 .halt_reg = 0x807c, 1267 .halt_check = BRANCH_HALT, 1268 .clkr = { 1269 .enable_reg = 0x807c, 1270 .enable_mask = BIT(0), 1271 .hw.init = &(const struct clk_init_data) { 1272 .name = "disp_cc_mdss_dptx2_pixel1_clk", 1273 .parent_hws = (const struct clk_hw*[]) { 1274 &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 1275 }, 1276 .num_parents = 1, 1277 .flags = CLK_SET_RATE_PARENT, 1278 .ops = &clk_branch2_ops, 1279 }, 1280 }, 1281 }; 1282 1283 static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { 1284 .halt_reg = 0x809c, 1285 .halt_check = BRANCH_HALT, 1286 .clkr = { 1287 .enable_reg = 0x809c, 1288 .enable_mask = BIT(0), 1289 .hw.init = &(const struct clk_init_data) { 1290 .name = "disp_cc_mdss_dptx3_aux_clk", 1291 .parent_hws = (const struct clk_hw*[]) { 1292 &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, 1293 }, 1294 .num_parents = 1, 1295 .flags = CLK_SET_RATE_PARENT, 1296 .ops = &clk_branch2_ops, 1297 }, 1298 }, 1299 }; 1300 1301 static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = { 1302 .halt_reg = 0x80a0, 1303 .halt_check = BRANCH_HALT, 1304 .clkr = { 1305 .enable_reg = 0x80a0, 1306 .enable_mask = BIT(0), 1307 .hw.init = &(const struct clk_init_data) { 1308 .name = "disp_cc_mdss_dptx3_crypto_clk", 1309 .parent_hws = (const struct clk_hw*[]) { 1310 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1311 }, 1312 .num_parents = 1, 1313 .flags = CLK_SET_RATE_PARENT, 1314 .ops = &clk_branch2_ops, 1315 }, 1316 }, 1317 }; 1318 1319 static struct clk_branch disp_cc_mdss_dptx3_link_clk = { 1320 .halt_reg = 0x8094, 1321 .halt_check = BRANCH_HALT, 1322 .clkr = { 1323 .enable_reg = 0x8094, 1324 .enable_mask = BIT(0), 1325 .hw.init = &(const struct clk_init_data) { 1326 .name = "disp_cc_mdss_dptx3_link_clk", 1327 .parent_hws = (const struct clk_hw*[]) { 1328 &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1329 }, 1330 .num_parents = 1, 1331 .flags = CLK_SET_RATE_PARENT, 1332 .ops = &clk_branch2_ops, 1333 }, 1334 }, 1335 }; 1336 1337 static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { 1338 .halt_reg = 0x8098, 1339 .halt_check = BRANCH_HALT, 1340 .clkr = { 1341 .enable_reg = 0x8098, 1342 .enable_mask = BIT(0), 1343 .hw.init = &(const struct clk_init_data) { 1344 .name = "disp_cc_mdss_dptx3_link_intf_clk", 1345 .parent_hws = (const struct clk_hw*[]) { 1346 &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 1347 }, 1348 .num_parents = 1, 1349 .flags = CLK_SET_RATE_PARENT, 1350 .ops = &clk_branch2_ops, 1351 }, 1352 }, 1353 }; 1354 1355 static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { 1356 .halt_reg = 0x8090, 1357 .halt_check = BRANCH_HALT, 1358 .clkr = { 1359 .enable_reg = 0x8090, 1360 .enable_mask = BIT(0), 1361 .hw.init = &(const struct clk_init_data) { 1362 .name = "disp_cc_mdss_dptx3_pixel0_clk", 1363 .parent_hws = (const struct clk_hw*[]) { 1364 &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 1365 }, 1366 .num_parents = 1, 1367 .flags = CLK_SET_RATE_PARENT, 1368 .ops = &clk_branch2_ops, 1369 }, 1370 }, 1371 }; 1372 1373 static struct clk_branch disp_cc_mdss_esc0_clk = { 1374 .halt_reg = 0x8038, 1375 .halt_check = BRANCH_HALT, 1376 .clkr = { 1377 .enable_reg = 0x8038, 1378 .enable_mask = BIT(0), 1379 .hw.init = &(const struct clk_init_data) { 1380 .name = "disp_cc_mdss_esc0_clk", 1381 .parent_hws = (const struct clk_hw*[]) { 1382 &disp_cc_mdss_esc0_clk_src.clkr.hw, 1383 }, 1384 .num_parents = 1, 1385 .flags = CLK_SET_RATE_PARENT, 1386 .ops = &clk_branch2_ops, 1387 }, 1388 }, 1389 }; 1390 1391 static struct clk_branch disp_cc_mdss_esc1_clk = { 1392 .halt_reg = 0x803c, 1393 .halt_check = BRANCH_HALT, 1394 .clkr = { 1395 .enable_reg = 0x803c, 1396 .enable_mask = BIT(0), 1397 .hw.init = &(const struct clk_init_data) { 1398 .name = "disp_cc_mdss_esc1_clk", 1399 .parent_hws = (const struct clk_hw*[]) { 1400 &disp_cc_mdss_esc1_clk_src.clkr.hw, 1401 }, 1402 .num_parents = 1, 1403 .flags = CLK_SET_RATE_PARENT, 1404 .ops = &clk_branch2_ops, 1405 }, 1406 }, 1407 }; 1408 1409 static struct clk_branch disp_cc_mdss_mdp1_clk = { 1410 .halt_reg = 0xa004, 1411 .halt_check = BRANCH_HALT, 1412 .clkr = { 1413 .enable_reg = 0xa004, 1414 .enable_mask = BIT(0), 1415 .hw.init = &(const struct clk_init_data) { 1416 .name = "disp_cc_mdss_mdp1_clk", 1417 .parent_hws = (const struct clk_hw*[]) { 1418 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1419 }, 1420 .num_parents = 1, 1421 .flags = CLK_SET_RATE_PARENT, 1422 .ops = &clk_branch2_ops, 1423 }, 1424 }, 1425 }; 1426 1427 static struct clk_branch disp_cc_mdss_mdp_clk = { 1428 .halt_reg = 0x800c, 1429 .halt_check = BRANCH_HALT, 1430 .clkr = { 1431 .enable_reg = 0x800c, 1432 .enable_mask = BIT(0), 1433 .hw.init = &(const struct clk_init_data) { 1434 .name = "disp_cc_mdss_mdp_clk", 1435 .parent_hws = (const struct clk_hw*[]) { 1436 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1437 }, 1438 .num_parents = 1, 1439 .flags = CLK_SET_RATE_PARENT, 1440 .ops = &clk_branch2_ops, 1441 }, 1442 }, 1443 }; 1444 1445 static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { 1446 .halt_reg = 0xa010, 1447 .halt_check = BRANCH_HALT, 1448 .clkr = { 1449 .enable_reg = 0xa010, 1450 .enable_mask = BIT(0), 1451 .hw.init = &(const struct clk_init_data) { 1452 .name = "disp_cc_mdss_mdp_lut1_clk", 1453 .parent_hws = (const struct clk_hw*[]) { 1454 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1455 }, 1456 .num_parents = 1, 1457 .flags = CLK_SET_RATE_PARENT, 1458 .ops = &clk_branch2_ops, 1459 }, 1460 }, 1461 }; 1462 1463 static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 1464 .halt_reg = 0x8018, 1465 .halt_check = BRANCH_HALT_VOTED, 1466 .clkr = { 1467 .enable_reg = 0x8018, 1468 .enable_mask = BIT(0), 1469 .hw.init = &(const struct clk_init_data) { 1470 .name = "disp_cc_mdss_mdp_lut_clk", 1471 .parent_hws = (const struct clk_hw*[]) { 1472 &disp_cc_mdss_mdp_clk_src.clkr.hw, 1473 }, 1474 .num_parents = 1, 1475 .flags = CLK_SET_RATE_PARENT, 1476 .ops = &clk_branch2_ops, 1477 }, 1478 }, 1479 }; 1480 1481 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 1482 .halt_reg = 0xc004, 1483 .halt_check = BRANCH_HALT_VOTED, 1484 .clkr = { 1485 .enable_reg = 0xc004, 1486 .enable_mask = BIT(0), 1487 .hw.init = &(const struct clk_init_data) { 1488 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1489 .parent_hws = (const struct clk_hw*[]) { 1490 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1491 }, 1492 .num_parents = 1, 1493 .flags = CLK_SET_RATE_PARENT, 1494 .ops = &clk_branch2_ops, 1495 }, 1496 }, 1497 }; 1498 1499 static struct clk_branch disp_cc_mdss_pclk0_clk = { 1500 .halt_reg = 0x8004, 1501 .halt_check = BRANCH_HALT, 1502 .clkr = { 1503 .enable_reg = 0x8004, 1504 .enable_mask = BIT(0), 1505 .hw.init = &(const struct clk_init_data) { 1506 .name = "disp_cc_mdss_pclk0_clk", 1507 .parent_hws = (const struct clk_hw*[]) { 1508 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 1509 }, 1510 .num_parents = 1, 1511 .flags = CLK_SET_RATE_PARENT, 1512 .ops = &clk_branch2_ops, 1513 }, 1514 }, 1515 }; 1516 1517 static struct clk_branch disp_cc_mdss_pclk1_clk = { 1518 .halt_reg = 0x8008, 1519 .halt_check = BRANCH_HALT, 1520 .clkr = { 1521 .enable_reg = 0x8008, 1522 .enable_mask = BIT(0), 1523 .hw.init = &(const struct clk_init_data) { 1524 .name = "disp_cc_mdss_pclk1_clk", 1525 .parent_hws = (const struct clk_hw*[]) { 1526 &disp_cc_mdss_pclk1_clk_src.clkr.hw, 1527 }, 1528 .num_parents = 1, 1529 .flags = CLK_SET_RATE_PARENT, 1530 .ops = &clk_branch2_ops, 1531 }, 1532 }, 1533 }; 1534 1535 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { 1536 .halt_reg = 0xc00c, 1537 .halt_check = BRANCH_HALT, 1538 .clkr = { 1539 .enable_reg = 0xc00c, 1540 .enable_mask = BIT(0), 1541 .hw.init = &(const struct clk_init_data) { 1542 .name = "disp_cc_mdss_rscc_ahb_clk", 1543 .parent_hws = (const struct clk_hw*[]) { 1544 &disp_cc_mdss_ahb_clk_src.clkr.hw, 1545 }, 1546 .num_parents = 1, 1547 .flags = CLK_SET_RATE_PARENT, 1548 .ops = &clk_branch2_ops, 1549 }, 1550 }, 1551 }; 1552 1553 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 1554 .halt_reg = 0xc008, 1555 .halt_check = BRANCH_HALT, 1556 .clkr = { 1557 .enable_reg = 0xc008, 1558 .enable_mask = BIT(0), 1559 .hw.init = &(const struct clk_init_data) { 1560 .name = "disp_cc_mdss_rscc_vsync_clk", 1561 .parent_hws = (const struct clk_hw*[]) { 1562 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1563 }, 1564 .num_parents = 1, 1565 .flags = CLK_SET_RATE_PARENT, 1566 .ops = &clk_branch2_ops, 1567 }, 1568 }, 1569 }; 1570 1571 static struct clk_branch disp_cc_mdss_vsync1_clk = { 1572 .halt_reg = 0xa01c, 1573 .halt_check = BRANCH_HALT, 1574 .clkr = { 1575 .enable_reg = 0xa01c, 1576 .enable_mask = BIT(0), 1577 .hw.init = &(const struct clk_init_data) { 1578 .name = "disp_cc_mdss_vsync1_clk", 1579 .parent_hws = (const struct clk_hw*[]) { 1580 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1581 }, 1582 .num_parents = 1, 1583 .flags = CLK_SET_RATE_PARENT, 1584 .ops = &clk_branch2_ops, 1585 }, 1586 }, 1587 }; 1588 1589 static struct clk_branch disp_cc_mdss_vsync_clk = { 1590 .halt_reg = 0x8024, 1591 .halt_check = BRANCH_HALT, 1592 .clkr = { 1593 .enable_reg = 0x8024, 1594 .enable_mask = BIT(0), 1595 .hw.init = &(const struct clk_init_data) { 1596 .name = "disp_cc_mdss_vsync_clk", 1597 .parent_hws = (const struct clk_hw*[]) { 1598 &disp_cc_mdss_vsync_clk_src.clkr.hw, 1599 }, 1600 .num_parents = 1, 1601 .flags = CLK_SET_RATE_PARENT, 1602 .ops = &clk_branch2_ops, 1603 }, 1604 }, 1605 }; 1606 1607 static struct clk_branch disp_cc_sleep_clk = { 1608 .halt_reg = 0xe074, 1609 .halt_check = BRANCH_HALT, 1610 .clkr = { 1611 .enable_reg = 0xe074, 1612 .enable_mask = BIT(0), 1613 .hw.init = &(const struct clk_init_data) { 1614 .name = "disp_cc_sleep_clk", 1615 .parent_hws = (const struct clk_hw*[]) { 1616 &disp_cc_sleep_clk_src.clkr.hw, 1617 }, 1618 .num_parents = 1, 1619 .flags = CLK_SET_RATE_PARENT, 1620 .ops = &clk_branch2_ops, 1621 }, 1622 }, 1623 }; 1624 1625 static struct gdsc mdss_gdsc = { 1626 .gdscr = 0x9000, 1627 .pd = { 1628 .name = "mdss_gdsc", 1629 }, 1630 .pwrsts = PWRSTS_OFF_ON, 1631 .flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE, 1632 }; 1633 1634 static struct gdsc mdss_int2_gdsc = { 1635 .gdscr = 0xb000, 1636 .pd = { 1637 .name = "mdss_int2_gdsc", 1638 }, 1639 .pwrsts = PWRSTS_OFF_ON, 1640 .flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE, 1641 }; 1642 1643 static struct clk_regmap *disp_cc_sm8550_clocks[] = { 1644 [DISP_CC_MDSS_ACCU_CLK] = &disp_cc_mdss_accu_clk.clkr, 1645 [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr, 1646 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 1647 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 1648 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 1649 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 1650 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 1651 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 1652 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 1653 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 1654 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 1655 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 1656 [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr, 1657 [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr, 1658 [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr, 1659 [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr, 1660 [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr, 1661 [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr, 1662 [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr, 1663 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr, 1664 [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr, 1665 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, 1666 [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 1667 [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = 1668 &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 1669 [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr, 1670 [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr, 1671 [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr, 1672 [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr, 1673 [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr, 1674 [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr, 1675 [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr, 1676 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr, 1677 [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr, 1678 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr, 1679 [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr, 1680 [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = 1681 &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 1682 [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr, 1683 [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr, 1684 [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr, 1685 [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr, 1686 [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr, 1687 [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr, 1688 [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr, 1689 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr, 1690 [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr, 1691 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr, 1692 [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr, 1693 [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr, 1694 [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr, 1695 [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr, 1696 [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr, 1697 [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr, 1698 [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr, 1699 [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr, 1700 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr, 1701 [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr, 1702 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 1703 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 1704 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 1705 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 1706 [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr, 1707 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 1708 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 1709 [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr, 1710 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 1711 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 1712 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 1713 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 1714 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 1715 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 1716 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, 1717 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, 1718 [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr, 1719 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 1720 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 1721 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 1722 [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 1723 [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, 1724 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, 1725 [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr, 1726 }; 1727 1728 static const struct qcom_reset_map disp_cc_sm8550_resets[] = { 1729 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 }, 1730 [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 }, 1731 [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 }, 1732 }; 1733 1734 static struct gdsc *disp_cc_sm8550_gdscs[] = { 1735 [MDSS_GDSC] = &mdss_gdsc, 1736 [MDSS_INT2_GDSC] = &mdss_int2_gdsc, 1737 }; 1738 1739 static const struct regmap_config disp_cc_sm8550_regmap_config = { 1740 .reg_bits = 32, 1741 .reg_stride = 4, 1742 .val_bits = 32, 1743 .max_register = 0x11008, 1744 .fast_io = true, 1745 }; 1746 1747 static struct qcom_cc_desc disp_cc_sm8550_desc = { 1748 .config = &disp_cc_sm8550_regmap_config, 1749 .clks = disp_cc_sm8550_clocks, 1750 .num_clks = ARRAY_SIZE(disp_cc_sm8550_clocks), 1751 .resets = disp_cc_sm8550_resets, 1752 .num_resets = ARRAY_SIZE(disp_cc_sm8550_resets), 1753 .gdscs = disp_cc_sm8550_gdscs, 1754 .num_gdscs = ARRAY_SIZE(disp_cc_sm8550_gdscs), 1755 }; 1756 1757 static const struct of_device_id disp_cc_sm8550_match_table[] = { 1758 { .compatible = "qcom,sar2130p-dispcc" }, 1759 { .compatible = "qcom,sm8550-dispcc" }, 1760 { .compatible = "qcom,sm8650-dispcc" }, 1761 { } 1762 }; 1763 MODULE_DEVICE_TABLE(of, disp_cc_sm8550_match_table); 1764 1765 static int disp_cc_sm8550_probe(struct platform_device *pdev) 1766 { 1767 struct regmap *regmap; 1768 int ret; 1769 1770 ret = devm_pm_runtime_enable(&pdev->dev); 1771 if (ret) 1772 return ret; 1773 1774 ret = pm_runtime_resume_and_get(&pdev->dev); 1775 if (ret) 1776 return ret; 1777 1778 regmap = qcom_cc_map(pdev, &disp_cc_sm8550_desc); 1779 if (IS_ERR(regmap)) { 1780 ret = PTR_ERR(regmap); 1781 goto err_put_rpm; 1782 } 1783 1784 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-dispcc")) { 1785 lucid_ole_vco[0].max_freq = 2100000000; 1786 disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sm8650; 1787 disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr.hw.init->parent_hws[0] = 1788 &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw; 1789 } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sar2130p-dispcc")) { 1790 disp_cc_pll0_config.l = 0x1f; 1791 disp_cc_pll0_config.alpha = 0x4000; 1792 disp_cc_pll0_config.user_ctl_val = 0x1; 1793 disp_cc_pll1_config.user_ctl_val = 0x1; 1794 disp_cc_mdss_mdp_clk_src.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src_sar2130p; 1795 } 1796 1797 clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 1798 clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); 1799 1800 /* Enable clock gating for MDP clocks */ 1801 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 1802 1803 /* Keep some clocks always-on */ 1804 qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ 1805 1806 ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8550_desc, regmap); 1807 if (ret) 1808 goto err_put_rpm; 1809 1810 pm_runtime_put(&pdev->dev); 1811 1812 return 0; 1813 1814 err_put_rpm: 1815 pm_runtime_put_sync(&pdev->dev); 1816 1817 return ret; 1818 } 1819 1820 static struct platform_driver disp_cc_sm8550_driver = { 1821 .probe = disp_cc_sm8550_probe, 1822 .driver = { 1823 .name = "disp_cc-sm8550", 1824 .of_match_table = disp_cc_sm8550_match_table, 1825 }, 1826 }; 1827 1828 module_platform_driver(disp_cc_sm8550_driver); 1829 1830 MODULE_DESCRIPTION("QTI DISPCC SM8550 / SM8650 Driver"); 1831 MODULE_LICENSE("GPL"); 1832