1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019, 2022, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,dispcc-sc7180.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-rcg.h" 17 #include "clk-regmap-divider.h" 18 #include "common.h" 19 #include "gdsc.h" 20 21 enum { 22 P_BI_TCXO, 23 P_DISP_CC_PLL0_OUT_EVEN, 24 P_DISP_CC_PLL0_OUT_MAIN, 25 P_DP_PHY_PLL_LINK_CLK, 26 P_DP_PHY_PLL_VCO_DIV_CLK, 27 P_DSI0_PHY_PLL_OUT_BYTECLK, 28 P_DSI0_PHY_PLL_OUT_DSICLK, 29 P_GPLL0_OUT_MAIN, 30 }; 31 32 static const struct pll_vco fabia_vco[] = { 33 { 249600000, 2000000000, 0 }, 34 }; 35 36 static struct clk_alpha_pll disp_cc_pll0 = { 37 .offset = 0x0, 38 .vco_table = fabia_vco, 39 .num_vco = ARRAY_SIZE(fabia_vco), 40 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 41 .clkr = { 42 .hw.init = &(struct clk_init_data){ 43 .name = "disp_cc_pll0", 44 .parent_data = &(const struct clk_parent_data){ 45 .fw_name = "bi_tcxo", 46 }, 47 .num_parents = 1, 48 .ops = &clk_alpha_pll_fabia_ops, 49 }, 50 }, 51 }; 52 53 static const struct clk_div_table post_div_table_disp_cc_pll0_out_even[] = { 54 { 0x0, 1 }, 55 { } 56 }; 57 58 static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = { 59 .offset = 0x0, 60 .post_div_shift = 8, 61 .post_div_table = post_div_table_disp_cc_pll0_out_even, 62 .num_post_div = ARRAY_SIZE(post_div_table_disp_cc_pll0_out_even), 63 .width = 4, 64 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 65 .clkr.hw.init = &(struct clk_init_data){ 66 .name = "disp_cc_pll0_out_even", 67 .parent_hws = (const struct clk_hw*[]){ 68 &disp_cc_pll0.clkr.hw, 69 }, 70 .num_parents = 1, 71 .flags = CLK_SET_RATE_PARENT, 72 .ops = &clk_alpha_pll_postdiv_fabia_ops, 73 }, 74 }; 75 76 static const struct parent_map disp_cc_parent_map_0[] = { 77 { P_BI_TCXO, 0 }, 78 }; 79 80 static const struct clk_parent_data disp_cc_parent_data_0[] = { 81 { .fw_name = "bi_tcxo" }, 82 }; 83 84 static const struct parent_map disp_cc_parent_map_1[] = { 85 { P_BI_TCXO, 0 }, 86 { P_DP_PHY_PLL_LINK_CLK, 1 }, 87 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, 88 }; 89 90 static const struct clk_parent_data disp_cc_parent_data_1[] = { 91 { .fw_name = "bi_tcxo" }, 92 { .fw_name = "dp_phy_pll_link_clk" }, 93 { .fw_name = "dp_phy_pll_vco_div_clk" }, 94 }; 95 96 static const struct parent_map disp_cc_parent_map_2[] = { 97 { P_BI_TCXO, 0 }, 98 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, 99 }; 100 101 static const struct clk_parent_data disp_cc_parent_data_2[] = { 102 { .fw_name = "bi_tcxo" }, 103 { .fw_name = "dsi0_phy_pll_out_byteclk" }, 104 }; 105 106 static const struct parent_map disp_cc_parent_map_3[] = { 107 { P_BI_TCXO, 0 }, 108 { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 109 { P_GPLL0_OUT_MAIN, 4 }, 110 { P_DISP_CC_PLL0_OUT_EVEN, 5 }, 111 }; 112 113 static const struct clk_parent_data disp_cc_parent_data_3[] = { 114 { .fw_name = "bi_tcxo" }, 115 { .hw = &disp_cc_pll0.clkr.hw }, 116 { .fw_name = "gcc_disp_gpll0_clk_src" }, 117 { .hw = &disp_cc_pll0_out_even.clkr.hw }, 118 }; 119 120 static const struct parent_map disp_cc_parent_map_4[] = { 121 { P_BI_TCXO, 0 }, 122 { P_GPLL0_OUT_MAIN, 4 }, 123 }; 124 125 static const struct clk_parent_data disp_cc_parent_data_4[] = { 126 { .fw_name = "bi_tcxo" }, 127 { .fw_name = "gcc_disp_gpll0_clk_src" }, 128 }; 129 130 static const struct parent_map disp_cc_parent_map_5[] = { 131 { P_BI_TCXO, 0 }, 132 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 133 }; 134 135 static const struct clk_parent_data disp_cc_parent_data_5[] = { 136 { .fw_name = "bi_tcxo" }, 137 { .fw_name = "dsi0_phy_pll_out_dsiclk" }, 138 }; 139 140 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 141 F(19200000, P_BI_TCXO, 1, 0, 0), 142 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), 143 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), 144 { } 145 }; 146 147 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 148 .cmd_rcgr = 0x22bc, 149 .mnd_width = 0, 150 .hid_width = 5, 151 .parent_map = disp_cc_parent_map_4, 152 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 153 .clkr.hw.init = &(struct clk_init_data){ 154 .name = "disp_cc_mdss_ahb_clk_src", 155 .parent_data = disp_cc_parent_data_4, 156 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 157 .flags = CLK_SET_RATE_PARENT, 158 .ops = &clk_rcg2_shared_ops, 159 }, 160 }; 161 162 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 163 .cmd_rcgr = 0x2110, 164 .mnd_width = 0, 165 .hid_width = 5, 166 .parent_map = disp_cc_parent_map_2, 167 .clkr.hw.init = &(struct clk_init_data){ 168 .name = "disp_cc_mdss_byte0_clk_src", 169 .parent_data = disp_cc_parent_data_2, 170 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 171 .flags = CLK_SET_RATE_PARENT, 172 .ops = &clk_byte2_ops, 173 }, 174 }; 175 176 static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { 177 F(19200000, P_BI_TCXO, 1, 0, 0), 178 { } 179 }; 180 181 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { 182 .cmd_rcgr = 0x21dc, 183 .mnd_width = 0, 184 .hid_width = 5, 185 .parent_map = disp_cc_parent_map_0, 186 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, 187 .clkr.hw.init = &(struct clk_init_data){ 188 .name = "disp_cc_mdss_dp_aux_clk_src", 189 .parent_data = disp_cc_parent_data_0, 190 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 191 .ops = &clk_rcg2_ops, 192 }, 193 }; 194 195 static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { 196 .cmd_rcgr = 0x2194, 197 .mnd_width = 0, 198 .hid_width = 5, 199 .parent_map = disp_cc_parent_map_1, 200 .clkr.hw.init = &(struct clk_init_data){ 201 .name = "disp_cc_mdss_dp_crypto_clk_src", 202 .parent_data = disp_cc_parent_data_1, 203 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 204 .ops = &clk_byte2_ops, 205 }, 206 }; 207 208 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { 209 .cmd_rcgr = 0x2178, 210 .mnd_width = 0, 211 .hid_width = 5, 212 .parent_map = disp_cc_parent_map_1, 213 .clkr.hw.init = &(struct clk_init_data){ 214 .name = "disp_cc_mdss_dp_link_clk_src", 215 .parent_data = disp_cc_parent_data_1, 216 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 217 .ops = &clk_byte2_ops, 218 }, 219 }; 220 221 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { 222 .cmd_rcgr = 0x21ac, 223 .mnd_width = 16, 224 .hid_width = 5, 225 .parent_map = disp_cc_parent_map_1, 226 .clkr.hw.init = &(struct clk_init_data){ 227 .name = "disp_cc_mdss_dp_pixel_clk_src", 228 .parent_data = disp_cc_parent_data_1, 229 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 230 .ops = &clk_dp_ops, 231 }, 232 }; 233 234 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 235 .cmd_rcgr = 0x2148, 236 .mnd_width = 0, 237 .hid_width = 5, 238 .parent_map = disp_cc_parent_map_2, 239 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, 240 .clkr.hw.init = &(struct clk_init_data){ 241 .name = "disp_cc_mdss_esc0_clk_src", 242 .parent_data = disp_cc_parent_data_2, 243 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 244 .ops = &clk_rcg2_ops, 245 }, 246 }; 247 248 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 249 F(19200000, P_BI_TCXO, 1, 0, 0), 250 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), 251 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), 252 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), 253 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 254 { } 255 }; 256 257 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 258 .cmd_rcgr = 0x20c8, 259 .mnd_width = 0, 260 .hid_width = 5, 261 .parent_map = disp_cc_parent_map_3, 262 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 263 .clkr.hw.init = &(struct clk_init_data){ 264 .name = "disp_cc_mdss_mdp_clk_src", 265 .parent_data = disp_cc_parent_data_3, 266 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 267 .ops = &clk_rcg2_shared_ops, 268 }, 269 }; 270 271 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 272 .cmd_rcgr = 0x2098, 273 .mnd_width = 8, 274 .hid_width = 5, 275 .parent_map = disp_cc_parent_map_5, 276 .clkr.hw.init = &(struct clk_init_data){ 277 .name = "disp_cc_mdss_pclk0_clk_src", 278 .parent_data = disp_cc_parent_data_5, 279 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 280 .flags = CLK_SET_RATE_PARENT, 281 .ops = &clk_pixel_ops, 282 }, 283 }; 284 285 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { 286 .cmd_rcgr = 0x20e0, 287 .mnd_width = 0, 288 .hid_width = 5, 289 .parent_map = disp_cc_parent_map_3, 290 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 291 .clkr.hw.init = &(struct clk_init_data){ 292 .name = "disp_cc_mdss_rot_clk_src", 293 .parent_data = disp_cc_parent_data_3, 294 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 295 .ops = &clk_rcg2_shared_ops, 296 }, 297 }; 298 299 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 300 .cmd_rcgr = 0x20f8, 301 .mnd_width = 0, 302 .hid_width = 5, 303 .parent_map = disp_cc_parent_map_0, 304 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, 305 .clkr.hw.init = &(struct clk_init_data){ 306 .name = "disp_cc_mdss_vsync_clk_src", 307 .parent_data = disp_cc_parent_data_0, 308 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 309 .ops = &clk_rcg2_shared_ops, 310 }, 311 }; 312 313 static struct clk_branch disp_cc_mdss_ahb_clk = { 314 .halt_reg = 0x2080, 315 .halt_check = BRANCH_HALT, 316 .clkr = { 317 .enable_reg = 0x2080, 318 .enable_mask = BIT(0), 319 .hw.init = &(struct clk_init_data){ 320 .name = "disp_cc_mdss_ahb_clk", 321 .parent_hws = (const struct clk_hw*[]){ 322 &disp_cc_mdss_ahb_clk_src.clkr.hw, 323 }, 324 .num_parents = 1, 325 .flags = CLK_SET_RATE_PARENT, 326 .ops = &clk_branch2_ops, 327 }, 328 }, 329 }; 330 331 static struct clk_branch disp_cc_mdss_byte0_clk = { 332 .halt_reg = 0x2028, 333 .halt_check = BRANCH_HALT, 334 .clkr = { 335 .enable_reg = 0x2028, 336 .enable_mask = BIT(0), 337 .hw.init = &(struct clk_init_data){ 338 .name = "disp_cc_mdss_byte0_clk", 339 .parent_hws = (const struct clk_hw*[]){ 340 &disp_cc_mdss_byte0_clk_src.clkr.hw, 341 }, 342 .num_parents = 1, 343 .flags = CLK_SET_RATE_PARENT, 344 .ops = &clk_branch2_ops, 345 }, 346 }, 347 }; 348 349 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 350 .reg = 0x2128, 351 .shift = 0, 352 .width = 2, 353 .clkr.hw.init = &(struct clk_init_data) { 354 .name = "disp_cc_mdss_byte0_div_clk_src", 355 .parent_hws = (const struct clk_hw*[]) { 356 &disp_cc_mdss_byte0_clk_src.clkr.hw, 357 }, 358 .num_parents = 1, 359 .ops = &clk_regmap_div_ops, 360 }, 361 }; 362 363 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { 364 .reg = 0x2190, 365 .shift = 0, 366 .width = 2, 367 .clkr.hw.init = &(struct clk_init_data) { 368 .name = "disp_cc_mdss_dp_link_div_clk_src", 369 .parent_hws = (const struct clk_hw*[]) { 370 &disp_cc_mdss_dp_link_clk_src.clkr.hw, 371 }, 372 .num_parents = 1, 373 .ops = &clk_regmap_div_ops, 374 }, 375 }; 376 377 static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 378 .halt_reg = 0x202c, 379 .halt_check = BRANCH_HALT, 380 .clkr = { 381 .enable_reg = 0x202c, 382 .enable_mask = BIT(0), 383 .hw.init = &(struct clk_init_data){ 384 .name = "disp_cc_mdss_byte0_intf_clk", 385 .parent_hws = (const struct clk_hw*[]){ 386 &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 387 }, 388 .num_parents = 1, 389 .flags = CLK_SET_RATE_PARENT, 390 .ops = &clk_branch2_ops, 391 }, 392 }, 393 }; 394 395 static struct clk_branch disp_cc_mdss_dp_aux_clk = { 396 .halt_reg = 0x2054, 397 .halt_check = BRANCH_HALT, 398 .clkr = { 399 .enable_reg = 0x2054, 400 .enable_mask = BIT(0), 401 .hw.init = &(struct clk_init_data){ 402 .name = "disp_cc_mdss_dp_aux_clk", 403 .parent_hws = (const struct clk_hw*[]){ 404 &disp_cc_mdss_dp_aux_clk_src.clkr.hw, 405 }, 406 .num_parents = 1, 407 .flags = CLK_SET_RATE_PARENT, 408 .ops = &clk_branch2_ops, 409 }, 410 }, 411 }; 412 413 static struct clk_branch disp_cc_mdss_dp_crypto_clk = { 414 .halt_reg = 0x2048, 415 .halt_check = BRANCH_HALT, 416 .clkr = { 417 .enable_reg = 0x2048, 418 .enable_mask = BIT(0), 419 .hw.init = &(struct clk_init_data){ 420 .name = "disp_cc_mdss_dp_crypto_clk", 421 .parent_hws = (const struct clk_hw*[]){ 422 &disp_cc_mdss_dp_crypto_clk_src.clkr.hw, 423 }, 424 .num_parents = 1, 425 .flags = CLK_SET_RATE_PARENT, 426 .ops = &clk_branch2_ops, 427 }, 428 }, 429 }; 430 431 static struct clk_branch disp_cc_mdss_dp_link_clk = { 432 .halt_reg = 0x2040, 433 .halt_check = BRANCH_HALT, 434 .clkr = { 435 .enable_reg = 0x2040, 436 .enable_mask = BIT(0), 437 .hw.init = &(struct clk_init_data){ 438 .name = "disp_cc_mdss_dp_link_clk", 439 .parent_hws = (const struct clk_hw*[]){ 440 &disp_cc_mdss_dp_link_clk_src.clkr.hw, 441 }, 442 .num_parents = 1, 443 .flags = CLK_SET_RATE_PARENT, 444 .ops = &clk_branch2_ops, 445 }, 446 }, 447 }; 448 449 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { 450 .halt_reg = 0x2044, 451 .halt_check = BRANCH_HALT, 452 .clkr = { 453 .enable_reg = 0x2044, 454 .enable_mask = BIT(0), 455 .hw.init = &(struct clk_init_data){ 456 .name = "disp_cc_mdss_dp_link_intf_clk", 457 .parent_hws = (const struct clk_hw*[]){ 458 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, 459 }, 460 .num_parents = 1, 461 .ops = &clk_branch2_ops, 462 }, 463 }, 464 }; 465 466 static struct clk_branch disp_cc_mdss_dp_pixel_clk = { 467 .halt_reg = 0x204c, 468 .halt_check = BRANCH_HALT, 469 .clkr = { 470 .enable_reg = 0x204c, 471 .enable_mask = BIT(0), 472 .hw.init = &(struct clk_init_data){ 473 .name = "disp_cc_mdss_dp_pixel_clk", 474 .parent_hws = (const struct clk_hw*[]){ 475 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, 476 }, 477 .num_parents = 1, 478 .flags = CLK_SET_RATE_PARENT, 479 .ops = &clk_branch2_ops, 480 }, 481 }, 482 }; 483 484 static struct clk_branch disp_cc_mdss_esc0_clk = { 485 .halt_reg = 0x2038, 486 .halt_check = BRANCH_HALT, 487 .clkr = { 488 .enable_reg = 0x2038, 489 .enable_mask = BIT(0), 490 .hw.init = &(struct clk_init_data){ 491 .name = "disp_cc_mdss_esc0_clk", 492 .parent_hws = (const struct clk_hw*[]){ 493 &disp_cc_mdss_esc0_clk_src.clkr.hw, 494 }, 495 .num_parents = 1, 496 .flags = CLK_SET_RATE_PARENT, 497 .ops = &clk_branch2_ops, 498 }, 499 }, 500 }; 501 502 static struct clk_branch disp_cc_mdss_mdp_clk = { 503 .halt_reg = 0x200c, 504 .halt_check = BRANCH_HALT, 505 .clkr = { 506 .enable_reg = 0x200c, 507 .enable_mask = BIT(0), 508 .hw.init = &(struct clk_init_data){ 509 .name = "disp_cc_mdss_mdp_clk", 510 .parent_hws = (const struct clk_hw*[]){ 511 &disp_cc_mdss_mdp_clk_src.clkr.hw, 512 }, 513 .num_parents = 1, 514 .flags = CLK_SET_RATE_PARENT, 515 .ops = &clk_branch2_ops, 516 }, 517 }, 518 }; 519 520 static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 521 .halt_reg = 0x201c, 522 .halt_check = BRANCH_VOTED, 523 .clkr = { 524 .enable_reg = 0x201c, 525 .enable_mask = BIT(0), 526 .hw.init = &(struct clk_init_data){ 527 .name = "disp_cc_mdss_mdp_lut_clk", 528 .parent_hws = (const struct clk_hw*[]){ 529 &disp_cc_mdss_mdp_clk_src.clkr.hw, 530 }, 531 .num_parents = 1, 532 .ops = &clk_branch2_ops, 533 }, 534 }, 535 }; 536 537 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 538 .halt_reg = 0x4004, 539 .halt_check = BRANCH_VOTED, 540 .clkr = { 541 .enable_reg = 0x4004, 542 .enable_mask = BIT(0), 543 .hw.init = &(struct clk_init_data){ 544 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 545 .parent_hws = (const struct clk_hw*[]){ 546 &disp_cc_mdss_ahb_clk_src.clkr.hw, 547 }, 548 .num_parents = 1, 549 .flags = CLK_SET_RATE_PARENT, 550 .ops = &clk_branch2_ops, 551 }, 552 }, 553 }; 554 555 static struct clk_branch disp_cc_mdss_pclk0_clk = { 556 .halt_reg = 0x2004, 557 .halt_check = BRANCH_HALT, 558 .clkr = { 559 .enable_reg = 0x2004, 560 .enable_mask = BIT(0), 561 .hw.init = &(struct clk_init_data){ 562 .name = "disp_cc_mdss_pclk0_clk", 563 .parent_hws = (const struct clk_hw*[]){ 564 &disp_cc_mdss_pclk0_clk_src.clkr.hw, 565 }, 566 .num_parents = 1, 567 .flags = CLK_SET_RATE_PARENT, 568 .ops = &clk_branch2_ops, 569 }, 570 }, 571 }; 572 573 static struct clk_branch disp_cc_mdss_rot_clk = { 574 .halt_reg = 0x2014, 575 .halt_check = BRANCH_HALT, 576 .clkr = { 577 .enable_reg = 0x2014, 578 .enable_mask = BIT(0), 579 .hw.init = &(struct clk_init_data){ 580 .name = "disp_cc_mdss_rot_clk", 581 .parent_hws = (const struct clk_hw*[]){ 582 &disp_cc_mdss_rot_clk_src.clkr.hw, 583 }, 584 .num_parents = 1, 585 .flags = CLK_SET_RATE_PARENT, 586 .ops = &clk_branch2_ops, 587 }, 588 }, 589 }; 590 591 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 592 .halt_reg = 0x4008, 593 .halt_check = BRANCH_HALT, 594 .clkr = { 595 .enable_reg = 0x4008, 596 .enable_mask = BIT(0), 597 .hw.init = &(struct clk_init_data){ 598 .name = "disp_cc_mdss_rscc_vsync_clk", 599 .parent_hws = (const struct clk_hw*[]){ 600 &disp_cc_mdss_vsync_clk_src.clkr.hw, 601 }, 602 .num_parents = 1, 603 .flags = CLK_SET_RATE_PARENT, 604 .ops = &clk_branch2_ops, 605 }, 606 }, 607 }; 608 609 static struct clk_branch disp_cc_mdss_vsync_clk = { 610 .halt_reg = 0x2024, 611 .halt_check = BRANCH_HALT, 612 .clkr = { 613 .enable_reg = 0x2024, 614 .enable_mask = BIT(0), 615 .hw.init = &(struct clk_init_data){ 616 .name = "disp_cc_mdss_vsync_clk", 617 .parent_hws = (const struct clk_hw*[]){ 618 &disp_cc_mdss_vsync_clk_src.clkr.hw, 619 }, 620 .num_parents = 1, 621 .flags = CLK_SET_RATE_PARENT, 622 .ops = &clk_branch2_ops, 623 }, 624 }, 625 }; 626 627 static struct gdsc mdss_gdsc = { 628 .gdscr = 0x3000, 629 .en_rest_wait_val = 0x2, 630 .en_few_wait_val = 0x2, 631 .clk_dis_wait_val = 0xf, 632 .pd = { 633 .name = "mdss_gdsc", 634 }, 635 .pwrsts = PWRSTS_OFF_ON, 636 .flags = HW_CTRL, 637 }; 638 639 static struct gdsc *disp_cc_sc7180_gdscs[] = { 640 [MDSS_GDSC] = &mdss_gdsc, 641 }; 642 643 static struct clk_regmap *disp_cc_sc7180_clocks[] = { 644 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 645 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 646 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 647 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 648 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 649 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 650 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, 651 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, 652 [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr, 653 [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr, 654 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, 655 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, 656 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = 657 &disp_cc_mdss_dp_link_div_clk_src.clkr, 658 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, 659 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, 660 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, 661 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 662 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 663 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 664 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 665 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 666 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 667 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 668 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 669 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, 670 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, 671 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, 672 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 673 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 674 [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 675 [DISP_CC_PLL0_OUT_EVEN] = &disp_cc_pll0_out_even.clkr, 676 }; 677 678 static const struct regmap_config disp_cc_sc7180_regmap_config = { 679 .reg_bits = 32, 680 .reg_stride = 4, 681 .val_bits = 32, 682 .max_register = 0x10000, 683 .fast_io = true, 684 }; 685 686 static const struct qcom_cc_desc disp_cc_sc7180_desc = { 687 .config = &disp_cc_sc7180_regmap_config, 688 .clks = disp_cc_sc7180_clocks, 689 .num_clks = ARRAY_SIZE(disp_cc_sc7180_clocks), 690 .gdscs = disp_cc_sc7180_gdscs, 691 .num_gdscs = ARRAY_SIZE(disp_cc_sc7180_gdscs), 692 }; 693 694 static const struct of_device_id disp_cc_sc7180_match_table[] = { 695 { .compatible = "qcom,sc7180-dispcc" }, 696 { } 697 }; 698 MODULE_DEVICE_TABLE(of, disp_cc_sc7180_match_table); 699 700 static int disp_cc_sc7180_probe(struct platform_device *pdev) 701 { 702 struct regmap *regmap; 703 struct alpha_pll_config disp_cc_pll_config = {}; 704 705 regmap = qcom_cc_map(pdev, &disp_cc_sc7180_desc); 706 if (IS_ERR(regmap)) 707 return PTR_ERR(regmap); 708 709 /* 1380MHz configuration */ 710 disp_cc_pll_config.l = 0x47; 711 disp_cc_pll_config.alpha = 0xe000; 712 disp_cc_pll_config.user_ctl_val = 0x00000001; 713 disp_cc_pll_config.user_ctl_hi_val = 0x00004805; 714 715 clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll_config); 716 717 return qcom_cc_really_probe(&pdev->dev, &disp_cc_sc7180_desc, regmap); 718 } 719 720 static struct platform_driver disp_cc_sc7180_driver = { 721 .probe = disp_cc_sc7180_probe, 722 .driver = { 723 .name = "sc7180-dispcc", 724 .of_match_table = disp_cc_sc7180_match_table, 725 }, 726 }; 727 728 module_platform_driver(disp_cc_sc7180_driver); 729 730 MODULE_DESCRIPTION("QTI DISP_CC SC7180 Driver"); 731 MODULE_LICENSE("GPL v2"); 732