1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/err.h> 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/string_choices.h> 13 #include <soc/qcom/cmd-db.h> 14 #include <soc/qcom/rpmh.h> 15 #include <soc/qcom/tcs.h> 16 17 #include <dt-bindings/clock/qcom,rpmh.h> 18 19 #define CLK_RPMH_ARC_EN_OFFSET 0 20 #define CLK_RPMH_VRM_EN_OFFSET 4 21 22 /** 23 * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM) 24 * @unit: divisor used to convert Hz value to an RPMh msg 25 * @width: multiplier used to convert Hz value to an RPMh msg 26 * @vcd: virtual clock domain that this bcm belongs to 27 * @reserved: reserved to pad the struct 28 */ 29 struct bcm_db { 30 __le32 unit; 31 __le16 width; 32 u8 vcd; 33 u8 reserved; 34 }; 35 36 /** 37 * struct clk_rpmh - individual rpmh clock data structure 38 * @hw: handle between common and hardware-specific interfaces 39 * @res_name: resource name for the rpmh clock 40 * @div: clock divider to compute the clock rate 41 * @res_addr: base address of the rpmh resource within the RPMh 42 * @res_on_val: rpmh clock enable value 43 * @state: rpmh clock requested state 44 * @aggr_state: rpmh clock aggregated state 45 * @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh 46 * @valid_state_mask: mask to determine the state of the rpmh clock 47 * @unit: divisor to convert rate to rpmh msg in magnitudes of Khz 48 * @dev: device to which it is attached 49 * @peer: pointer to the clock rpmh sibling 50 */ 51 struct clk_rpmh { 52 struct clk_hw hw; 53 const char *res_name; 54 u8 div; 55 u32 res_addr; 56 u32 res_on_val; 57 u32 state; 58 u32 aggr_state; 59 u32 last_sent_aggr_state; 60 u32 valid_state_mask; 61 u32 unit; 62 struct device *dev; 63 struct clk_rpmh *peer; 64 }; 65 66 struct clk_rpmh_desc { 67 struct clk_hw **clks; 68 size_t num_clks; 69 /* RPMh clock clkaN are optional for this platform */ 70 bool clka_optional; 71 }; 72 73 static DEFINE_MUTEX(rpmh_clk_lock); 74 75 #define __DEFINE_CLK_RPMH(_name, _clk_name, _res_name, \ 76 _res_en_offset, _res_on, _div) \ 77 static struct clk_rpmh clk_rpmh_##_clk_name##_ao; \ 78 static struct clk_rpmh clk_rpmh_##_clk_name = { \ 79 .res_name = _res_name, \ 80 .res_addr = _res_en_offset, \ 81 .res_on_val = _res_on, \ 82 .div = _div, \ 83 .peer = &clk_rpmh_##_clk_name##_ao, \ 84 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ 85 BIT(RPMH_ACTIVE_ONLY_STATE) | \ 86 BIT(RPMH_SLEEP_STATE)), \ 87 .hw.init = &(struct clk_init_data){ \ 88 .ops = &clk_rpmh_ops, \ 89 .name = #_name, \ 90 .parent_data = &(const struct clk_parent_data){ \ 91 .fw_name = "xo", \ 92 .name = "xo_board", \ 93 }, \ 94 .num_parents = 1, \ 95 }, \ 96 }; \ 97 static struct clk_rpmh clk_rpmh_##_clk_name##_ao= { \ 98 .res_name = _res_name, \ 99 .res_addr = _res_en_offset, \ 100 .res_on_val = _res_on, \ 101 .div = _div, \ 102 .peer = &clk_rpmh_##_clk_name, \ 103 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \ 104 BIT(RPMH_ACTIVE_ONLY_STATE)), \ 105 .hw.init = &(struct clk_init_data){ \ 106 .ops = &clk_rpmh_ops, \ 107 .name = #_name "_ao", \ 108 .parent_data = &(const struct clk_parent_data){ \ 109 .fw_name = "xo", \ 110 .name = "xo_board", \ 111 }, \ 112 .num_parents = 1, \ 113 }, \ 114 } 115 116 #define DEFINE_CLK_RPMH_ARC(_name, _res_name, _res_on, _div) \ 117 __DEFINE_CLK_RPMH(_name, _name##_##div##_div, _res_name, \ 118 CLK_RPMH_ARC_EN_OFFSET, _res_on, _div) 119 120 #define DEFINE_CLK_RPMH_VRM(_name, _suffix, _res_name, _div) \ 121 __DEFINE_CLK_RPMH(_name, _name##_suffix, _res_name, \ 122 CLK_RPMH_VRM_EN_OFFSET, 1, _div) 123 124 #define DEFINE_CLK_RPMH_BCM(_name, _res_name) \ 125 static struct clk_rpmh clk_rpmh_##_name = { \ 126 .res_name = _res_name, \ 127 .valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \ 128 .div = 1, \ 129 .hw.init = &(struct clk_init_data){ \ 130 .ops = &clk_rpmh_bcm_ops, \ 131 .name = #_name, \ 132 }, \ 133 } 134 135 static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw) 136 { 137 return container_of(_hw, struct clk_rpmh, hw); 138 } 139 140 static inline bool has_state_changed(struct clk_rpmh *c, u32 state) 141 { 142 return (c->last_sent_aggr_state & BIT(state)) 143 != (c->aggr_state & BIT(state)); 144 } 145 146 static int clk_rpmh_send(struct clk_rpmh *c, enum rpmh_state state, 147 struct tcs_cmd *cmd, bool wait) 148 { 149 if (wait) 150 return rpmh_write(c->dev, state, cmd, 1); 151 152 return rpmh_write_async(c->dev, state, cmd, 1); 153 } 154 155 static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c) 156 { 157 struct tcs_cmd cmd = { 0 }; 158 u32 cmd_state, on_val; 159 enum rpmh_state state = RPMH_SLEEP_STATE; 160 int ret; 161 bool wait; 162 163 cmd.addr = c->res_addr; 164 cmd_state = c->aggr_state; 165 on_val = c->res_on_val; 166 167 for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) { 168 if (has_state_changed(c, state)) { 169 if (cmd_state & BIT(state)) 170 cmd.data = on_val; 171 172 wait = cmd_state && state == RPMH_ACTIVE_ONLY_STATE; 173 ret = clk_rpmh_send(c, state, &cmd, wait); 174 if (ret) { 175 dev_err(c->dev, "set %s state of %s failed: (%d)\n", 176 !state ? "sleep" : 177 state == RPMH_WAKE_ONLY_STATE ? 178 "wake" : "active", c->res_name, ret); 179 return ret; 180 } 181 } 182 } 183 184 c->last_sent_aggr_state = c->aggr_state; 185 c->peer->last_sent_aggr_state = c->last_sent_aggr_state; 186 187 return 0; 188 } 189 190 /* 191 * Update state and aggregate state values based on enable value. 192 */ 193 static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c, 194 bool enable) 195 { 196 int ret; 197 198 c->state = enable ? c->valid_state_mask : 0; 199 c->aggr_state = c->state | c->peer->state; 200 c->peer->aggr_state = c->aggr_state; 201 202 ret = clk_rpmh_send_aggregate_command(c); 203 if (!ret) 204 return 0; 205 206 if (ret && enable) 207 c->state = 0; 208 else if (ret) 209 c->state = c->valid_state_mask; 210 211 WARN(1, "clk: %s failed to %s\n", c->res_name, 212 str_enable_disable(enable)); 213 return ret; 214 } 215 216 static int clk_rpmh_prepare(struct clk_hw *hw) 217 { 218 struct clk_rpmh *c = to_clk_rpmh(hw); 219 int ret = 0; 220 221 mutex_lock(&rpmh_clk_lock); 222 ret = clk_rpmh_aggregate_state_send_command(c, true); 223 mutex_unlock(&rpmh_clk_lock); 224 225 return ret; 226 } 227 228 static void clk_rpmh_unprepare(struct clk_hw *hw) 229 { 230 struct clk_rpmh *c = to_clk_rpmh(hw); 231 232 mutex_lock(&rpmh_clk_lock); 233 clk_rpmh_aggregate_state_send_command(c, false); 234 mutex_unlock(&rpmh_clk_lock); 235 }; 236 237 static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw, 238 unsigned long prate) 239 { 240 struct clk_rpmh *r = to_clk_rpmh(hw); 241 242 /* 243 * RPMh clocks have a fixed rate. Return static rate. 244 */ 245 return prate / r->div; 246 } 247 248 static const struct clk_ops clk_rpmh_ops = { 249 .prepare = clk_rpmh_prepare, 250 .unprepare = clk_rpmh_unprepare, 251 .recalc_rate = clk_rpmh_recalc_rate, 252 }; 253 254 static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable) 255 { 256 struct tcs_cmd cmd = { 0 }; 257 u32 cmd_state; 258 int ret = 0; 259 260 mutex_lock(&rpmh_clk_lock); 261 if (enable) { 262 cmd_state = 1; 263 if (c->aggr_state) 264 cmd_state = c->aggr_state; 265 } else { 266 cmd_state = 0; 267 } 268 269 cmd_state = min(cmd_state, BCM_TCS_CMD_VOTE_MASK); 270 271 if (c->last_sent_aggr_state != cmd_state) { 272 cmd.addr = c->res_addr; 273 cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state); 274 275 /* 276 * Send only an active only state request. RPMh continues to 277 * use the active state when we're in sleep/wake state as long 278 * as the sleep/wake state has never been set. 279 */ 280 ret = clk_rpmh_send(c, RPMH_ACTIVE_ONLY_STATE, &cmd, enable); 281 if (ret) { 282 dev_err(c->dev, "set active state of %s failed: (%d)\n", 283 c->res_name, ret); 284 } else { 285 c->last_sent_aggr_state = cmd_state; 286 } 287 } 288 289 mutex_unlock(&rpmh_clk_lock); 290 291 return ret; 292 } 293 294 static int clk_rpmh_bcm_prepare(struct clk_hw *hw) 295 { 296 struct clk_rpmh *c = to_clk_rpmh(hw); 297 298 return clk_rpmh_bcm_send_cmd(c, true); 299 } 300 301 static void clk_rpmh_bcm_unprepare(struct clk_hw *hw) 302 { 303 struct clk_rpmh *c = to_clk_rpmh(hw); 304 305 clk_rpmh_bcm_send_cmd(c, false); 306 } 307 308 static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate, 309 unsigned long parent_rate) 310 { 311 struct clk_rpmh *c = to_clk_rpmh(hw); 312 313 c->aggr_state = rate / c->unit; 314 /* 315 * Since any non-zero value sent to hw would result in enabling the 316 * clock, only send the value if the clock has already been prepared. 317 */ 318 if (clk_hw_is_prepared(hw)) 319 clk_rpmh_bcm_send_cmd(c, true); 320 321 return 0; 322 } 323 324 static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate, 325 unsigned long *parent_rate) 326 { 327 return rate; 328 } 329 330 static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw, 331 unsigned long prate) 332 { 333 struct clk_rpmh *c = to_clk_rpmh(hw); 334 335 return (unsigned long)c->aggr_state * c->unit; 336 } 337 338 static const struct clk_ops clk_rpmh_bcm_ops = { 339 .prepare = clk_rpmh_bcm_prepare, 340 .unprepare = clk_rpmh_bcm_unprepare, 341 .set_rate = clk_rpmh_bcm_set_rate, 342 .round_rate = clk_rpmh_round_rate, 343 .recalc_rate = clk_rpmh_bcm_recalc_rate, 344 }; 345 346 /* Resource name must match resource id present in cmd-db */ 347 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 1); 348 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 2); 349 DEFINE_CLK_RPMH_ARC(bi_tcxo, "xo.lvl", 0x3, 4); 350 DEFINE_CLK_RPMH_ARC(qlink, "qphy.lvl", 0x1, 4); 351 352 DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a2, "lnbclka1", 2); 353 DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a2, "lnbclka2", 2); 354 DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2); 355 356 DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a4, "lnbclka1", 4); 357 DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a4, "lnbclka2", 4); 358 DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a4, "lnbclka3", 4); 359 360 DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _g4, "lnbclkg2", 4); 361 DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _g4, "lnbclkg3", 4); 362 363 DEFINE_CLK_RPMH_VRM(rf_clk1, _a, "rfclka1", 1); 364 DEFINE_CLK_RPMH_VRM(rf_clk2, _a, "rfclka2", 1); 365 DEFINE_CLK_RPMH_VRM(rf_clk3, _a, "rfclka3", 1); 366 DEFINE_CLK_RPMH_VRM(rf_clk4, _a, "rfclka4", 1); 367 DEFINE_CLK_RPMH_VRM(rf_clk5, _a, "rfclka5", 1); 368 369 DEFINE_CLK_RPMH_VRM(rf_clk1, _d, "rfclkd1", 1); 370 DEFINE_CLK_RPMH_VRM(rf_clk2, _d, "rfclkd2", 1); 371 DEFINE_CLK_RPMH_VRM(rf_clk3, _d, "rfclkd3", 1); 372 DEFINE_CLK_RPMH_VRM(rf_clk4, _d, "rfclkd4", 1); 373 374 DEFINE_CLK_RPMH_VRM(rf_clk3, _a2, "rfclka3", 2); 375 376 DEFINE_CLK_RPMH_VRM(clk1, _a1, "clka1", 1); 377 DEFINE_CLK_RPMH_VRM(clk2, _a1, "clka2", 1); 378 DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1); 379 DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1); 380 DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1); 381 382 DEFINE_CLK_RPMH_VRM(clk3, _a2, "clka3", 2); 383 DEFINE_CLK_RPMH_VRM(clk4, _a2, "clka4", 2); 384 DEFINE_CLK_RPMH_VRM(clk5, _a2, "clka5", 2); 385 DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2); 386 DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2); 387 DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2); 388 389 DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2); 390 391 DEFINE_CLK_RPMH_BCM(ce, "CE0"); 392 DEFINE_CLK_RPMH_BCM(hwkm, "HK0"); 393 DEFINE_CLK_RPMH_BCM(ipa, "IP0"); 394 DEFINE_CLK_RPMH_BCM(pka, "PKA0"); 395 DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0"); 396 397 static struct clk_hw *sar2130p_rpmh_clocks[] = { 398 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw, 399 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw, 400 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 401 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 402 }; 403 404 static const struct clk_rpmh_desc clk_rpmh_sar2130p = { 405 .clks = sar2130p_rpmh_clocks, 406 .num_clks = ARRAY_SIZE(sar2130p_rpmh_clocks), 407 }; 408 409 static struct clk_hw *sdm845_rpmh_clocks[] = { 410 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 411 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 412 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 413 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 414 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 415 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 416 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 417 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 418 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 419 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 420 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 421 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 422 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 423 [RPMH_CE_CLK] = &clk_rpmh_ce.hw, 424 }; 425 426 static const struct clk_rpmh_desc clk_rpmh_sdm845 = { 427 .clks = sdm845_rpmh_clocks, 428 .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks), 429 }; 430 431 static struct clk_hw *sa8775p_rpmh_clocks[] = { 432 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 433 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 434 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw, 435 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 436 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw, 437 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 438 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 439 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 440 }; 441 442 static const struct clk_rpmh_desc clk_rpmh_sa8775p = { 443 .clks = sa8775p_rpmh_clocks, 444 .num_clks = ARRAY_SIZE(sa8775p_rpmh_clocks), 445 }; 446 447 static struct clk_hw *sdm670_rpmh_clocks[] = { 448 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 449 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 450 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 451 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 452 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 453 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 454 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 455 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 456 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 457 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 458 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 459 [RPMH_CE_CLK] = &clk_rpmh_ce.hw, 460 }; 461 462 static const struct clk_rpmh_desc clk_rpmh_sdm670 = { 463 .clks = sdm670_rpmh_clocks, 464 .num_clks = ARRAY_SIZE(sdm670_rpmh_clocks), 465 }; 466 467 static struct clk_hw *sdx55_rpmh_clocks[] = { 468 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 469 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 470 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw, 471 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw, 472 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw, 473 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw, 474 [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, 475 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 476 }; 477 478 static const struct clk_rpmh_desc clk_rpmh_sdx55 = { 479 .clks = sdx55_rpmh_clocks, 480 .num_clks = ARRAY_SIZE(sdx55_rpmh_clocks), 481 }; 482 483 static struct clk_hw *sm8150_rpmh_clocks[] = { 484 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 485 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 486 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 487 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 488 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 489 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 490 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 491 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 492 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 493 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 494 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 495 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 496 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 497 }; 498 499 static const struct clk_rpmh_desc clk_rpmh_sm8150 = { 500 .clks = sm8150_rpmh_clocks, 501 .num_clks = ARRAY_SIZE(sm8150_rpmh_clocks), 502 }; 503 504 static struct clk_hw *sc7180_rpmh_clocks[] = { 505 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 506 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 507 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 508 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 509 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 510 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 511 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 512 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 513 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 514 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 515 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 516 }; 517 518 static const struct clk_rpmh_desc clk_rpmh_sc7180 = { 519 .clks = sc7180_rpmh_clocks, 520 .num_clks = ARRAY_SIZE(sc7180_rpmh_clocks), 521 }; 522 523 static struct clk_hw *sc8180x_rpmh_clocks[] = { 524 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 525 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 526 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 527 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 528 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 529 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 530 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_d.hw, 531 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_d_ao.hw, 532 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_d.hw, 533 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_d_ao.hw, 534 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_d.hw, 535 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_d_ao.hw, 536 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 537 }; 538 539 static const struct clk_rpmh_desc clk_rpmh_sc8180x = { 540 .clks = sc8180x_rpmh_clocks, 541 .num_clks = ARRAY_SIZE(sc8180x_rpmh_clocks), 542 }; 543 544 static struct clk_hw *sm8250_rpmh_clocks[] = { 545 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 546 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 547 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw, 548 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw, 549 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 550 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 551 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 552 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 553 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 554 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 555 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 556 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 557 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 558 }; 559 560 static const struct clk_rpmh_desc clk_rpmh_sm8250 = { 561 .clks = sm8250_rpmh_clocks, 562 .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks), 563 }; 564 565 static struct clk_hw *sm8350_rpmh_clocks[] = { 566 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 567 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 568 [RPMH_DIV_CLK1] = &clk_rpmh_div_clk1_div2.hw, 569 [RPMH_DIV_CLK1_A] = &clk_rpmh_div_clk1_div2_ao.hw, 570 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a2.hw, 571 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a2_ao.hw, 572 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 573 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 574 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 575 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 576 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 577 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 578 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 579 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 580 [RPMH_RF_CLK5] = &clk_rpmh_rf_clk5_a.hw, 581 [RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a_ao.hw, 582 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 583 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 584 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 585 }; 586 587 static const struct clk_rpmh_desc clk_rpmh_sm8350 = { 588 .clks = sm8350_rpmh_clocks, 589 .num_clks = ARRAY_SIZE(sm8350_rpmh_clocks), 590 }; 591 592 static struct clk_hw *sc8280xp_rpmh_clocks[] = { 593 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 594 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 595 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 596 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 597 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 598 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 599 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 600 }; 601 602 static const struct clk_rpmh_desc clk_rpmh_sc8280xp = { 603 .clks = sc8280xp_rpmh_clocks, 604 .num_clks = ARRAY_SIZE(sc8280xp_rpmh_clocks), 605 }; 606 607 static struct clk_hw *sm8450_rpmh_clocks[] = { 608 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 609 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 610 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw, 611 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw, 612 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a4.hw, 613 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw, 614 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 615 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 616 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 617 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 618 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 619 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 620 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 621 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 622 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 623 }; 624 625 static const struct clk_rpmh_desc clk_rpmh_sm8450 = { 626 .clks = sm8450_rpmh_clocks, 627 .num_clks = ARRAY_SIZE(sm8450_rpmh_clocks), 628 }; 629 630 static struct clk_hw *sm8550_rpmh_clocks[] = { 631 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 632 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 633 [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, 634 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, 635 [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw, 636 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw, 637 [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, 638 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, 639 [RPMH_RF_CLK1] = &clk_rpmh_clk1_a1.hw, 640 [RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_ao.hw, 641 [RPMH_RF_CLK2] = &clk_rpmh_clk2_a1.hw, 642 [RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_ao.hw, 643 [RPMH_RF_CLK3] = &clk_rpmh_clk3_a1.hw, 644 [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a1_ao.hw, 645 [RPMH_RF_CLK4] = &clk_rpmh_clk4_a1.hw, 646 [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a1_ao.hw, 647 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 648 }; 649 650 static const struct clk_rpmh_desc clk_rpmh_sm8550 = { 651 .clks = sm8550_rpmh_clocks, 652 .num_clks = ARRAY_SIZE(sm8550_rpmh_clocks), 653 .clka_optional = true, 654 }; 655 656 static struct clk_hw *sm8650_rpmh_clocks[] = { 657 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 658 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 659 [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, 660 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, 661 [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw, 662 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw, 663 [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, 664 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, 665 [RPMH_RF_CLK1] = &clk_rpmh_clk1_a1.hw, 666 [RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_ao.hw, 667 [RPMH_RF_CLK2] = &clk_rpmh_clk2_a1.hw, 668 [RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_ao.hw, 669 /* 670 * The clka3 RPMh resource is missing in cmd-db 671 * for current platforms, while the clka3 exists 672 * on the PMK8550, the clock is unconnected and 673 * unused. 674 */ 675 [RPMH_RF_CLK4] = &clk_rpmh_clk4_a2.hw, 676 [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a2_ao.hw, 677 [RPMH_RF_CLK5] = &clk_rpmh_clk5_a2.hw, 678 [RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a2_ao.hw, 679 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 680 }; 681 682 static const struct clk_rpmh_desc clk_rpmh_sm8650 = { 683 .clks = sm8650_rpmh_clocks, 684 .num_clks = ARRAY_SIZE(sm8650_rpmh_clocks), 685 .clka_optional = true, 686 }; 687 688 static struct clk_hw *sc7280_rpmh_clocks[] = { 689 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 690 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 691 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 692 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 693 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 694 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 695 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 696 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 697 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 698 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 699 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 700 [RPMH_PKA_CLK] = &clk_rpmh_pka.hw, 701 [RPMH_HWKM_CLK] = &clk_rpmh_hwkm.hw, 702 }; 703 704 static const struct clk_rpmh_desc clk_rpmh_sc7280 = { 705 .clks = sc7280_rpmh_clocks, 706 .num_clks = ARRAY_SIZE(sc7280_rpmh_clocks), 707 }; 708 709 static struct clk_hw *sm6350_rpmh_clocks[] = { 710 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 711 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 712 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_g4.hw, 713 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_g4_ao.hw, 714 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_g4.hw, 715 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_g4_ao.hw, 716 [RPMH_QLINK_CLK] = &clk_rpmh_qlink_div4.hw, 717 [RPMH_QLINK_CLK_A] = &clk_rpmh_qlink_div4_ao.hw, 718 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 719 }; 720 721 static const struct clk_rpmh_desc clk_rpmh_sm6350 = { 722 .clks = sm6350_rpmh_clocks, 723 .num_clks = ARRAY_SIZE(sm6350_rpmh_clocks), 724 }; 725 726 static struct clk_hw *sdx65_rpmh_clocks[] = { 727 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 728 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 729 [RPMH_LN_BB_CLK1] = &clk_rpmh_ln_bb_clk1_a4.hw, 730 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_ln_bb_clk1_a4_ao.hw, 731 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 732 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 733 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 734 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 735 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 736 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 737 [RPMH_RF_CLK4] = &clk_rpmh_rf_clk4_a.hw, 738 [RPMH_RF_CLK4_A] = &clk_rpmh_rf_clk4_a_ao.hw, 739 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 740 [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, 741 }; 742 743 static const struct clk_rpmh_desc clk_rpmh_sdx65 = { 744 .clks = sdx65_rpmh_clocks, 745 .num_clks = ARRAY_SIZE(sdx65_rpmh_clocks), 746 }; 747 748 static struct clk_hw *qdu1000_rpmh_clocks[] = { 749 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw, 750 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw, 751 }; 752 753 static const struct clk_rpmh_desc clk_rpmh_qdu1000 = { 754 .clks = qdu1000_rpmh_clocks, 755 .num_clks = ARRAY_SIZE(qdu1000_rpmh_clocks), 756 }; 757 758 static struct clk_hw *sdx75_rpmh_clocks[] = { 759 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 760 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 761 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 762 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 763 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 764 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 765 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a.hw, 766 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a_ao.hw, 767 [RPMH_QPIC_CLK] = &clk_rpmh_qpic_clk.hw, 768 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 769 }; 770 771 static const struct clk_rpmh_desc clk_rpmh_sdx75 = { 772 .clks = sdx75_rpmh_clocks, 773 .num_clks = ARRAY_SIZE(sdx75_rpmh_clocks), 774 }; 775 776 static struct clk_hw *sm4450_rpmh_clocks[] = { 777 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div4.hw, 778 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div4_ao.hw, 779 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a4.hw, 780 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a4_ao.hw, 781 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a4.hw, 782 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a4_ao.hw, 783 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 784 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 785 [RPMH_RF_CLK5] = &clk_rpmh_rf_clk5_a.hw, 786 [RPMH_RF_CLK5_A] = &clk_rpmh_rf_clk5_a_ao.hw, 787 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 788 }; 789 790 static const struct clk_rpmh_desc clk_rpmh_sm4450 = { 791 .clks = sm4450_rpmh_clocks, 792 .num_clks = ARRAY_SIZE(sm4450_rpmh_clocks), 793 }; 794 795 static struct clk_hw *x1e80100_rpmh_clocks[] = { 796 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 797 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 798 [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, 799 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, 800 [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw, 801 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw, 802 [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, 803 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, 804 [RPMH_RF_CLK3] = &clk_rpmh_clk3_a2.hw, 805 [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a2_ao.hw, 806 [RPMH_RF_CLK4] = &clk_rpmh_clk4_a2.hw, 807 [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a2_ao.hw, 808 [RPMH_RF_CLK5] = &clk_rpmh_clk5_a2.hw, 809 [RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a2_ao.hw, 810 }; 811 812 static const struct clk_rpmh_desc clk_rpmh_x1e80100 = { 813 .clks = x1e80100_rpmh_clocks, 814 .num_clks = ARRAY_SIZE(x1e80100_rpmh_clocks), 815 }; 816 817 static struct clk_hw *qcs615_rpmh_clocks[] = { 818 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 819 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 820 [RPMH_LN_BB_CLK2] = &clk_rpmh_ln_bb_clk2_a2.hw, 821 [RPMH_LN_BB_CLK2_A] = &clk_rpmh_ln_bb_clk2_a2_ao.hw, 822 [RPMH_LN_BB_CLK3] = &clk_rpmh_ln_bb_clk3_a2.hw, 823 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_ln_bb_clk3_a2_ao.hw, 824 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 825 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 826 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 827 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 828 }; 829 830 static const struct clk_rpmh_desc clk_rpmh_qcs615 = { 831 .clks = qcs615_rpmh_clocks, 832 .num_clks = ARRAY_SIZE(qcs615_rpmh_clocks), 833 }; 834 835 static struct clk_hw *sm8750_rpmh_clocks[] = { 836 [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, 837 [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, 838 [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, 839 [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, 840 [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, 841 [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, 842 [RPMH_RF_CLK1] = &clk_rpmh_rf_clk1_a.hw, 843 [RPMH_RF_CLK1_A] = &clk_rpmh_rf_clk1_a_ao.hw, 844 [RPMH_RF_CLK2] = &clk_rpmh_rf_clk2_a.hw, 845 [RPMH_RF_CLK2_A] = &clk_rpmh_rf_clk2_a_ao.hw, 846 [RPMH_RF_CLK3] = &clk_rpmh_rf_clk3_a2.hw, 847 [RPMH_RF_CLK3_A] = &clk_rpmh_rf_clk3_a2_ao.hw, 848 [RPMH_IPA_CLK] = &clk_rpmh_ipa.hw, 849 }; 850 851 static const struct clk_rpmh_desc clk_rpmh_sm8750 = { 852 .clks = sm8750_rpmh_clocks, 853 .num_clks = ARRAY_SIZE(sm8750_rpmh_clocks), 854 .clka_optional = true, 855 }; 856 857 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, 858 void *data) 859 { 860 struct clk_rpmh_desc *rpmh = data; 861 unsigned int idx = clkspec->args[0]; 862 863 if (idx >= rpmh->num_clks) { 864 pr_err("%s: invalid index %u\n", __func__, idx); 865 return ERR_PTR(-EINVAL); 866 } 867 868 return rpmh->clks[idx]; 869 } 870 871 static int clk_rpmh_probe(struct platform_device *pdev) 872 { 873 struct clk_hw **hw_clks; 874 struct clk_rpmh *rpmh_clk; 875 const struct clk_rpmh_desc *desc; 876 int ret, i; 877 878 desc = of_device_get_match_data(&pdev->dev); 879 if (!desc) 880 return -ENODEV; 881 882 hw_clks = desc->clks; 883 884 for (i = 0; i < desc->num_clks; i++) { 885 const char *name; 886 u32 res_addr; 887 size_t aux_data_len; 888 const struct bcm_db *data; 889 890 if (!hw_clks[i]) 891 continue; 892 893 name = hw_clks[i]->init->name; 894 895 rpmh_clk = to_clk_rpmh(hw_clks[i]); 896 res_addr = cmd_db_read_addr(rpmh_clk->res_name); 897 if (!res_addr) { 898 hw_clks[i] = NULL; 899 900 if (desc->clka_optional && 901 !strncmp(rpmh_clk->res_name, "clka", sizeof("clka") - 1)) 902 continue; 903 904 dev_err(&pdev->dev, "missing RPMh resource address for %s\n", 905 rpmh_clk->res_name); 906 return -ENODEV; 907 } 908 909 data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len); 910 if (IS_ERR(data)) { 911 ret = PTR_ERR(data); 912 dev_err(&pdev->dev, 913 "error reading RPMh aux data for %s (%d)\n", 914 rpmh_clk->res_name, ret); 915 return ret; 916 } 917 918 /* Convert unit from Khz to Hz */ 919 if (aux_data_len == sizeof(*data)) 920 rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL; 921 922 rpmh_clk->res_addr += res_addr; 923 rpmh_clk->dev = &pdev->dev; 924 925 ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]); 926 if (ret) { 927 dev_err(&pdev->dev, "failed to register %s\n", name); 928 return ret; 929 } 930 } 931 932 /* typecast to silence compiler warning */ 933 ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get, 934 (void *)desc); 935 if (ret) { 936 dev_err(&pdev->dev, "Failed to add clock provider\n"); 937 return ret; 938 } 939 940 dev_dbg(&pdev->dev, "Registered RPMh clocks\n"); 941 942 return 0; 943 } 944 945 static const struct of_device_id clk_rpmh_match_table[] = { 946 { .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615}, 947 { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000}, 948 { .compatible = "qcom,sa8775p-rpmh-clk", .data = &clk_rpmh_sa8775p}, 949 { .compatible = "qcom,sar2130p-rpmh-clk", .data = &clk_rpmh_sar2130p}, 950 { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180}, 951 { .compatible = "qcom,sc7280-rpmh-clk", .data = &clk_rpmh_sc7280}, 952 { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, 953 { .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp}, 954 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, 955 { .compatible = "qcom,sdm670-rpmh-clk", .data = &clk_rpmh_sdm670}, 956 { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55}, 957 { .compatible = "qcom,sdx65-rpmh-clk", .data = &clk_rpmh_sdx65}, 958 { .compatible = "qcom,sdx75-rpmh-clk", .data = &clk_rpmh_sdx75}, 959 { .compatible = "qcom,sm4450-rpmh-clk", .data = &clk_rpmh_sm4450}, 960 { .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350}, 961 { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150}, 962 { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, 963 { .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350}, 964 { .compatible = "qcom,sm8450-rpmh-clk", .data = &clk_rpmh_sm8450}, 965 { .compatible = "qcom,sm8550-rpmh-clk", .data = &clk_rpmh_sm8550}, 966 { .compatible = "qcom,sm8650-rpmh-clk", .data = &clk_rpmh_sm8650}, 967 { .compatible = "qcom,sm8750-rpmh-clk", .data = &clk_rpmh_sm8750}, 968 { .compatible = "qcom,x1e80100-rpmh-clk", .data = &clk_rpmh_x1e80100}, 969 { } 970 }; 971 MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); 972 973 static struct platform_driver clk_rpmh_driver = { 974 .probe = clk_rpmh_probe, 975 .driver = { 976 .name = "clk-rpmh", 977 .of_match_table = clk_rpmh_match_table, 978 }, 979 }; 980 981 static int __init clk_rpmh_init(void) 982 { 983 return platform_driver_register(&clk_rpmh_driver); 984 } 985 core_initcall(clk_rpmh_init); 986 987 static void __exit clk_rpmh_exit(void) 988 { 989 platform_driver_unregister(&clk_rpmh_driver); 990 } 991 module_exit(clk_rpmh_exit); 992 993 MODULE_DESCRIPTION("QCOM RPMh Clock Driver"); 994 MODULE_LICENSE("GPL v2"); 995