1*fcaf2036SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 223b5e15aSShawn Guo /* 323b5e15aSShawn Guo * Copyright 2012 Freescale Semiconductor, Inc. 423b5e15aSShawn Guo */ 523b5e15aSShawn Guo 623b5e15aSShawn Guo #ifndef __MXS_CLK_H 723b5e15aSShawn Guo #define __MXS_CLK_H 823b5e15aSShawn Guo 9bb0bf354SStephen Boyd struct clk; 10bb0bf354SStephen Boyd 1123b5e15aSShawn Guo #include <linux/clk-provider.h> 1223b5e15aSShawn Guo #include <linux/spinlock.h> 1323b5e15aSShawn Guo 1423b5e15aSShawn Guo #define SET 0x4 1523b5e15aSShawn Guo #define CLR 0x8 1623b5e15aSShawn Guo 1723b5e15aSShawn Guo extern spinlock_t mxs_lock; 1823b5e15aSShawn Guo 1923b5e15aSShawn Guo int mxs_clk_wait(void __iomem *reg, u8 shift); 2023b5e15aSShawn Guo 2123b5e15aSShawn Guo struct clk *mxs_clk_pll(const char *name, const char *parent_name, 2223b5e15aSShawn Guo void __iomem *base, u8 power, unsigned long rate); 2323b5e15aSShawn Guo 2423b5e15aSShawn Guo struct clk *mxs_clk_ref(const char *name, const char *parent_name, 2523b5e15aSShawn Guo void __iomem *reg, u8 idx); 2623b5e15aSShawn Guo 2723b5e15aSShawn Guo struct clk *mxs_clk_div(const char *name, const char *parent_name, 2823b5e15aSShawn Guo void __iomem *reg, u8 shift, u8 width, u8 busy); 2923b5e15aSShawn Guo 3023b5e15aSShawn Guo struct clk *mxs_clk_frac(const char *name, const char *parent_name, 3123b5e15aSShawn Guo void __iomem *reg, u8 shift, u8 width, u8 busy); 3223b5e15aSShawn Guo 3323b5e15aSShawn Guo static inline struct clk *mxs_clk_fixed(const char *name, int rate) 3423b5e15aSShawn Guo { 350f4207f3SStephen Boyd return clk_register_fixed_rate(NULL, name, NULL, 0, rate); 3623b5e15aSShawn Guo } 3723b5e15aSShawn Guo 3823b5e15aSShawn Guo static inline struct clk *mxs_clk_gate(const char *name, 3923b5e15aSShawn Guo const char *parent_name, void __iomem *reg, u8 shift) 4023b5e15aSShawn Guo { 4123b5e15aSShawn Guo return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT, 4223b5e15aSShawn Guo reg, shift, CLK_GATE_SET_TO_DISABLE, 4323b5e15aSShawn Guo &mxs_lock); 4423b5e15aSShawn Guo } 4523b5e15aSShawn Guo 4623b5e15aSShawn Guo static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, 474a1caed3SUwe Kleine-König u8 shift, u8 width, const char *const *parent_names, int num_parents) 4823b5e15aSShawn Guo { 4923b5e15aSShawn Guo return clk_register_mux(NULL, name, parent_names, num_parents, 50819c1de3SJames Hogan CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 51819c1de3SJames Hogan reg, shift, width, 0, &mxs_lock); 5223b5e15aSShawn Guo } 5323b5e15aSShawn Guo 5423b5e15aSShawn Guo static inline struct clk *mxs_clk_fixed_factor(const char *name, 5523b5e15aSShawn Guo const char *parent_name, unsigned int mult, unsigned int div) 5623b5e15aSShawn Guo { 5723b5e15aSShawn Guo return clk_register_fixed_factor(NULL, name, parent_name, 5823b5e15aSShawn Guo CLK_SET_RATE_PARENT, mult, div); 5923b5e15aSShawn Guo } 6023b5e15aSShawn Guo 6123b5e15aSShawn Guo #endif /* __MXS_CLK_H */ 62