1 /* 2 * Ingenic SoC CGU driver 3 * 4 * Copyright (c) 2013-2015 Imagination Technologies 5 * Author: Paul Burton <paul.burton@mips.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #ifndef __DRIVERS_CLK_INGENIC_CGU_H__ 19 #define __DRIVERS_CLK_INGENIC_CGU_H__ 20 21 #include <linux/bitops.h> 22 #include <linux/of.h> 23 #include <linux/spinlock.h> 24 25 /** 26 * struct ingenic_cgu_pll_info - information about a PLL 27 * @reg: the offset of the PLL's control register within the CGU 28 * @m_shift: the number of bits to shift the multiplier value by (ie. the 29 * index of the lowest bit of the multiplier value in the PLL's 30 * control register) 31 * @m_bits: the size of the multiplier field in bits 32 * @m_offset: the multiplier value which encodes to 0 in the PLL's control 33 * register 34 * @n_shift: the number of bits to shift the divider value by (ie. the 35 * index of the lowest bit of the divider value in the PLL's 36 * control register) 37 * @n_bits: the size of the divider field in bits 38 * @n_offset: the divider value which encodes to 0 in the PLL's control 39 * register 40 * @od_shift: the number of bits to shift the post-VCO divider value by (ie. 41 * the index of the lowest bit of the post-VCO divider value in 42 * the PLL's control register) 43 * @od_bits: the size of the post-VCO divider field in bits 44 * @od_max: the maximum post-VCO divider value 45 * @od_encoding: a pointer to an array mapping post-VCO divider values to 46 * their encoded values in the PLL control register, or -1 for 47 * unsupported values 48 * @bypass_bit: the index of the bypass bit in the PLL control register 49 * @enable_bit: the index of the enable bit in the PLL control register 50 * @stable_bit: the index of the stable bit in the PLL control register 51 * @no_bypass_bit: if set, the PLL has no bypass functionality 52 */ 53 struct ingenic_cgu_pll_info { 54 unsigned reg; 55 const s8 *od_encoding; 56 u8 m_shift, m_bits, m_offset; 57 u8 n_shift, n_bits, n_offset; 58 u8 od_shift, od_bits, od_max; 59 u8 bypass_bit; 60 u8 enable_bit; 61 u8 stable_bit; 62 bool no_bypass_bit; 63 }; 64 65 /** 66 * struct ingenic_cgu_mux_info - information about a clock mux 67 * @reg: offset of the mux control register within the CGU 68 * @shift: number of bits to shift the mux value by (ie. the index of 69 * the lowest bit of the mux value within its control register) 70 * @bits: the size of the mux value in bits 71 */ 72 struct ingenic_cgu_mux_info { 73 unsigned reg; 74 u8 shift; 75 u8 bits; 76 }; 77 78 /** 79 * struct ingenic_cgu_div_info - information about a divider 80 * @reg: offset of the divider control register within the CGU 81 * @shift: number of bits to left shift the divide value by (ie. the index of 82 * the lowest bit of the divide value within its control register) 83 * @div: number to divide the divider value by (i.e. if the 84 * effective divider value is the value written to the register 85 * multiplied by some constant) 86 * @bits: the size of the divide value in bits 87 * @ce_bit: the index of the change enable bit within reg, or -1 if there 88 * isn't one 89 * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one 90 * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one 91 * @div_table: optional table to map the value read from the register to the 92 * actual divider value 93 */ 94 struct ingenic_cgu_div_info { 95 unsigned reg; 96 u8 shift; 97 u8 div; 98 u8 bits; 99 s8 ce_bit; 100 s8 busy_bit; 101 s8 stop_bit; 102 const u8 *div_table; 103 }; 104 105 /** 106 * struct ingenic_cgu_fixdiv_info - information about a fixed divider 107 * @div: the divider applied to the parent clock 108 */ 109 struct ingenic_cgu_fixdiv_info { 110 unsigned div; 111 }; 112 113 /** 114 * struct ingenic_cgu_gate_info - information about a clock gate 115 * @reg: offset of the gate control register within the CGU 116 * @bit: offset of the bit in the register that controls the gate 117 * @clear_to_gate: if set, the clock is gated when the bit is cleared 118 * @delay_us: delay in microseconds after which the clock is considered stable 119 */ 120 struct ingenic_cgu_gate_info { 121 unsigned reg; 122 u8 bit; 123 bool clear_to_gate; 124 u16 delay_us; 125 }; 126 127 /** 128 * struct ingenic_cgu_custom_info - information about a custom (SoC) clock 129 * @clk_ops: custom clock operation callbacks 130 */ 131 struct ingenic_cgu_custom_info { 132 const struct clk_ops *clk_ops; 133 }; 134 135 /** 136 * struct ingenic_cgu_clk_info - information about a clock 137 * @name: name of the clock 138 * @type: a bitmask formed from CGU_CLK_* values 139 * @parents: an array of the indices of potential parents of this clock 140 * within the clock_info array of the CGU, or -1 in entries 141 * which correspond to no valid parent 142 * @pll: information valid if type includes CGU_CLK_PLL 143 * @gate: information valid if type includes CGU_CLK_GATE 144 * @mux: information valid if type includes CGU_CLK_MUX 145 * @div: information valid if type includes CGU_CLK_DIV 146 * @fixdiv: information valid if type includes CGU_CLK_FIXDIV 147 * @custom: information valid if type includes CGU_CLK_CUSTOM 148 */ 149 struct ingenic_cgu_clk_info { 150 const char *name; 151 152 enum { 153 CGU_CLK_NONE = 0, 154 CGU_CLK_EXT = BIT(0), 155 CGU_CLK_PLL = BIT(1), 156 CGU_CLK_GATE = BIT(2), 157 CGU_CLK_MUX = BIT(3), 158 CGU_CLK_MUX_GLITCHFREE = BIT(4), 159 CGU_CLK_DIV = BIT(5), 160 CGU_CLK_FIXDIV = BIT(6), 161 CGU_CLK_CUSTOM = BIT(7), 162 } type; 163 164 int parents[4]; 165 166 union { 167 struct ingenic_cgu_pll_info pll; 168 169 struct { 170 struct ingenic_cgu_gate_info gate; 171 struct ingenic_cgu_mux_info mux; 172 struct ingenic_cgu_div_info div; 173 struct ingenic_cgu_fixdiv_info fixdiv; 174 }; 175 176 struct ingenic_cgu_custom_info custom; 177 }; 178 }; 179 180 /** 181 * struct ingenic_cgu - data about the CGU 182 * @np: the device tree node that caused the CGU to be probed 183 * @base: the ioremap'ed base address of the CGU registers 184 * @clock_info: an array containing information about implemented clocks 185 * @clocks: used to provide clocks to DT, allows lookup of struct clk* 186 * @lock: lock to be held whilst manipulating CGU registers 187 */ 188 struct ingenic_cgu { 189 struct device_node *np; 190 void __iomem *base; 191 192 const struct ingenic_cgu_clk_info *clock_info; 193 struct clk_onecell_data clocks; 194 195 spinlock_t lock; 196 }; 197 198 /** 199 * struct ingenic_clk - private data for a clock 200 * @hw: see Documentation/driver-api/clk.rst 201 * @cgu: a pointer to the CGU data 202 * @idx: the index of this clock in cgu->clock_info 203 */ 204 struct ingenic_clk { 205 struct clk_hw hw; 206 struct ingenic_cgu *cgu; 207 unsigned idx; 208 }; 209 210 #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw) 211 212 /** 213 * ingenic_cgu_new() - create a new CGU instance 214 * @clock_info: an array of clock information structures describing the clocks 215 * which are implemented by the CGU 216 * @num_clocks: the number of entries in clock_info 217 * @np: the device tree node which causes this CGU to be probed 218 * 219 * Return: a pointer to the CGU instance if initialisation is successful, 220 * otherwise NULL. 221 */ 222 struct ingenic_cgu * 223 ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, 224 unsigned num_clocks, struct device_node *np); 225 226 /** 227 * ingenic_cgu_register_clocks() - Registers the clocks 228 * @cgu: pointer to cgu data 229 * 230 * Register the clocks described by the CGU with the common clock framework. 231 * 232 * Return: 0 on success or -errno if unsuccesful. 233 */ 234 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu); 235 236 #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */ 237