1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020-2024 Intel Corporation 4 */ 5 6 #include <linux/firmware.h> 7 #include <linux/highmem.h> 8 #include <linux/moduleparam.h> 9 #include <linux/pci.h> 10 11 #include "vpu_boot_api.h" 12 #include "ivpu_drv.h" 13 #include "ivpu_fw.h" 14 #include "ivpu_fw_log.h" 15 #include "ivpu_gem.h" 16 #include "ivpu_hw.h" 17 #include "ivpu_ipc.h" 18 #include "ivpu_pm.h" 19 20 #define FW_GLOBAL_MEM_START (2ull * SZ_1G) 21 #define FW_GLOBAL_MEM_END (3ull * SZ_1G) 22 #define FW_SHARED_MEM_SIZE SZ_256M /* Must be aligned to FW_SHARED_MEM_ALIGNMENT */ 23 #define FW_SHARED_MEM_ALIGNMENT SZ_128K /* VPU MTRR limitation */ 24 #define FW_RUNTIME_MAX_SIZE SZ_512M 25 #define FW_SHAVE_NN_MAX_SIZE SZ_2M 26 #define FW_RUNTIME_MIN_ADDR (FW_GLOBAL_MEM_START) 27 #define FW_RUNTIME_MAX_ADDR (FW_GLOBAL_MEM_END - FW_SHARED_MEM_SIZE) 28 #define FW_FILE_IMAGE_OFFSET (VPU_FW_HEADER_SIZE + FW_VERSION_HEADER_SIZE) 29 30 #define WATCHDOG_MSS_REDIRECT 32 31 #define WATCHDOG_NCE_REDIRECT 33 32 33 #define ADDR_TO_L2_CACHE_CFG(addr) ((addr) >> 31) 34 35 /* Check if FW API is compatible with the driver */ 36 #define IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, name, min_major) \ 37 ivpu_fw_check_api(vdev, fw_hdr, #name, \ 38 VPU_##name##_API_VER_INDEX, \ 39 VPU_##name##_API_VER_MAJOR, \ 40 VPU_##name##_API_VER_MINOR, min_major) 41 42 /* Check if API version is lower that the given version */ 43 #define IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, name, major, minor) \ 44 ivpu_fw_check_api_ver_lt(vdev, fw_hdr, #name, VPU_##name##_API_VER_INDEX, major, minor) 45 46 #define IVPU_FOCUS_PRESENT_TIMER_MS 1000 47 48 static char *ivpu_firmware; 49 #if IS_ENABLED(CONFIG_DRM_ACCEL_IVPU_DEBUG) 50 module_param_named_unsafe(firmware, ivpu_firmware, charp, 0644); 51 MODULE_PARM_DESC(firmware, "NPU firmware binary in /lib/firmware/.."); 52 #endif 53 54 static struct { 55 int gen; 56 const char *name; 57 } fw_names[] = { 58 { IVPU_HW_IP_37XX, "vpu_37xx.bin" }, 59 { IVPU_HW_IP_37XX, "intel/vpu/vpu_37xx_v0.0.bin" }, 60 { IVPU_HW_IP_40XX, "vpu_40xx.bin" }, 61 { IVPU_HW_IP_40XX, "intel/vpu/vpu_40xx_v0.0.bin" }, 62 { IVPU_HW_IP_50XX, "vpu_50xx.bin" }, 63 { IVPU_HW_IP_50XX, "intel/vpu/vpu_50xx_v0.0.bin" }, 64 }; 65 66 /* Production fw_names from the table above */ 67 MODULE_FIRMWARE("intel/vpu/vpu_37xx_v0.0.bin"); 68 MODULE_FIRMWARE("intel/vpu/vpu_40xx_v0.0.bin"); 69 MODULE_FIRMWARE("intel/vpu/vpu_50xx_v0.0.bin"); 70 71 static int ivpu_fw_request(struct ivpu_device *vdev) 72 { 73 int ret = -ENOENT; 74 int i; 75 76 if (ivpu_firmware) { 77 ret = request_firmware(&vdev->fw->file, ivpu_firmware, vdev->drm.dev); 78 if (!ret) 79 vdev->fw->name = ivpu_firmware; 80 return ret; 81 } 82 83 for (i = 0; i < ARRAY_SIZE(fw_names); i++) { 84 if (fw_names[i].gen != ivpu_hw_ip_gen(vdev)) 85 continue; 86 87 ret = firmware_request_nowarn(&vdev->fw->file, fw_names[i].name, vdev->drm.dev); 88 if (!ret) { 89 vdev->fw->name = fw_names[i].name; 90 return 0; 91 } 92 } 93 94 ivpu_err(vdev, "Failed to request firmware: %d\n", ret); 95 return ret; 96 } 97 98 static int 99 ivpu_fw_check_api(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr, 100 const char *str, int index, u16 expected_major, u16 expected_minor, 101 u16 min_major) 102 { 103 u16 major = (u16)(fw_hdr->api_version[index] >> 16); 104 u16 minor = (u16)(fw_hdr->api_version[index]); 105 106 if (major < min_major) { 107 ivpu_err(vdev, "Incompatible FW %s API version: %d.%d, required %d.0 or later\n", 108 str, major, minor, min_major); 109 return -EINVAL; 110 } 111 if (major != expected_major) { 112 ivpu_warn(vdev, "Major FW %s API version different: %d.%d (expected %d.%d)\n", 113 str, major, minor, expected_major, expected_minor); 114 } 115 ivpu_dbg(vdev, FW_BOOT, "FW %s API version: %d.%d (expected %d.%d)\n", 116 str, major, minor, expected_major, expected_minor); 117 118 return 0; 119 } 120 121 static bool 122 ivpu_fw_check_api_ver_lt(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr, 123 const char *str, int index, u16 major, u16 minor) 124 { 125 u16 fw_major = (u16)(fw_hdr->api_version[index] >> 16); 126 u16 fw_minor = (u16)(fw_hdr->api_version[index]); 127 128 if (fw_major < major || (fw_major == major && fw_minor < minor)) 129 return true; 130 131 return false; 132 } 133 134 static bool is_within_range(u64 addr, size_t size, u64 range_start, size_t range_size) 135 { 136 if (addr < range_start || addr + size > range_start + range_size) 137 return false; 138 139 return true; 140 } 141 142 static u32 143 ivpu_fw_sched_mode_select(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr) 144 { 145 if (ivpu_sched_mode != IVPU_SCHED_MODE_AUTO) 146 return ivpu_sched_mode; 147 148 if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, JSM, 3, 24)) 149 return VPU_SCHEDULING_MODE_OS; 150 151 return VPU_SCHEDULING_MODE_HW; 152 } 153 154 static int ivpu_fw_parse(struct ivpu_device *vdev) 155 { 156 struct ivpu_fw_info *fw = vdev->fw; 157 const struct vpu_firmware_header *fw_hdr = (const void *)fw->file->data; 158 u64 runtime_addr, image_load_addr, runtime_size, image_size; 159 160 if (fw->file->size <= FW_FILE_IMAGE_OFFSET) { 161 ivpu_err(vdev, "Firmware file is too small: %zu\n", fw->file->size); 162 return -EINVAL; 163 } 164 165 if (fw_hdr->header_version != VPU_FW_HEADER_VERSION) { 166 ivpu_err(vdev, "Invalid firmware header version: %u\n", fw_hdr->header_version); 167 return -EINVAL; 168 } 169 170 runtime_addr = fw_hdr->boot_params_load_address; 171 runtime_size = fw_hdr->runtime_size; 172 image_load_addr = fw_hdr->image_load_address; 173 image_size = fw_hdr->image_size; 174 175 if (runtime_addr < FW_RUNTIME_MIN_ADDR || runtime_addr > FW_RUNTIME_MAX_ADDR) { 176 ivpu_err(vdev, "Invalid firmware runtime address: 0x%llx\n", runtime_addr); 177 return -EINVAL; 178 } 179 180 if (runtime_size < fw->file->size || runtime_size > FW_RUNTIME_MAX_SIZE) { 181 ivpu_err(vdev, "Invalid firmware runtime size: %llu\n", runtime_size); 182 return -EINVAL; 183 } 184 185 if (FW_FILE_IMAGE_OFFSET + image_size > fw->file->size) { 186 ivpu_err(vdev, "Invalid image size: %llu\n", image_size); 187 return -EINVAL; 188 } 189 190 if (image_load_addr < runtime_addr || 191 image_load_addr + image_size > runtime_addr + runtime_size) { 192 ivpu_err(vdev, "Invalid firmware load address size: 0x%llx and size %llu\n", 193 image_load_addr, image_size); 194 return -EINVAL; 195 } 196 197 if (fw_hdr->shave_nn_fw_size > FW_SHAVE_NN_MAX_SIZE) { 198 ivpu_err(vdev, "SHAVE NN firmware is too big: %u\n", fw_hdr->shave_nn_fw_size); 199 return -EINVAL; 200 } 201 202 if (fw_hdr->entry_point < image_load_addr || 203 fw_hdr->entry_point >= image_load_addr + image_size) { 204 ivpu_err(vdev, "Invalid entry point: 0x%llx\n", fw_hdr->entry_point); 205 return -EINVAL; 206 } 207 ivpu_dbg(vdev, FW_BOOT, "Header version: 0x%x, format 0x%x\n", 208 fw_hdr->header_version, fw_hdr->image_format); 209 210 if (!scnprintf(fw->version, sizeof(fw->version), "%s", fw->file->data + VPU_FW_HEADER_SIZE)) 211 ivpu_warn(vdev, "Missing firmware version\n"); 212 213 ivpu_info(vdev, "Firmware: %s, version: %s\n", fw->name, fw->version); 214 215 if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, BOOT, 3)) 216 return -EINVAL; 217 if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, JSM, 3)) 218 return -EINVAL; 219 220 fw->runtime_addr = runtime_addr; 221 fw->runtime_size = runtime_size; 222 fw->image_load_offset = image_load_addr - runtime_addr; 223 fw->image_size = image_size; 224 fw->shave_nn_size = PAGE_ALIGN(fw_hdr->shave_nn_fw_size); 225 226 fw->cold_boot_entry_point = fw_hdr->entry_point; 227 fw->entry_point = fw->cold_boot_entry_point; 228 229 fw->trace_level = min_t(u32, ivpu_fw_log_level, IVPU_FW_LOG_FATAL); 230 fw->trace_destination_mask = VPU_TRACE_DESTINATION_VERBOSE_TRACING; 231 fw->trace_hw_component_mask = -1; 232 233 fw->dvfs_mode = 0; 234 235 fw->sched_mode = ivpu_fw_sched_mode_select(vdev, fw_hdr); 236 fw->primary_preempt_buf_size = fw_hdr->preemption_buffer_1_size; 237 fw->secondary_preempt_buf_size = fw_hdr->preemption_buffer_2_size; 238 ivpu_info(vdev, "Scheduler mode: %s\n", fw->sched_mode ? "HW" : "OS"); 239 240 if (fw_hdr->ro_section_start_address && !is_within_range(fw_hdr->ro_section_start_address, 241 fw_hdr->ro_section_size, 242 fw_hdr->image_load_address, 243 fw_hdr->image_size)) { 244 ivpu_err(vdev, "Invalid read-only section: start address 0x%llx, size %u\n", 245 fw_hdr->ro_section_start_address, fw_hdr->ro_section_size); 246 return -EINVAL; 247 } 248 249 fw->read_only_addr = fw_hdr->ro_section_start_address; 250 fw->read_only_size = fw_hdr->ro_section_size; 251 252 ivpu_dbg(vdev, FW_BOOT, "Size: file %lu image %u runtime %u shavenn %u\n", 253 fw->file->size, fw->image_size, fw->runtime_size, fw->shave_nn_size); 254 ivpu_dbg(vdev, FW_BOOT, "Address: runtime 0x%llx, load 0x%llx, entry point 0x%llx\n", 255 fw->runtime_addr, image_load_addr, fw->entry_point); 256 ivpu_dbg(vdev, FW_BOOT, "Read-only section: address 0x%llx, size %u\n", 257 fw->read_only_addr, fw->read_only_size); 258 259 return 0; 260 } 261 262 static void ivpu_fw_release(struct ivpu_device *vdev) 263 { 264 release_firmware(vdev->fw->file); 265 } 266 267 /* Initialize workarounds that depend on FW version */ 268 static void 269 ivpu_fw_init_wa(struct ivpu_device *vdev) 270 { 271 const struct vpu_firmware_header *fw_hdr = (const void *)vdev->fw->file->data; 272 273 if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, BOOT, 3, 17) || 274 (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_DISABLE)) 275 vdev->wa.disable_d0i3_msg = true; 276 277 /* Force enable the feature for testing purposes */ 278 if (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_ENABLE) 279 vdev->wa.disable_d0i3_msg = false; 280 281 IVPU_PRINT_WA(disable_d0i3_msg); 282 } 283 284 static int ivpu_fw_update_global_range(struct ivpu_device *vdev) 285 { 286 struct ivpu_fw_info *fw = vdev->fw; 287 u64 start = ALIGN(fw->runtime_addr + fw->runtime_size, FW_SHARED_MEM_ALIGNMENT); 288 u64 size = FW_SHARED_MEM_SIZE; 289 290 if (start + size > FW_GLOBAL_MEM_END) { 291 ivpu_err(vdev, "No space for shared region, start %lld, size %lld\n", start, size); 292 return -EINVAL; 293 } 294 295 ivpu_hw_range_init(&vdev->hw->ranges.global, start, size); 296 return 0; 297 } 298 299 static int ivpu_fw_mem_init(struct ivpu_device *vdev) 300 { 301 struct ivpu_fw_info *fw = vdev->fw; 302 struct ivpu_addr_range fw_range; 303 int log_verb_size; 304 int ret; 305 306 ret = ivpu_fw_update_global_range(vdev); 307 if (ret) 308 return ret; 309 310 fw_range.start = fw->runtime_addr; 311 fw_range.end = fw->runtime_addr + fw->runtime_size; 312 fw->mem = ivpu_bo_create(vdev, &vdev->gctx, &fw_range, fw->runtime_size, 313 DRM_IVPU_BO_WC | DRM_IVPU_BO_MAPPABLE); 314 if (!fw->mem) { 315 ivpu_err(vdev, "Failed to create firmware runtime memory buffer\n"); 316 return -ENOMEM; 317 } 318 319 ret = ivpu_mmu_context_set_pages_ro(vdev, &vdev->gctx, fw->read_only_addr, 320 fw->read_only_size); 321 if (ret) { 322 ivpu_err(vdev, "Failed to set firmware image read-only\n"); 323 goto err_free_fw_mem; 324 } 325 326 fw->mem_log_crit = ivpu_bo_create_global(vdev, IVPU_FW_CRITICAL_BUFFER_SIZE, 327 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE); 328 if (!fw->mem_log_crit) { 329 ivpu_err(vdev, "Failed to create critical log buffer\n"); 330 ret = -ENOMEM; 331 goto err_free_fw_mem; 332 } 333 334 if (ivpu_fw_log_level <= IVPU_FW_LOG_INFO) 335 log_verb_size = IVPU_FW_VERBOSE_BUFFER_LARGE_SIZE; 336 else 337 log_verb_size = IVPU_FW_VERBOSE_BUFFER_SMALL_SIZE; 338 339 fw->mem_log_verb = ivpu_bo_create_global(vdev, log_verb_size, 340 DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE); 341 if (!fw->mem_log_verb) { 342 ivpu_err(vdev, "Failed to create verbose log buffer\n"); 343 ret = -ENOMEM; 344 goto err_free_log_crit; 345 } 346 347 if (fw->shave_nn_size) { 348 fw->mem_shave_nn = ivpu_bo_create(vdev, &vdev->gctx, &vdev->hw->ranges.shave, 349 fw->shave_nn_size, DRM_IVPU_BO_WC); 350 if (!fw->mem_shave_nn) { 351 ivpu_err(vdev, "Failed to create shavenn buffer\n"); 352 ret = -ENOMEM; 353 goto err_free_log_verb; 354 } 355 } 356 357 return 0; 358 359 err_free_log_verb: 360 ivpu_bo_free(fw->mem_log_verb); 361 err_free_log_crit: 362 ivpu_bo_free(fw->mem_log_crit); 363 err_free_fw_mem: 364 ivpu_bo_free(fw->mem); 365 return ret; 366 } 367 368 static void ivpu_fw_mem_fini(struct ivpu_device *vdev) 369 { 370 struct ivpu_fw_info *fw = vdev->fw; 371 372 if (fw->mem_shave_nn) { 373 ivpu_bo_free(fw->mem_shave_nn); 374 fw->mem_shave_nn = NULL; 375 } 376 377 ivpu_bo_free(fw->mem_log_verb); 378 ivpu_bo_free(fw->mem_log_crit); 379 ivpu_bo_free(fw->mem); 380 381 fw->mem_log_verb = NULL; 382 fw->mem_log_crit = NULL; 383 fw->mem = NULL; 384 } 385 386 int ivpu_fw_init(struct ivpu_device *vdev) 387 { 388 int ret; 389 390 ret = ivpu_fw_request(vdev); 391 if (ret) 392 return ret; 393 394 ret = ivpu_fw_parse(vdev); 395 if (ret) 396 goto err_fw_release; 397 398 ivpu_fw_init_wa(vdev); 399 400 ret = ivpu_fw_mem_init(vdev); 401 if (ret) 402 goto err_fw_release; 403 404 ivpu_fw_load(vdev); 405 406 return 0; 407 408 err_fw_release: 409 ivpu_fw_release(vdev); 410 return ret; 411 } 412 413 void ivpu_fw_fini(struct ivpu_device *vdev) 414 { 415 ivpu_fw_mem_fini(vdev); 416 ivpu_fw_release(vdev); 417 } 418 419 void ivpu_fw_load(struct ivpu_device *vdev) 420 { 421 struct ivpu_fw_info *fw = vdev->fw; 422 u64 image_end_offset = fw->image_load_offset + fw->image_size; 423 424 memset(ivpu_bo_vaddr(fw->mem), 0, fw->image_load_offset); 425 memcpy(ivpu_bo_vaddr(fw->mem) + fw->image_load_offset, 426 fw->file->data + FW_FILE_IMAGE_OFFSET, fw->image_size); 427 428 if (IVPU_WA(clear_runtime_mem)) { 429 u8 *start = ivpu_bo_vaddr(fw->mem) + image_end_offset; 430 u64 size = ivpu_bo_size(fw->mem) - image_end_offset; 431 432 memset(start, 0, size); 433 } 434 435 wmb(); /* Flush WC buffers after writing fw->mem */ 436 } 437 438 static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 439 { 440 ivpu_dbg(vdev, FW_BOOT, "boot_params.magic = 0x%x\n", 441 boot_params->magic); 442 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_id = 0x%x\n", 443 boot_params->vpu_id); 444 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_count = 0x%x\n", 445 boot_params->vpu_count); 446 ivpu_dbg(vdev, FW_BOOT, "boot_params.frequency = %u\n", 447 boot_params->frequency); 448 ivpu_dbg(vdev, FW_BOOT, "boot_params.perf_clk_frequency = %u\n", 449 boot_params->perf_clk_frequency); 450 451 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_start = 0x%llx\n", 452 boot_params->ipc_header_area_start); 453 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_header_area_size = 0x%x\n", 454 boot_params->ipc_header_area_size); 455 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_base = 0x%llx\n", 456 boot_params->shared_region_base); 457 ivpu_dbg(vdev, FW_BOOT, "boot_params.shared_region_size = 0x%x\n", 458 boot_params->shared_region_size); 459 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_start = 0x%llx\n", 460 boot_params->ipc_payload_area_start); 461 ivpu_dbg(vdev, FW_BOOT, "boot_params.ipc_payload_area_size = 0x%x\n", 462 boot_params->ipc_payload_area_size); 463 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_base = 0x%llx\n", 464 boot_params->global_aliased_pio_base); 465 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_aliased_pio_size = 0x%x\n", 466 boot_params->global_aliased_pio_size); 467 468 ivpu_dbg(vdev, FW_BOOT, "boot_params.autoconfig = 0x%x\n", 469 boot_params->autoconfig); 470 471 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 0x%x\n", 472 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use); 473 ivpu_dbg(vdev, FW_BOOT, "boot_params.cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 0x%x\n", 474 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg); 475 476 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_base = 0x%llx\n", 477 boot_params->global_memory_allocator_base); 478 ivpu_dbg(vdev, FW_BOOT, "boot_params.global_memory_allocator_size = 0x%x\n", 479 boot_params->global_memory_allocator_size); 480 481 ivpu_dbg(vdev, FW_BOOT, "boot_params.shave_nn_fw_base = 0x%llx\n", 482 boot_params->shave_nn_fw_base); 483 484 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_mss = 0x%x\n", 485 boot_params->watchdog_irq_mss); 486 ivpu_dbg(vdev, FW_BOOT, "boot_params.watchdog_irq_nce = 0x%x\n", 487 boot_params->watchdog_irq_nce); 488 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_to_vpu_irq = 0x%x\n", 489 boot_params->host_to_vpu_irq); 490 ivpu_dbg(vdev, FW_BOOT, "boot_params.job_done_irq = 0x%x\n", 491 boot_params->job_done_irq); 492 493 ivpu_dbg(vdev, FW_BOOT, "boot_params.host_version_id = 0x%x\n", 494 boot_params->host_version_id); 495 ivpu_dbg(vdev, FW_BOOT, "boot_params.si_stepping = 0x%x\n", 496 boot_params->si_stepping); 497 ivpu_dbg(vdev, FW_BOOT, "boot_params.device_id = 0x%llx\n", 498 boot_params->device_id); 499 ivpu_dbg(vdev, FW_BOOT, "boot_params.feature_exclusion = 0x%llx\n", 500 boot_params->feature_exclusion); 501 ivpu_dbg(vdev, FW_BOOT, "boot_params.sku = 0x%llx\n", 502 boot_params->sku); 503 ivpu_dbg(vdev, FW_BOOT, "boot_params.min_freq_pll_ratio = 0x%x\n", 504 boot_params->min_freq_pll_ratio); 505 ivpu_dbg(vdev, FW_BOOT, "boot_params.pn_freq_pll_ratio = 0x%x\n", 506 boot_params->pn_freq_pll_ratio); 507 ivpu_dbg(vdev, FW_BOOT, "boot_params.max_freq_pll_ratio = 0x%x\n", 508 boot_params->max_freq_pll_ratio); 509 ivpu_dbg(vdev, FW_BOOT, "boot_params.default_trace_level = 0x%x\n", 510 boot_params->default_trace_level); 511 ivpu_dbg(vdev, FW_BOOT, "boot_params.tracing_buff_message_format_mask = 0x%llx\n", 512 boot_params->tracing_buff_message_format_mask); 513 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_destination_mask = 0x%x\n", 514 boot_params->trace_destination_mask); 515 ivpu_dbg(vdev, FW_BOOT, "boot_params.trace_hw_component_mask = 0x%llx\n", 516 boot_params->trace_hw_component_mask); 517 ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n", 518 boot_params->boot_type); 519 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_base = 0x%llx\n", 520 boot_params->punit_telemetry_sram_base); 521 ivpu_dbg(vdev, FW_BOOT, "boot_params.punit_telemetry_sram_size = 0x%llx\n", 522 boot_params->punit_telemetry_sram_size); 523 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_telemetry_enable = 0x%x\n", 524 boot_params->vpu_telemetry_enable); 525 ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_scheduling_mode = 0x%x\n", 526 boot_params->vpu_scheduling_mode); 527 ivpu_dbg(vdev, FW_BOOT, "boot_params.dvfs_mode = %u\n", 528 boot_params->dvfs_mode); 529 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_delayed_entry = %d\n", 530 boot_params->d0i3_delayed_entry); 531 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n", 532 boot_params->d0i3_residency_time_us); 533 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n", 534 boot_params->d0i3_entry_vpu_ts); 535 ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n", 536 boot_params->system_time_us); 537 ivpu_dbg(vdev, FW_BOOT, "boot_params.power_profile = %u\n", 538 boot_params->power_profile); 539 } 540 541 void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) 542 { 543 struct ivpu_bo *ipc_mem_rx = vdev->ipc->mem_rx; 544 545 /* In case of warm boot only update variable params */ 546 if (!ivpu_fw_is_cold_boot(vdev)) { 547 boot_params->d0i3_residency_time_us = 548 ktime_us_delta(ktime_get_boottime(), vdev->hw->d0i3_entry_host_ts); 549 boot_params->d0i3_entry_vpu_ts = vdev->hw->d0i3_entry_vpu_ts; 550 boot_params->system_time_us = ktime_to_us(ktime_get_real()); 551 552 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_residency_time_us = %lld\n", 553 boot_params->d0i3_residency_time_us); 554 ivpu_dbg(vdev, FW_BOOT, "boot_params.d0i3_entry_vpu_ts = %llu\n", 555 boot_params->d0i3_entry_vpu_ts); 556 ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n", 557 boot_params->system_time_us); 558 559 boot_params->save_restore_ret_address = 0; 560 vdev->pm->is_warmboot = true; 561 wmb(); /* Flush WC buffers after writing save_restore_ret_address */ 562 return; 563 } 564 565 vdev->pm->is_warmboot = false; 566 567 boot_params->magic = VPU_BOOT_PARAMS_MAGIC; 568 boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number; 569 boot_params->frequency = ivpu_hw_pll_freq_get(vdev); 570 571 /* 572 * This param is a debug firmware feature. It switches default clock 573 * to higher resolution one for fine-grained and more accurate firmware 574 * task profiling. 575 */ 576 boot_params->perf_clk_frequency = ivpu_hw_profiling_freq_get(vdev); 577 578 /* 579 * Uncached region of VPU address space, covers IPC buffers, job queues 580 * and log buffers, programmable to L2$ Uncached by VPU MTRR 581 */ 582 boot_params->shared_region_base = vdev->hw->ranges.global.start; 583 boot_params->shared_region_size = vdev->hw->ranges.global.end - 584 vdev->hw->ranges.global.start; 585 586 boot_params->ipc_header_area_start = ipc_mem_rx->vpu_addr; 587 boot_params->ipc_header_area_size = ivpu_bo_size(ipc_mem_rx) / 2; 588 589 boot_params->ipc_payload_area_start = ipc_mem_rx->vpu_addr + ivpu_bo_size(ipc_mem_rx) / 2; 590 boot_params->ipc_payload_area_size = ivpu_bo_size(ipc_mem_rx) / 2; 591 592 if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { 593 boot_params->global_aliased_pio_base = vdev->hw->ranges.user.start; 594 boot_params->global_aliased_pio_size = ivpu_hw_range_size(&vdev->hw->ranges.user); 595 } 596 597 /* Allow configuration for L2C_PAGE_TABLE with boot param value */ 598 boot_params->autoconfig = 1; 599 600 /* Enable L2 cache for first 2GB of high memory */ 601 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].use = 1; 602 boot_params->cache_defaults[VPU_BOOT_L2_CACHE_CFG_NN].cfg = 603 ADDR_TO_L2_CACHE_CFG(vdev->hw->ranges.shave.start); 604 605 if (vdev->fw->mem_shave_nn) 606 boot_params->shave_nn_fw_base = vdev->fw->mem_shave_nn->vpu_addr; 607 608 boot_params->watchdog_irq_mss = WATCHDOG_MSS_REDIRECT; 609 boot_params->watchdog_irq_nce = WATCHDOG_NCE_REDIRECT; 610 boot_params->si_stepping = ivpu_revision(vdev); 611 boot_params->device_id = ivpu_device_id(vdev); 612 boot_params->feature_exclusion = vdev->hw->tile_fuse; 613 boot_params->sku = vdev->hw->sku; 614 615 boot_params->min_freq_pll_ratio = vdev->hw->pll.min_ratio; 616 boot_params->pn_freq_pll_ratio = vdev->hw->pll.pn_ratio; 617 boot_params->max_freq_pll_ratio = vdev->hw->pll.max_ratio; 618 619 boot_params->default_trace_level = vdev->fw->trace_level; 620 boot_params->tracing_buff_message_format_mask = BIT(VPU_TRACING_FORMAT_STRING); 621 boot_params->trace_destination_mask = vdev->fw->trace_destination_mask; 622 boot_params->trace_hw_component_mask = vdev->fw->trace_hw_component_mask; 623 boot_params->crit_tracing_buff_addr = vdev->fw->mem_log_crit->vpu_addr; 624 boot_params->crit_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_crit); 625 boot_params->verbose_tracing_buff_addr = vdev->fw->mem_log_verb->vpu_addr; 626 boot_params->verbose_tracing_buff_size = ivpu_bo_size(vdev->fw->mem_log_verb); 627 628 boot_params->punit_telemetry_sram_base = ivpu_hw_telemetry_offset_get(vdev); 629 boot_params->punit_telemetry_sram_size = ivpu_hw_telemetry_size_get(vdev); 630 boot_params->vpu_telemetry_enable = ivpu_hw_telemetry_enable_get(vdev); 631 boot_params->vpu_scheduling_mode = vdev->fw->sched_mode; 632 if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) 633 boot_params->vpu_focus_present_timer_ms = IVPU_FOCUS_PRESENT_TIMER_MS; 634 boot_params->dvfs_mode = vdev->fw->dvfs_mode; 635 if (!IVPU_WA(disable_d0i3_msg)) 636 boot_params->d0i3_delayed_entry = 1; 637 boot_params->d0i3_residency_time_us = 0; 638 boot_params->d0i3_entry_vpu_ts = 0; 639 if (IVPU_WA(disable_d0i2)) 640 boot_params->power_profile = 1; 641 642 boot_params->system_time_us = ktime_to_us(ktime_get_real()); 643 wmb(); /* Flush WC buffers after writing bootparams */ 644 645 ivpu_fw_boot_params_print(vdev, boot_params); 646 } 647