1*8ba2876dSOmer Shpigelman /* SPDX-License-Identifier: GPL-2.0 2*8ba2876dSOmer Shpigelman * 3*8ba2876dSOmer Shpigelman * Copyright 2016-2018 HabanaLabs, Ltd. 4*8ba2876dSOmer Shpigelman * All Rights Reserved. 5*8ba2876dSOmer Shpigelman * 6*8ba2876dSOmer Shpigelman */ 7*8ba2876dSOmer Shpigelman 8*8ba2876dSOmer Shpigelman /************************************ 9*8ba2876dSOmer Shpigelman ** This is an auto-generated file ** 10*8ba2876dSOmer Shpigelman ** DO NOT EDIT BELOW ** 11*8ba2876dSOmer Shpigelman ************************************/ 12*8ba2876dSOmer Shpigelman 13*8ba2876dSOmer Shpigelman #ifndef ASIC_REG_PCIE_WRAP_REGS_H_ 14*8ba2876dSOmer Shpigelman #define ASIC_REG_PCIE_WRAP_REGS_H_ 15*8ba2876dSOmer Shpigelman 16*8ba2876dSOmer Shpigelman /* 17*8ba2876dSOmer Shpigelman ***************************************** 18*8ba2876dSOmer Shpigelman * PCIE_WRAP (Prototype: PCIE_WRAP) 19*8ba2876dSOmer Shpigelman ***************************************** 20*8ba2876dSOmer Shpigelman */ 21*8ba2876dSOmer Shpigelman 22*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_PHY_RST_N 0xC01300 23*8ba2876dSOmer Shpigelman 24*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_OUTSTAND_TRANS 0xC01400 25*8ba2876dSOmer Shpigelman 26*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_MASK_REQ 0xC01404 27*8ba2876dSOmer Shpigelman 28*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWADDR_L 0xC01500 29*8ba2876dSOmer Shpigelman 30*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWADDR_H 0xC01504 31*8ba2876dSOmer Shpigelman 32*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWLEN 0xC01508 33*8ba2876dSOmer Shpigelman 34*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWSIZE 0xC0150C 35*8ba2876dSOmer Shpigelman 36*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWBURST 0xC01510 37*8ba2876dSOmer Shpigelman 38*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWLOCK 0xC01514 39*8ba2876dSOmer Shpigelman 40*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWCACHE 0xC01518 41*8ba2876dSOmer Shpigelman 42*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWPROT 0xC0151C 43*8ba2876dSOmer Shpigelman 44*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWVALID 0xC01520 45*8ba2876dSOmer Shpigelman 46*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_WDATA_0 0xC01524 47*8ba2876dSOmer Shpigelman 48*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_WDATA_1 0xC01528 49*8ba2876dSOmer Shpigelman 50*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_WDATA_2 0xC0152C 51*8ba2876dSOmer Shpigelman 52*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_WDATA_3 0xC01530 53*8ba2876dSOmer Shpigelman 54*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_WSTRB 0xC01544 55*8ba2876dSOmer Shpigelman 56*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_WLAST 0xC01548 57*8ba2876dSOmer Shpigelman 58*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_WVALID 0xC0154C 59*8ba2876dSOmer Shpigelman 60*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_BRESP 0xC01550 61*8ba2876dSOmer Shpigelman 62*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_BVALID 0xC01554 63*8ba2876dSOmer Shpigelman 64*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_ARADDR_0 0xC01558 65*8ba2876dSOmer Shpigelman 66*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_ARADDR_1 0xC0155C 67*8ba2876dSOmer Shpigelman 68*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_ARLEN 0xC01560 69*8ba2876dSOmer Shpigelman 70*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_ARSIZE 0xC01564 71*8ba2876dSOmer Shpigelman 72*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_ARBURST 0xC01568 73*8ba2876dSOmer Shpigelman 74*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_ARLOCK 0xC0156C 75*8ba2876dSOmer Shpigelman 76*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_ARCACHE 0xC01570 77*8ba2876dSOmer Shpigelman 78*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_ARPROT 0xC01574 79*8ba2876dSOmer Shpigelman 80*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_ARVALID 0xC01578 81*8ba2876dSOmer Shpigelman 82*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_RDATA_0 0xC0157C 83*8ba2876dSOmer Shpigelman 84*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_RDATA_1 0xC01580 85*8ba2876dSOmer Shpigelman 86*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_RDATA_2 0xC01584 87*8ba2876dSOmer Shpigelman 88*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_RDATA_3 0xC01588 89*8ba2876dSOmer Shpigelman 90*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_RLAST 0xC0159C 91*8ba2876dSOmer Shpigelman 92*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_RRESP 0xC015A0 93*8ba2876dSOmer Shpigelman 94*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_RVALID 0xC015A4 95*8ba2876dSOmer Shpigelman 96*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWMISC_INFO 0xC015A8 97*8ba2876dSOmer Shpigelman 98*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWMISC_INFO_HDR_34DW_0 0xC015AC 99*8ba2876dSOmer Shpigelman 100*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWMISC_INFO_HDR_34DW_1 0xC015B0 101*8ba2876dSOmer Shpigelman 102*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWMISC_INFO_P_TAG 0xC015B4 103*8ba2876dSOmer Shpigelman 104*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWMISC_INFO_ATU_BYPAS 0xC015B8 105*8ba2876dSOmer Shpigelman 106*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWMISC_INFO_FUNC_NUM 0xC015BC 107*8ba2876dSOmer Shpigelman 108*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWMISC_INFO_VFUNC_ACT 0xC015C0 109*8ba2876dSOmer Shpigelman 110*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWMISC_INFO_VFUNC_NUM 0xC015C4 111*8ba2876dSOmer Shpigelman 112*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_AWMISC_INFO_TLPPRFX 0xC015C8 113*8ba2876dSOmer Shpigelman 114*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_ARMISC_INFO 0xC015CC 115*8ba2876dSOmer Shpigelman 116*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_ARMISC_INFO_TLPPRFX 0xC015D0 117*8ba2876dSOmer Shpigelman 118*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_ARMISC_INFO_ATU_BYP 0xC015D4 119*8ba2876dSOmer Shpigelman 120*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_ARMISC_INFO_FUNC_NUM 0xC015D8 121*8ba2876dSOmer Shpigelman 122*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_ARMISC_INFO_VFUNC_ACT 0xC015DC 123*8ba2876dSOmer Shpigelman 124*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_IND_ARMISC_INFO_VFUNC_NUM 0xC015E0 125*8ba2876dSOmer Shpigelman 126*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SLV_AWMISC_INFO 0xC01800 127*8ba2876dSOmer Shpigelman 128*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SLV_AWMISC_INFO_HDR_34DW_0 0xC01804 129*8ba2876dSOmer Shpigelman 130*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SLV_AWMISC_INFO_HDR_34DW_1 0xC01808 131*8ba2876dSOmer Shpigelman 132*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SLV_AWMISC_INFO_P_TAG 0xC0180C 133*8ba2876dSOmer Shpigelman 134*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SLV_AWMISC_INFO_ATU_BYPAS 0xC01810 135*8ba2876dSOmer Shpigelman 136*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SLV_AWMISC_INFO_FUNC_NUM 0xC01814 137*8ba2876dSOmer Shpigelman 138*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SLV_AWMISC_INFO_VFUNC_ACT 0xC01818 139*8ba2876dSOmer Shpigelman 140*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SLV_AWMISC_INFO_VFUNC_NUM 0xC0181C 141*8ba2876dSOmer Shpigelman 142*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SLV_AWMISC_INFO_TLPPRFX 0xC01820 143*8ba2876dSOmer Shpigelman 144*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SLV_ARMISC_INFO 0xC01824 145*8ba2876dSOmer Shpigelman 146*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SLV_ARMISC_INFO_TLPPRFX 0xC01828 147*8ba2876dSOmer Shpigelman 148*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SLV_ARMISC_INFO_ATU_BYP 0xC0182C 149*8ba2876dSOmer Shpigelman 150*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SLV_ARMISC_INFO_FUNC_NUM 0xC01830 151*8ba2876dSOmer Shpigelman 152*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SLV_ARMISC_INFO_VFUNC_ACT 0xC01834 153*8ba2876dSOmer Shpigelman 154*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SLV_ARMISC_INFO_VFUNC_NUM 0xC01838 155*8ba2876dSOmer Shpigelman 156*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_MAX_QID 0xC01900 157*8ba2876dSOmer Shpigelman 158*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_BASE_ADDR_L_0 0xC01910 159*8ba2876dSOmer Shpigelman 160*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_BASE_ADDR_L_1 0xC01914 161*8ba2876dSOmer Shpigelman 162*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_BASE_ADDR_L_2 0xC01918 163*8ba2876dSOmer Shpigelman 164*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_BASE_ADDR_L_3 0xC0191C 165*8ba2876dSOmer Shpigelman 166*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_BASE_ADDR_H_0 0xC01920 167*8ba2876dSOmer Shpigelman 168*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_BASE_ADDR_H_1 0xC01924 169*8ba2876dSOmer Shpigelman 170*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_BASE_ADDR_H_2 0xC01928 171*8ba2876dSOmer Shpigelman 172*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_BASE_ADDR_H_3 0xC0192C 173*8ba2876dSOmer Shpigelman 174*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_MASK 0xC01940 175*8ba2876dSOmer Shpigelman 176*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SQ_BASE_ADDR_H 0xC01A00 177*8ba2876dSOmer Shpigelman 178*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SQ_BASE_ADDR_L 0xC01A04 179*8ba2876dSOmer Shpigelman 180*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SQ_STRIDE_ACCRESS 0xC01A08 181*8ba2876dSOmer Shpigelman 182*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SQ_POP_CMD 0xC01A10 183*8ba2876dSOmer Shpigelman 184*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SQ_POP_DATA 0xC01A14 185*8ba2876dSOmer Shpigelman 186*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_INTR_0 0xC01A20 187*8ba2876dSOmer Shpigelman 188*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_INTR_1 0xC01A24 189*8ba2876dSOmer Shpigelman 190*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_INTR_2 0xC01A28 191*8ba2876dSOmer Shpigelman 192*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_INTR_3 0xC01A2C 193*8ba2876dSOmer Shpigelman 194*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_INTR_4 0xC01A30 195*8ba2876dSOmer Shpigelman 196*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_INTR_5 0xC01A34 197*8ba2876dSOmer Shpigelman 198*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_INTR_6 0xC01A38 199*8ba2876dSOmer Shpigelman 200*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_INTR_7 0xC01A3C 201*8ba2876dSOmer Shpigelman 202*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_MMU_BYPASS_DMA 0xC01A80 203*8ba2876dSOmer Shpigelman 204*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_MMU_BYPASS_NON_DMA 0xC01A84 205*8ba2876dSOmer Shpigelman 206*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_ASID_NON_DMA 0xC01A90 207*8ba2876dSOmer Shpigelman 208*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_ASID_DMA_0 0xC01AA0 209*8ba2876dSOmer Shpigelman 210*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_ASID_DMA_1 0xC01AA4 211*8ba2876dSOmer Shpigelman 212*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_ASID_DMA_2 0xC01AA8 213*8ba2876dSOmer Shpigelman 214*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_ASID_DMA_3 0xC01AAC 215*8ba2876dSOmer Shpigelman 216*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_ASID_DMA_4 0xC01AB0 217*8ba2876dSOmer Shpigelman 218*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_ASID_DMA_5 0xC01AB4 219*8ba2876dSOmer Shpigelman 220*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_ASID_DMA_6 0xC01AB8 221*8ba2876dSOmer Shpigelman 222*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_ASID_DMA_7 0xC01ABC 223*8ba2876dSOmer Shpigelman 224*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_CPU_HOT_RST 0xC01AE0 225*8ba2876dSOmer Shpigelman 226*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_AXI_PROT_OVR 0xC01AE4 227*8ba2876dSOmer Shpigelman 228*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_CACHE_OVR 0xC01B00 229*8ba2876dSOmer Shpigelman 230*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_LOCK_OVR 0xC01B04 231*8ba2876dSOmer Shpigelman 232*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_PROT_OVR 0xC01B08 233*8ba2876dSOmer Shpigelman 234*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_ARUSER_OVR 0xC01B0C 235*8ba2876dSOmer Shpigelman 236*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_AWUSER_OVR 0xC01B10 237*8ba2876dSOmer Shpigelman 238*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_ARUSER_OVR_EN 0xC01B14 239*8ba2876dSOmer Shpigelman 240*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_AWUSER_OVR_EN 0xC01B18 241*8ba2876dSOmer Shpigelman 242*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_MAX_OUTSTAND 0xC01B20 243*8ba2876dSOmer Shpigelman 244*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_MST_IN 0xC01B24 245*8ba2876dSOmer Shpigelman 246*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_RSP_OK 0xC01B28 247*8ba2876dSOmer Shpigelman 248*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_LBW_CACHE_OVR 0xC01B40 249*8ba2876dSOmer Shpigelman 250*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_LBW_LOCK_OVR 0xC01B44 251*8ba2876dSOmer Shpigelman 252*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_LBW_PROT_OVR 0xC01B48 253*8ba2876dSOmer Shpigelman 254*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_LBW_ARUSER_OVR 0xC01B4C 255*8ba2876dSOmer Shpigelman 256*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_LBW_AWUSER_OVR 0xC01B50 257*8ba2876dSOmer Shpigelman 258*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_LBW_ARUSER_OVR_EN 0xC01B58 259*8ba2876dSOmer Shpigelman 260*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_LBW_AWUSER_OVR_EN 0xC01B5C 261*8ba2876dSOmer Shpigelman 262*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_LBW_MAX_OUTSTAND 0xC01B60 263*8ba2876dSOmer Shpigelman 264*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_LBW_MST_IN 0xC01B64 265*8ba2876dSOmer Shpigelman 266*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_LBW_RSP_OK 0xC01B68 267*8ba2876dSOmer Shpigelman 268*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_QUEUE_INIT 0xC01C00 269*8ba2876dSOmer Shpigelman 270*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_AXI_SPLIT_INTR_0 0xC01C10 271*8ba2876dSOmer Shpigelman 272*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_AXI_SPLIT_INTR_1 0xC01C14 273*8ba2876dSOmer Shpigelman 274*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_AWUSER 0xC01D00 275*8ba2876dSOmer Shpigelman 276*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_ARUSER 0xC01D04 277*8ba2876dSOmer Shpigelman 278*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_PCIE_AWUSER 0xC01D08 279*8ba2876dSOmer Shpigelman 280*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_PCIE_ARUSER 0xC01D0C 281*8ba2876dSOmer Shpigelman 282*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_PSOC_AWUSER 0xC01D10 283*8ba2876dSOmer Shpigelman 284*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_PSOC_ARUSER 0xC01D14 285*8ba2876dSOmer Shpigelman 286*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SCH_Q_AWUSER 0xC01D18 287*8ba2876dSOmer Shpigelman 288*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SCH_Q_ARUSER 0xC01D1C 289*8ba2876dSOmer Shpigelman 290*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_PSOC2PCI_AWUSER 0xC01D40 291*8ba2876dSOmer Shpigelman 292*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_PSOC2PCI_ARUSER 0xC01D44 293*8ba2876dSOmer Shpigelman 294*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DRAIN_TIMEOUT 0xC01D50 295*8ba2876dSOmer Shpigelman 296*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DRAIN_CFG 0xC01D54 297*8ba2876dSOmer Shpigelman 298*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_DB_AXI_ERR 0xC01DE0 299*8ba2876dSOmer Shpigelman 300*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_SPMU_INTR 0xC01DE4 301*8ba2876dSOmer Shpigelman 302*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_AXI_INTR 0xC01DE8 303*8ba2876dSOmer Shpigelman 304*8ba2876dSOmer Shpigelman #define mmPCIE_WRAP_E2E_CTRL 0xC01DF0 305*8ba2876dSOmer Shpigelman 306*8ba2876dSOmer Shpigelman #endif /* ASIC_REG_PCIE_WRAP_REGS_H_ */ 307