1*2aad2bf8SOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*2aad2bf8SOded Gabbay * 3*2aad2bf8SOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*2aad2bf8SOded Gabbay * All Rights Reserved. 5*2aad2bf8SOded Gabbay * 6*2aad2bf8SOded Gabbay */ 7*2aad2bf8SOded Gabbay 8*2aad2bf8SOded Gabbay /************************************ 9*2aad2bf8SOded Gabbay ** This is an auto-generated file ** 10*2aad2bf8SOded Gabbay ** DO NOT EDIT BELOW ** 11*2aad2bf8SOded Gabbay ************************************/ 12*2aad2bf8SOded Gabbay 13*2aad2bf8SOded Gabbay #ifndef ASIC_REG_MMU_UP_REGS_H_ 14*2aad2bf8SOded Gabbay #define ASIC_REG_MMU_UP_REGS_H_ 15*2aad2bf8SOded Gabbay 16*2aad2bf8SOded Gabbay /* 17*2aad2bf8SOded Gabbay ***************************************** 18*2aad2bf8SOded Gabbay * MMU_UP (Prototype: MMU) 19*2aad2bf8SOded Gabbay ***************************************** 20*2aad2bf8SOded Gabbay */ 21*2aad2bf8SOded Gabbay 22*2aad2bf8SOded Gabbay #define mmMMU_UP_MMU_ENABLE 0xC1100C 23*2aad2bf8SOded Gabbay 24*2aad2bf8SOded Gabbay #define mmMMU_UP_FORCE_ORDERING 0xC11010 25*2aad2bf8SOded Gabbay 26*2aad2bf8SOded Gabbay #define mmMMU_UP_FEATURE_ENABLE 0xC11014 27*2aad2bf8SOded Gabbay 28*2aad2bf8SOded Gabbay #define mmMMU_UP_VA_ORDERING_MASK_31_7 0xC11018 29*2aad2bf8SOded Gabbay 30*2aad2bf8SOded Gabbay #define mmMMU_UP_VA_ORDERING_MASK_49_32 0xC1101C 31*2aad2bf8SOded Gabbay 32*2aad2bf8SOded Gabbay #define mmMMU_UP_LOG2_DDR_SIZE 0xC11020 33*2aad2bf8SOded Gabbay 34*2aad2bf8SOded Gabbay #define mmMMU_UP_SCRAMBLER 0xC11024 35*2aad2bf8SOded Gabbay 36*2aad2bf8SOded Gabbay #define mmMMU_UP_MEM_INIT_BUSY 0xC11028 37*2aad2bf8SOded Gabbay 38*2aad2bf8SOded Gabbay #define mmMMU_UP_SPI_MASK 0xC1102C 39*2aad2bf8SOded Gabbay 40*2aad2bf8SOded Gabbay #define mmMMU_UP_SPI_CAUSE 0xC11030 41*2aad2bf8SOded Gabbay 42*2aad2bf8SOded Gabbay #define mmMMU_UP_PAGE_ERROR_CAPTURE 0xC11034 43*2aad2bf8SOded Gabbay 44*2aad2bf8SOded Gabbay #define mmMMU_UP_PAGE_ERROR_CAPTURE_VA 0xC11038 45*2aad2bf8SOded Gabbay 46*2aad2bf8SOded Gabbay #define mmMMU_UP_ACCESS_ERROR_CAPTURE 0xC1103C 47*2aad2bf8SOded Gabbay 48*2aad2bf8SOded Gabbay #define mmMMU_UP_ACCESS_ERROR_CAPTURE_VA 0xC11040 49*2aad2bf8SOded Gabbay 50*2aad2bf8SOded Gabbay #define mmMMU_UP_SPI_INTERRUPT_CLR 0xC11044 51*2aad2bf8SOded Gabbay 52*2aad2bf8SOded Gabbay #define mmMMU_UP_SPI_INTERRUPT_MASK 0xC11048 53*2aad2bf8SOded Gabbay 54*2aad2bf8SOded Gabbay #define mmMMU_UP_DBG_MEM_WRAP_RM 0xC1104C 55*2aad2bf8SOded Gabbay 56*2aad2bf8SOded Gabbay #define mmMMU_UP_SPI_CAUSE_CLR 0xC11050 57*2aad2bf8SOded Gabbay 58*2aad2bf8SOded Gabbay #define mmMMU_UP_SLICE_CREDIT 0xC11054 59*2aad2bf8SOded Gabbay 60*2aad2bf8SOded Gabbay #define mmMMU_UP_PIPE_CREDIT 0xC11058 61*2aad2bf8SOded Gabbay 62*2aad2bf8SOded Gabbay #define mmMMU_UP_RAZWI_WRITE_VLD 0xC1105C 63*2aad2bf8SOded Gabbay 64*2aad2bf8SOded Gabbay #define mmMMU_UP_RAZWI_WRITE_ID 0xC11060 65*2aad2bf8SOded Gabbay 66*2aad2bf8SOded Gabbay #define mmMMU_UP_RAZWI_READ_VLD 0xC11064 67*2aad2bf8SOded Gabbay 68*2aad2bf8SOded Gabbay #define mmMMU_UP_RAZWI_READ_ID 0xC11068 69*2aad2bf8SOded Gabbay 70*2aad2bf8SOded Gabbay #define mmMMU_UP_MMU_BYPASS 0xC1106C 71*2aad2bf8SOded Gabbay 72*2aad2bf8SOded Gabbay #endif /* ASIC_REG_MMU_UP_REGS_H_ */ 73