1273b5176SLizhi Hou // SPDX-License-Identifier: GPL-2.0 2273b5176SLizhi Hou /* 3273b5176SLizhi Hou * Copyright (C) 2024, Advanced Micro Devices, Inc. 4273b5176SLizhi Hou */ 5273b5176SLizhi Hou 6273b5176SLizhi Hou #include <drm/amdxdna_accel.h> 7273b5176SLizhi Hou #include <drm/drm_device.h> 8273b5176SLizhi Hou #include <drm/gpu_scheduler.h> 9273b5176SLizhi Hou #include <linux/sizes.h> 10273b5176SLizhi Hou 11273b5176SLizhi Hou #include "aie2_pci.h" 12273b5176SLizhi Hou #include "amdxdna_mailbox.h" 13273b5176SLizhi Hou #include "amdxdna_pci_drv.h" 14273b5176SLizhi Hou 15273b5176SLizhi Hou /* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */ 16273b5176SLizhi Hou #define MPNPU_PUB_SEC_INTR 0x3010060 17273b5176SLizhi Hou #define MPNPU_PUB_PWRMGMT_INTR 0x3010064 18273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH0 0x301006C 19273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH1 0x3010070 20273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH2 0x3010074 21273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH3 0x3010078 22273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH4 0x301007C 23273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH5 0x3010080 24273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH6 0x3010084 25273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH7 0x3010088 26273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH8 0x301008C 27273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH9 0x3010090 28273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH10 0x3010094 29273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH11 0x3010098 30273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH12 0x301009C 31273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH13 0x30100A0 32273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH14 0x30100A4 33273b5176SLizhi Hou #define MPNPU_PUB_SCRATCH15 0x30100A8 34273b5176SLizhi Hou #define MP0_C2PMSG_73 0x3810A24 35273b5176SLizhi Hou #define MP0_C2PMSG_123 0x3810AEC 36273b5176SLizhi Hou 37273b5176SLizhi Hou #define MP1_C2PMSG_0 0x3B10900 38273b5176SLizhi Hou #define MP1_C2PMSG_60 0x3B109F0 39273b5176SLizhi Hou #define MP1_C2PMSG_61 0x3B109F4 40273b5176SLizhi Hou 41273b5176SLizhi Hou #define MPNPU_SRAM_X2I_MAILBOX_0 0x3600000 42273b5176SLizhi Hou #define MPNPU_SRAM_X2I_MAILBOX_15 0x361E000 43273b5176SLizhi Hou #define MPNPU_SRAM_X2I_MAILBOX_31 0x363E000 44273b5176SLizhi Hou #define MPNPU_SRAM_I2X_MAILBOX_31 0x363F000 45273b5176SLizhi Hou 46273b5176SLizhi Hou #define MMNPU_APERTURE0_BASE 0x3000000 47273b5176SLizhi Hou #define MMNPU_APERTURE1_BASE 0x3600000 48273b5176SLizhi Hou #define MMNPU_APERTURE3_BASE 0x3810000 49273b5176SLizhi Hou #define MMNPU_APERTURE4_BASE 0x3B10000 50273b5176SLizhi Hou 51273b5176SLizhi Hou /* PCIe BAR Index for NPU6 */ 52273b5176SLizhi Hou #define NPU6_REG_BAR_INDEX 0 53273b5176SLizhi Hou #define NPU6_MBOX_BAR_INDEX 0 54273b5176SLizhi Hou #define NPU6_PSP_BAR_INDEX 4 55273b5176SLizhi Hou #define NPU6_SMU_BAR_INDEX 5 56273b5176SLizhi Hou #define NPU6_SRAM_BAR_INDEX 2 57273b5176SLizhi Hou /* Associated BARs and Apertures */ 58273b5176SLizhi Hou #define NPU6_REG_BAR_BASE MMNPU_APERTURE0_BASE 59273b5176SLizhi Hou #define NPU6_MBOX_BAR_BASE MMNPU_APERTURE0_BASE 60273b5176SLizhi Hou #define NPU6_PSP_BAR_BASE MMNPU_APERTURE3_BASE 61273b5176SLizhi Hou #define NPU6_SMU_BAR_BASE MMNPU_APERTURE4_BASE 62273b5176SLizhi Hou #define NPU6_SRAM_BAR_BASE MMNPU_APERTURE1_BASE 63273b5176SLizhi Hou 64*fee7aaeeSLizhi Hou static const struct amdxdna_dev_priv npu6_dev_priv = { 65273b5176SLizhi Hou .fw_path = "amdnpu/17f0_10/npu.sbin", 66273b5176SLizhi Hou .protocol_major = 0x6, 67273b5176SLizhi Hou .protocol_minor = 12, 68f4d7b8a6SLizhi Hou .rt_config = npu4_default_rt_cfg, 69f4d7b8a6SLizhi Hou .dpm_clk_tbl = npu4_dpm_clk_table, 70273b5176SLizhi Hou .col_align = COL_ALIGN_NATURE, 71273b5176SLizhi Hou .mbox_dev_addr = NPU6_MBOX_BAR_BASE, 72273b5176SLizhi Hou .mbox_size = 0, /* Use BAR size */ 73273b5176SLizhi Hou .sram_dev_addr = NPU6_SRAM_BAR_BASE, 74273b5176SLizhi Hou .sram_offs = { 75273b5176SLizhi Hou DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_0), 76273b5176SLizhi Hou DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU6_SRAM, MPNPU_SRAM_X2I_MAILBOX_15), 77273b5176SLizhi Hou }, 78273b5176SLizhi Hou .psp_regs_off = { 79273b5176SLizhi Hou DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU6_PSP, MP0_C2PMSG_123), 80273b5176SLizhi Hou DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU6_REG, MPNPU_PUB_SCRATCH3), 81273b5176SLizhi Hou DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU6_REG, MPNPU_PUB_SCRATCH4), 82273b5176SLizhi Hou DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU6_REG, MPNPU_PUB_SCRATCH9), 83273b5176SLizhi Hou DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU6_PSP, MP0_C2PMSG_73), 84273b5176SLizhi Hou DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU6_PSP, MP0_C2PMSG_123), 85273b5176SLizhi Hou DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU6_REG, MPNPU_PUB_SCRATCH3), 86273b5176SLizhi Hou }, 87273b5176SLizhi Hou .smu_regs_off = { 88273b5176SLizhi Hou DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU6_SMU, MP1_C2PMSG_0), 89273b5176SLizhi Hou DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU6_SMU, MP1_C2PMSG_60), 90273b5176SLizhi Hou DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU6_SMU, MMNPU_APERTURE4_BASE), 91273b5176SLizhi Hou DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU6_SMU, MP1_C2PMSG_61), 92273b5176SLizhi Hou DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU6_SMU, MP1_C2PMSG_60), 93273b5176SLizhi Hou }, 94f4d7b8a6SLizhi Hou .hw_ops = { 95f4d7b8a6SLizhi Hou .set_dpm = npu4_set_dpm, 96f4d7b8a6SLizhi Hou }, 97f4d7b8a6SLizhi Hou 98273b5176SLizhi Hou }; 99273b5176SLizhi Hou 100273b5176SLizhi Hou const struct amdxdna_dev_info dev_npu6_info = { 101273b5176SLizhi Hou .reg_bar = NPU6_REG_BAR_INDEX, 102273b5176SLizhi Hou .mbox_bar = NPU6_MBOX_BAR_INDEX, 103273b5176SLizhi Hou .sram_bar = NPU6_SRAM_BAR_INDEX, 104273b5176SLizhi Hou .psp_bar = NPU6_PSP_BAR_INDEX, 105273b5176SLizhi Hou .smu_bar = NPU6_SMU_BAR_INDEX, 106273b5176SLizhi Hou .first_col = 0, 107273b5176SLizhi Hou .dev_mem_buf_shift = 15, /* 32 KiB aligned */ 108273b5176SLizhi Hou .dev_mem_base = AIE2_DEVM_BASE, 109273b5176SLizhi Hou .dev_mem_size = AIE2_DEVM_SIZE, 110273b5176SLizhi Hou .vbnv = "RyzenAI-npu6", 111273b5176SLizhi Hou .device_type = AMDXDNA_DEV_TYPE_KMQ, 112273b5176SLizhi Hou .dev_priv = &npu6_dev_priv, 113273b5176SLizhi Hou .ops = &aie2_ops, 114273b5176SLizhi Hou }; 115