18c9ff1b1SLizhi Hou // SPDX-License-Identifier: GPL-2.0 28c9ff1b1SLizhi Hou /* 38c9ff1b1SLizhi Hou * Copyright (C) 2024, Advanced Micro Devices, Inc. 48c9ff1b1SLizhi Hou */ 58c9ff1b1SLizhi Hou 68c9ff1b1SLizhi Hou #include <drm/amdxdna_accel.h> 78c9ff1b1SLizhi Hou #include <drm/drm_device.h> 8aac24309SLizhi Hou #include <drm/gpu_scheduler.h> 98c9ff1b1SLizhi Hou #include <linux/sizes.h> 108c9ff1b1SLizhi Hou 118c9ff1b1SLizhi Hou #include "aie2_pci.h" 12b87f920bSLizhi Hou #include "amdxdna_mailbox.h" 138c9ff1b1SLizhi Hou #include "amdxdna_pci_drv.h" 148c9ff1b1SLizhi Hou 158c9ff1b1SLizhi Hou /* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */ 168c9ff1b1SLizhi Hou #define MPNPU_PUB_SEC_INTR 0x3010060 178c9ff1b1SLizhi Hou #define MPNPU_PUB_PWRMGMT_INTR 0x3010064 188c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH0 0x301006C 198c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH1 0x3010070 208c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH2 0x3010074 218c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH3 0x3010078 228c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH4 0x301007C 238c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH5 0x3010080 248c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH6 0x3010084 258c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH7 0x3010088 268c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH8 0x301008C 278c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH9 0x3010090 288c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH10 0x3010094 298c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH11 0x3010098 308c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH12 0x301009C 318c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH13 0x30100A0 328c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH14 0x30100A4 338c9ff1b1SLizhi Hou #define MPNPU_PUB_SCRATCH15 0x30100A8 348c9ff1b1SLizhi Hou #define MP0_C2PMSG_73 0x3810A24 358c9ff1b1SLizhi Hou #define MP0_C2PMSG_123 0x3810AEC 368c9ff1b1SLizhi Hou 378c9ff1b1SLizhi Hou #define MP1_C2PMSG_0 0x3B10900 388c9ff1b1SLizhi Hou #define MP1_C2PMSG_60 0x3B109F0 398c9ff1b1SLizhi Hou #define MP1_C2PMSG_61 0x3B109F4 408c9ff1b1SLizhi Hou 418c9ff1b1SLizhi Hou #define MPNPU_SRAM_X2I_MAILBOX_0 0x3600000 428c9ff1b1SLizhi Hou #define MPNPU_SRAM_X2I_MAILBOX_15 0x361E000 438c9ff1b1SLizhi Hou #define MPNPU_SRAM_X2I_MAILBOX_31 0x363E000 448c9ff1b1SLizhi Hou #define MPNPU_SRAM_I2X_MAILBOX_31 0x363F000 458c9ff1b1SLizhi Hou 468c9ff1b1SLizhi Hou #define MMNPU_APERTURE0_BASE 0x3000000 478c9ff1b1SLizhi Hou #define MMNPU_APERTURE1_BASE 0x3600000 488c9ff1b1SLizhi Hou #define MMNPU_APERTURE3_BASE 0x3810000 498c9ff1b1SLizhi Hou #define MMNPU_APERTURE4_BASE 0x3B10000 508c9ff1b1SLizhi Hou 518c9ff1b1SLizhi Hou /* PCIe BAR Index for NPU5 */ 528c9ff1b1SLizhi Hou #define NPU5_REG_BAR_INDEX 0 538c9ff1b1SLizhi Hou #define NPU5_MBOX_BAR_INDEX 0 548c9ff1b1SLizhi Hou #define NPU5_PSP_BAR_INDEX 4 558c9ff1b1SLizhi Hou #define NPU5_SMU_BAR_INDEX 5 568c9ff1b1SLizhi Hou #define NPU5_SRAM_BAR_INDEX 2 578c9ff1b1SLizhi Hou /* Associated BARs and Apertures */ 588c9ff1b1SLizhi Hou #define NPU5_REG_BAR_BASE MMNPU_APERTURE0_BASE 598c9ff1b1SLizhi Hou #define NPU5_MBOX_BAR_BASE MMNPU_APERTURE0_BASE 608c9ff1b1SLizhi Hou #define NPU5_PSP_BAR_BASE MMNPU_APERTURE3_BASE 618c9ff1b1SLizhi Hou #define NPU5_SMU_BAR_BASE MMNPU_APERTURE4_BASE 628c9ff1b1SLizhi Hou #define NPU5_SRAM_BAR_BASE MMNPU_APERTURE1_BASE 638c9ff1b1SLizhi Hou 64*71486e48SLizhi Hou static const struct amdxdna_dev_priv npu5_dev_priv = { 658c9ff1b1SLizhi Hou .fw_path = "amdnpu/17f0_11/npu.sbin", 668c9ff1b1SLizhi Hou .protocol_major = 0x6, 67b1dcfe62SLizhi Hou .protocol_minor = 12, 68f4d7b8a6SLizhi Hou .rt_config = npu4_default_rt_cfg, 69f4d7b8a6SLizhi Hou .dpm_clk_tbl = npu4_dpm_clk_table, 708c9ff1b1SLizhi Hou .col_align = COL_ALIGN_NATURE, 718c9ff1b1SLizhi Hou .mbox_dev_addr = NPU5_MBOX_BAR_BASE, 728c9ff1b1SLizhi Hou .mbox_size = 0, /* Use BAR size */ 738c9ff1b1SLizhi Hou .sram_dev_addr = NPU5_SRAM_BAR_BASE, 748c9ff1b1SLizhi Hou .sram_offs = { 758c9ff1b1SLizhi Hou DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU5_SRAM, MPNPU_SRAM_X2I_MAILBOX_0), 768c9ff1b1SLizhi Hou DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU5_SRAM, MPNPU_SRAM_X2I_MAILBOX_15), 778c9ff1b1SLizhi Hou }, 788c9ff1b1SLizhi Hou .psp_regs_off = { 798c9ff1b1SLizhi Hou DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU5_PSP, MP0_C2PMSG_123), 808c9ff1b1SLizhi Hou DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU5_REG, MPNPU_PUB_SCRATCH3), 818c9ff1b1SLizhi Hou DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU5_REG, MPNPU_PUB_SCRATCH4), 828c9ff1b1SLizhi Hou DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU5_REG, MPNPU_PUB_SCRATCH9), 838c9ff1b1SLizhi Hou DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU5_PSP, MP0_C2PMSG_73), 848c9ff1b1SLizhi Hou DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU5_PSP, MP0_C2PMSG_123), 858c9ff1b1SLizhi Hou DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU5_REG, MPNPU_PUB_SCRATCH3), 868c9ff1b1SLizhi Hou }, 878c9ff1b1SLizhi Hou .smu_regs_off = { 888c9ff1b1SLizhi Hou DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU5_SMU, MP1_C2PMSG_0), 898c9ff1b1SLizhi Hou DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU5_SMU, MP1_C2PMSG_60), 908c9ff1b1SLizhi Hou DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU5_SMU, MMNPU_APERTURE4_BASE), 918c9ff1b1SLizhi Hou DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU5_SMU, MP1_C2PMSG_61), 928c9ff1b1SLizhi Hou DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU5_SMU, MP1_C2PMSG_60), 938c9ff1b1SLizhi Hou }, 94f4d7b8a6SLizhi Hou .hw_ops = { 95f4d7b8a6SLizhi Hou .set_dpm = npu4_set_dpm, 96f4d7b8a6SLizhi Hou }, 978c9ff1b1SLizhi Hou }; 988c9ff1b1SLizhi Hou 998c9ff1b1SLizhi Hou const struct amdxdna_dev_info dev_npu5_info = { 1008c9ff1b1SLizhi Hou .reg_bar = NPU5_REG_BAR_INDEX, 1018c9ff1b1SLizhi Hou .mbox_bar = NPU5_MBOX_BAR_INDEX, 1028c9ff1b1SLizhi Hou .sram_bar = NPU5_SRAM_BAR_INDEX, 1038c9ff1b1SLizhi Hou .psp_bar = NPU5_PSP_BAR_INDEX, 1048c9ff1b1SLizhi Hou .smu_bar = NPU5_SMU_BAR_INDEX, 1058c9ff1b1SLizhi Hou .first_col = 0, 1068c9ff1b1SLizhi Hou .dev_mem_buf_shift = 15, /* 32 KiB aligned */ 1078c9ff1b1SLizhi Hou .dev_mem_base = AIE2_DEVM_BASE, 1088c9ff1b1SLizhi Hou .dev_mem_size = AIE2_DEVM_SIZE, 1098c9ff1b1SLizhi Hou .vbnv = "RyzenAI-npu5", 1108c9ff1b1SLizhi Hou .device_type = AMDXDNA_DEV_TYPE_KMQ, 1118c9ff1b1SLizhi Hou .dev_priv = &npu5_dev_priv, 1128c9ff1b1SLizhi Hou .ops = &aie2_ops, 1138c9ff1b1SLizhi Hou }; 114