1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #include <drm/amdxdna_accel.h> 7 #include <drm/drm_device.h> 8 #include <linux/sizes.h> 9 10 #include "aie2_pci.h" 11 #include "amdxdna_pci_drv.h" 12 13 /* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */ 14 #define MPNPU_PUB_SEC_INTR 0x3010060 15 #define MPNPU_PUB_PWRMGMT_INTR 0x3010064 16 #define MPNPU_PUB_SCRATCH0 0x301006C 17 #define MPNPU_PUB_SCRATCH1 0x3010070 18 #define MPNPU_PUB_SCRATCH2 0x3010074 19 #define MPNPU_PUB_SCRATCH3 0x3010078 20 #define MPNPU_PUB_SCRATCH4 0x301007C 21 #define MPNPU_PUB_SCRATCH5 0x3010080 22 #define MPNPU_PUB_SCRATCH6 0x3010084 23 #define MPNPU_PUB_SCRATCH7 0x3010088 24 #define MPNPU_PUB_SCRATCH8 0x301008C 25 #define MPNPU_PUB_SCRATCH9 0x3010090 26 #define MPNPU_PUB_SCRATCH10 0x3010094 27 #define MPNPU_PUB_SCRATCH11 0x3010098 28 #define MPNPU_PUB_SCRATCH12 0x301009C 29 #define MPNPU_PUB_SCRATCH13 0x30100A0 30 #define MPNPU_PUB_SCRATCH14 0x30100A4 31 #define MPNPU_PUB_SCRATCH15 0x30100A8 32 #define MP0_C2PMSG_73 0x3810A24 33 #define MP0_C2PMSG_123 0x3810AEC 34 35 #define MP1_C2PMSG_0 0x3B10900 36 #define MP1_C2PMSG_60 0x3B109F0 37 #define MP1_C2PMSG_61 0x3B109F4 38 39 #define MPNPU_SRAM_X2I_MAILBOX_0 0x3600000 40 #define MPNPU_SRAM_X2I_MAILBOX_15 0x361E000 41 #define MPNPU_SRAM_X2I_MAILBOX_31 0x363E000 42 #define MPNPU_SRAM_I2X_MAILBOX_31 0x363F000 43 44 #define MMNPU_APERTURE0_BASE 0x3000000 45 #define MMNPU_APERTURE1_BASE 0x3600000 46 #define MMNPU_APERTURE3_BASE 0x3810000 47 #define MMNPU_APERTURE4_BASE 0x3B10000 48 49 /* PCIe BAR Index for NPU4 */ 50 #define NPU4_REG_BAR_INDEX 0 51 #define NPU4_MBOX_BAR_INDEX 0 52 #define NPU4_PSP_BAR_INDEX 4 53 #define NPU4_SMU_BAR_INDEX 5 54 #define NPU4_SRAM_BAR_INDEX 2 55 /* Associated BARs and Apertures */ 56 #define NPU4_REG_BAR_BASE MMNPU_APERTURE0_BASE 57 #define NPU4_MBOX_BAR_BASE MMNPU_APERTURE0_BASE 58 #define NPU4_PSP_BAR_BASE MMNPU_APERTURE3_BASE 59 #define NPU4_SMU_BAR_BASE MMNPU_APERTURE4_BASE 60 #define NPU4_SRAM_BAR_BASE MMNPU_APERTURE1_BASE 61 62 #define NPU4_RT_CFG_TYPE_PDI_LOAD 5 63 #define NPU4_RT_CFG_VAL_PDI_LOAD_MGMT 0 64 #define NPU4_RT_CFG_VAL_PDI_LOAD_APP 1 65 66 #define NPU4_MPNPUCLK_FREQ_MAX 1267 67 #define NPU4_HCLK_FREQ_MAX 1800 68 69 const struct amdxdna_dev_priv npu4_dev_priv = { 70 .fw_path = "amdnpu/17f0_10/npu.sbin", 71 .protocol_major = 0x6, 72 .protocol_minor = 0x1, 73 .rt_config = {NPU4_RT_CFG_TYPE_PDI_LOAD, NPU4_RT_CFG_VAL_PDI_LOAD_APP}, 74 .col_align = COL_ALIGN_NATURE, 75 .mbox_dev_addr = NPU4_MBOX_BAR_BASE, 76 .mbox_size = 0, /* Use BAR size */ 77 .sram_dev_addr = NPU4_SRAM_BAR_BASE, 78 .sram_offs = { 79 DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU4_SRAM, MPNPU_SRAM_X2I_MAILBOX_0), 80 DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU4_SRAM, MPNPU_SRAM_X2I_MAILBOX_15), 81 }, 82 .psp_regs_off = { 83 DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU4_PSP, MP0_C2PMSG_123), 84 DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU4_REG, MPNPU_PUB_SCRATCH3), 85 DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU4_REG, MPNPU_PUB_SCRATCH4), 86 DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU4_REG, MPNPU_PUB_SCRATCH9), 87 DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU4_PSP, MP0_C2PMSG_73), 88 DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU4_PSP, MP0_C2PMSG_123), 89 DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU4_REG, MPNPU_PUB_SCRATCH3), 90 }, 91 .smu_regs_off = { 92 DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU4_SMU, MP1_C2PMSG_0), 93 DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU4_SMU, MP1_C2PMSG_60), 94 DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU4_SMU, MMNPU_APERTURE4_BASE), 95 DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU4_SMU, MP1_C2PMSG_61), 96 DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU4_SMU, MP1_C2PMSG_60), 97 }, 98 .smu_mpnpuclk_freq_max = NPU4_MPNPUCLK_FREQ_MAX, 99 .smu_hclk_freq_max = NPU4_HCLK_FREQ_MAX, 100 }; 101 102 const struct amdxdna_dev_info dev_npu4_info = { 103 .reg_bar = NPU4_REG_BAR_INDEX, 104 .mbox_bar = NPU4_MBOX_BAR_INDEX, 105 .sram_bar = NPU4_SRAM_BAR_INDEX, 106 .psp_bar = NPU4_PSP_BAR_INDEX, 107 .smu_bar = NPU4_SMU_BAR_INDEX, 108 .first_col = 0, 109 .dev_mem_buf_shift = 15, /* 32 KiB aligned */ 110 .dev_mem_base = AIE2_DEVM_BASE, 111 .dev_mem_size = AIE2_DEVM_SIZE, 112 .vbnv = "RyzenAI-npu4", 113 .device_type = AMDXDNA_DEV_TYPE_KMQ, 114 .dev_priv = &npu4_dev_priv, 115 .ops = &aie2_ops, /* NPU4 can share NPU1's callback */ 116 }; 117