1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #include <drm/amdxdna_accel.h> 7 #include <drm/drm_device.h> 8 #include <drm/gpu_scheduler.h> 9 #include <linux/sizes.h> 10 11 #include "aie2_pci.h" 12 #include "amdxdna_mailbox.h" 13 #include "amdxdna_pci_drv.h" 14 15 /* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */ 16 #define MPNPU_PUB_SEC_INTR 0x3010060 17 #define MPNPU_PUB_PWRMGMT_INTR 0x3010064 18 #define MPNPU_PUB_SCRATCH0 0x301006C 19 #define MPNPU_PUB_SCRATCH1 0x3010070 20 #define MPNPU_PUB_SCRATCH2 0x3010074 21 #define MPNPU_PUB_SCRATCH3 0x3010078 22 #define MPNPU_PUB_SCRATCH4 0x301007C 23 #define MPNPU_PUB_SCRATCH5 0x3010080 24 #define MPNPU_PUB_SCRATCH6 0x3010084 25 #define MPNPU_PUB_SCRATCH7 0x3010088 26 #define MPNPU_PUB_SCRATCH8 0x301008C 27 #define MPNPU_PUB_SCRATCH9 0x3010090 28 #define MPNPU_PUB_SCRATCH10 0x3010094 29 #define MPNPU_PUB_SCRATCH11 0x3010098 30 #define MPNPU_PUB_SCRATCH12 0x301009C 31 #define MPNPU_PUB_SCRATCH13 0x30100A0 32 #define MPNPU_PUB_SCRATCH14 0x30100A4 33 #define MPNPU_PUB_SCRATCH15 0x30100A8 34 #define MP0_C2PMSG_73 0x3810A24 35 #define MP0_C2PMSG_123 0x3810AEC 36 37 #define MP1_C2PMSG_0 0x3B10900 38 #define MP1_C2PMSG_60 0x3B109F0 39 #define MP1_C2PMSG_61 0x3B109F4 40 41 #define MPNPU_SRAM_X2I_MAILBOX_0 0x3600000 42 #define MPNPU_SRAM_X2I_MAILBOX_15 0x361E000 43 #define MPNPU_SRAM_X2I_MAILBOX_31 0x363E000 44 #define MPNPU_SRAM_I2X_MAILBOX_31 0x363F000 45 46 #define MMNPU_APERTURE0_BASE 0x3000000 47 #define MMNPU_APERTURE1_BASE 0x3600000 48 #define MMNPU_APERTURE3_BASE 0x3810000 49 #define MMNPU_APERTURE4_BASE 0x3B10000 50 51 /* PCIe BAR Index for NPU2 */ 52 #define NPU2_REG_BAR_INDEX 0 53 #define NPU2_MBOX_BAR_INDEX 0 54 #define NPU2_PSP_BAR_INDEX 4 55 #define NPU2_SMU_BAR_INDEX 5 56 #define NPU2_SRAM_BAR_INDEX 2 57 /* Associated BARs and Apertures */ 58 #define NPU2_REG_BAR_BASE MMNPU_APERTURE0_BASE 59 #define NPU2_MBOX_BAR_BASE MMNPU_APERTURE0_BASE 60 #define NPU2_PSP_BAR_BASE MMNPU_APERTURE3_BASE 61 #define NPU2_SMU_BAR_BASE MMNPU_APERTURE4_BASE 62 #define NPU2_SRAM_BAR_BASE MMNPU_APERTURE1_BASE 63 64 #define NPU2_RT_CFG_TYPE_PDI_LOAD 5 65 #define NPU2_RT_CFG_VAL_PDI_LOAD_MGMT 0 66 #define NPU2_RT_CFG_VAL_PDI_LOAD_APP 1 67 68 #define NPU2_MPNPUCLK_FREQ_MAX 1267 69 #define NPU2_HCLK_FREQ_MAX 1800 70 71 const struct amdxdna_dev_priv npu2_dev_priv = { 72 .fw_path = "amdnpu/17f0_00/npu.sbin", 73 .protocol_major = 0x6, 74 .protocol_minor = 0x1, 75 .rt_config = {NPU2_RT_CFG_TYPE_PDI_LOAD, NPU2_RT_CFG_VAL_PDI_LOAD_APP}, 76 .col_align = COL_ALIGN_NATURE, 77 .mbox_dev_addr = NPU2_MBOX_BAR_BASE, 78 .mbox_size = 0, /* Use BAR size */ 79 .sram_dev_addr = NPU2_SRAM_BAR_BASE, 80 .sram_offs = { 81 DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU2_SRAM, MPNPU_SRAM_X2I_MAILBOX_0), 82 DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU2_SRAM, MPNPU_SRAM_X2I_MAILBOX_15), 83 }, 84 .psp_regs_off = { 85 DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU2_PSP, MP0_C2PMSG_123), 86 DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU2_REG, MPNPU_PUB_SCRATCH3), 87 DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU2_REG, MPNPU_PUB_SCRATCH4), 88 DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU2_REG, MPNPU_PUB_SCRATCH9), 89 DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU2_PSP, MP0_C2PMSG_73), 90 DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU2_PSP, MP0_C2PMSG_123), 91 DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU2_REG, MPNPU_PUB_SCRATCH3), 92 }, 93 .smu_regs_off = { 94 DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU2_SMU, MP1_C2PMSG_0), 95 DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU2_SMU, MP1_C2PMSG_60), 96 DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU2_SMU, MMNPU_APERTURE4_BASE), 97 DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU2_SMU, MP1_C2PMSG_61), 98 DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU2_SMU, MP1_C2PMSG_60), 99 }, 100 .smu_mpnpuclk_freq_max = NPU2_MPNPUCLK_FREQ_MAX, 101 .smu_hclk_freq_max = NPU2_HCLK_FREQ_MAX, 102 }; 103 104 const struct amdxdna_dev_info dev_npu2_info = { 105 .reg_bar = NPU2_REG_BAR_INDEX, 106 .mbox_bar = NPU2_MBOX_BAR_INDEX, 107 .sram_bar = NPU2_SRAM_BAR_INDEX, 108 .psp_bar = NPU2_PSP_BAR_INDEX, 109 .smu_bar = NPU2_SMU_BAR_INDEX, 110 .first_col = 0, 111 .dev_mem_buf_shift = 15, /* 32 KiB aligned */ 112 .dev_mem_base = AIE2_DEVM_BASE, 113 .dev_mem_size = AIE2_DEVM_SIZE, 114 .vbnv = "RyzenAI-npu2", 115 .device_type = AMDXDNA_DEV_TYPE_KMQ, 116 .dev_priv = &npu2_dev_priv, 117 .ops = &aie2_ops, /* NPU2 can share NPU1's callback */ 118 }; 119