1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 271b973a4SNobuhiro Iwamatsu #ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H 371b973a4SNobuhiro Iwamatsu #define __ASM_SH_CPU_SH4_DMA_SH7780_H 471b973a4SNobuhiro Iwamatsu 59f380456SPaul Mundt #include <linux/sh_intc.h> 69f380456SPaul Mundt 771b973a4SNobuhiro Iwamatsu #if defined(CONFIG_CPU_SUBTYPE_SH7343) || \ 871b973a4SNobuhiro Iwamatsu defined(CONFIG_CPU_SUBTYPE_SH7730) 99f380456SPaul Mundt #define DMTE0_IRQ evt2irq(0x800) 109f380456SPaul Mundt #define DMTE4_IRQ evt2irq(0xb80) 119f380456SPaul Mundt #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ 1271b973a4SNobuhiro Iwamatsu #define SH_DMAC_BASE0 0xFE008020 13623b4ac4SGuennadi Liakhovetski #elif defined(CONFIG_CPU_SUBTYPE_SH7722) 149f380456SPaul Mundt #define DMTE0_IRQ evt2irq(0x800) 159f380456SPaul Mundt #define DMTE4_IRQ evt2irq(0xb80) 169f380456SPaul Mundt #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ 17623b4ac4SGuennadi Liakhovetski #define SH_DMAC_BASE0 0xFE008020 18455f9726SRichard Weinberger #elif defined(CONFIG_CPU_SUBTYPE_SH7763) 199f380456SPaul Mundt #define DMTE0_IRQ evt2irq(0x640) 209f380456SPaul Mundt #define DMTE4_IRQ evt2irq(0x780) 219f380456SPaul Mundt #define DMAE0_IRQ evt2irq(0x6c0) 2271b973a4SNobuhiro Iwamatsu #define SH_DMAC_BASE0 0xFF608020 23623b4ac4SGuennadi Liakhovetski #elif defined(CONFIG_CPU_SUBTYPE_SH7723) 249f380456SPaul Mundt #define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/ 259f380456SPaul Mundt #define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */ 269f380456SPaul Mundt #define DMTE6_IRQ evt2irq(0x700) 279f380456SPaul Mundt #define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */ 289f380456SPaul Mundt #define DMTE9_IRQ evt2irq(0x760) 299f380456SPaul Mundt #define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */ 309f380456SPaul Mundt #define DMTE11_IRQ evt2irq(0xb20) 319f380456SPaul Mundt #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ 329f380456SPaul Mundt #define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/ 3371b973a4SNobuhiro Iwamatsu #define SH_DMAC_BASE0 0xFE008020 3471b973a4SNobuhiro Iwamatsu #define SH_DMAC_BASE1 0xFDC08020 35623b4ac4SGuennadi Liakhovetski #elif defined(CONFIG_CPU_SUBTYPE_SH7724) 369f380456SPaul Mundt #define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/ 379f380456SPaul Mundt #define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */ 389f380456SPaul Mundt #define DMTE6_IRQ evt2irq(0x700) 399f380456SPaul Mundt #define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */ 409f380456SPaul Mundt #define DMTE9_IRQ evt2irq(0x760) 419f380456SPaul Mundt #define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */ 429f380456SPaul Mundt #define DMTE11_IRQ evt2irq(0xb20) 439f380456SPaul Mundt #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ 449f380456SPaul Mundt #define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/ 45623b4ac4SGuennadi Liakhovetski #define SH_DMAC_BASE0 0xFE008020 46623b4ac4SGuennadi Liakhovetski #define SH_DMAC_BASE1 0xFDC08020 4771b973a4SNobuhiro Iwamatsu #elif defined(CONFIG_CPU_SUBTYPE_SH7780) 489f380456SPaul Mundt #define DMTE0_IRQ evt2irq(0x640) 499f380456SPaul Mundt #define DMTE4_IRQ evt2irq(0x780) 509f380456SPaul Mundt #define DMTE6_IRQ evt2irq(0x7c0) 519f380456SPaul Mundt #define DMTE8_IRQ evt2irq(0xd80) 529f380456SPaul Mundt #define DMTE9_IRQ evt2irq(0xda0) 539f380456SPaul Mundt #define DMTE10_IRQ evt2irq(0xdc0) 549f380456SPaul Mundt #define DMTE11_IRQ evt2irq(0xde0) 559f380456SPaul Mundt #define DMAE0_IRQ evt2irq(0x6c0) /* DMA Error IRQ */ 5671b973a4SNobuhiro Iwamatsu #define SH_DMAC_BASE0 0xFC808020 5771b973a4SNobuhiro Iwamatsu #define SH_DMAC_BASE1 0xFC818020 5871b973a4SNobuhiro Iwamatsu #else /* SH7785 */ 599f380456SPaul Mundt #define DMTE0_IRQ evt2irq(0x620) 609f380456SPaul Mundt #define DMTE4_IRQ evt2irq(0x6a0) 619f380456SPaul Mundt #define DMTE6_IRQ evt2irq(0x880) 629f380456SPaul Mundt #define DMTE8_IRQ evt2irq(0x8c0) 639f380456SPaul Mundt #define DMTE9_IRQ evt2irq(0x8e0) 649f380456SPaul Mundt #define DMTE10_IRQ evt2irq(0x900) 659f380456SPaul Mundt #define DMTE11_IRQ evt2irq(0x920) 669f380456SPaul Mundt #define DMAE0_IRQ evt2irq(0x6e0) /* DMA Error IRQ0 */ 679f380456SPaul Mundt #define DMAE1_IRQ evt2irq(0x940) /* DMA Error IRQ1 */ 6871b973a4SNobuhiro Iwamatsu #define SH_DMAC_BASE0 0xFC808020 6971b973a4SNobuhiro Iwamatsu #define SH_DMAC_BASE1 0xFCC08020 7071b973a4SNobuhiro Iwamatsu #endif 7171b973a4SNobuhiro Iwamatsu 7271b973a4SNobuhiro Iwamatsu #endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */ 73