1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SMP related functions 4 * 5 * Copyright IBM Corp. 1999, 2012 6 * Author(s): Denis Joseph Barrow, 7 * Martin Schwidefsky <schwidefsky@de.ibm.com>, 8 * 9 * based on other smp stuff by 10 * (c) 1995 Alan Cox, CymruNET Ltd <alan@cymru.net> 11 * (c) 1998 Ingo Molnar 12 * 13 * The code outside of smp.c uses logical cpu numbers, only smp.c does 14 * the translation of logical to physical cpu ids. All new code that 15 * operates on physical cpu numbers needs to go into smp.c. 16 */ 17 18 #define KMSG_COMPONENT "cpu" 19 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt 20 21 #include <linux/workqueue.h> 22 #include <linux/memblock.h> 23 #include <linux/export.h> 24 #include <linux/init.h> 25 #include <linux/mm.h> 26 #include <linux/err.h> 27 #include <linux/spinlock.h> 28 #include <linux/kernel_stat.h> 29 #include <linux/delay.h> 30 #include <linux/interrupt.h> 31 #include <linux/irqflags.h> 32 #include <linux/irq_work.h> 33 #include <linux/cpu.h> 34 #include <linux/slab.h> 35 #include <linux/sched/hotplug.h> 36 #include <linux/sched/task_stack.h> 37 #include <linux/crash_dump.h> 38 #include <linux/kprobes.h> 39 #include <asm/access-regs.h> 40 #include <asm/asm-offsets.h> 41 #include <asm/ctlreg.h> 42 #include <asm/pfault.h> 43 #include <asm/diag.h> 44 #include <asm/facility.h> 45 #include <asm/fpu.h> 46 #include <asm/ipl.h> 47 #include <asm/setup.h> 48 #include <asm/irq.h> 49 #include <asm/tlbflush.h> 50 #include <asm/vtimer.h> 51 #include <asm/abs_lowcore.h> 52 #include <asm/sclp.h> 53 #include <asm/debug.h> 54 #include <asm/os_info.h> 55 #include <asm/sigp.h> 56 #include <asm/idle.h> 57 #include <asm/nmi.h> 58 #include <asm/stacktrace.h> 59 #include <asm/topology.h> 60 #include <asm/vdso.h> 61 #include <asm/maccess.h> 62 #include "entry.h" 63 64 enum { 65 ec_schedule = 0, 66 ec_call_function_single, 67 ec_stop_cpu, 68 ec_mcck_pending, 69 ec_irq_work, 70 }; 71 72 enum { 73 CPU_STATE_STANDBY, 74 CPU_STATE_CONFIGURED, 75 }; 76 77 static u8 boot_core_type; 78 DEFINE_PER_CPU(struct pcpu, pcpu_devices); 79 /* 80 * Pointer to the pcpu area of the boot CPU. This is required when a restart 81 * interrupt is triggered on an offline CPU. For that case accessing percpu 82 * data with the common primitives does not work, since the percpu offset is 83 * stored in a non existent lowcore. 84 */ 85 static struct pcpu *ipl_pcpu; 86 87 unsigned int smp_cpu_mt_shift; 88 EXPORT_SYMBOL(smp_cpu_mt_shift); 89 90 unsigned int smp_cpu_mtid; 91 EXPORT_SYMBOL(smp_cpu_mtid); 92 93 #ifdef CONFIG_CRASH_DUMP 94 __vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS]; 95 #endif 96 97 static unsigned int smp_max_threads __initdata = -1U; 98 cpumask_t cpu_setup_mask; 99 100 static int __init early_nosmt(char *s) 101 { 102 smp_max_threads = 1; 103 return 0; 104 } 105 early_param("nosmt", early_nosmt); 106 107 static int __init early_smt(char *s) 108 { 109 get_option(&s, &smp_max_threads); 110 return 0; 111 } 112 early_param("smt", early_smt); 113 114 /* 115 * The smp_cpu_state_mutex must be held when changing the state or polarization 116 * member of a pcpu data structure within the pcpu_devices array. 117 */ 118 DEFINE_MUTEX(smp_cpu_state_mutex); 119 120 /* 121 * Signal processor helper functions. 122 */ 123 static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm) 124 { 125 int cc; 126 127 while (1) { 128 cc = __pcpu_sigp(addr, order, parm, NULL); 129 if (cc != SIGP_CC_BUSY) 130 return cc; 131 cpu_relax(); 132 } 133 } 134 135 static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) 136 { 137 int cc, retry; 138 139 for (retry = 0; ; retry++) { 140 cc = __pcpu_sigp(pcpu->address, order, parm, NULL); 141 if (cc != SIGP_CC_BUSY) 142 break; 143 if (retry >= 3) 144 udelay(10); 145 } 146 return cc; 147 } 148 149 static inline int pcpu_stopped(struct pcpu *pcpu) 150 { 151 u32 status; 152 153 if (__pcpu_sigp(pcpu->address, SIGP_SENSE, 154 0, &status) != SIGP_CC_STATUS_STORED) 155 return 0; 156 return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED)); 157 } 158 159 static inline int pcpu_running(struct pcpu *pcpu) 160 { 161 if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING, 162 0, NULL) != SIGP_CC_STATUS_STORED) 163 return 1; 164 /* Status stored condition code is equivalent to cpu not running. */ 165 return 0; 166 } 167 168 /* 169 * Find struct pcpu by cpu address. 170 */ 171 static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address) 172 { 173 int cpu; 174 175 for_each_cpu(cpu, mask) 176 if (per_cpu(pcpu_devices, cpu).address == address) 177 return &per_cpu(pcpu_devices, cpu); 178 return NULL; 179 } 180 181 static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit) 182 { 183 int order; 184 185 if (test_and_set_bit(ec_bit, &pcpu->ec_mask)) 186 return; 187 order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL; 188 pcpu->ec_clk = get_tod_clock_fast(); 189 pcpu_sigp_retry(pcpu, order, 0); 190 } 191 192 static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu) 193 { 194 unsigned long async_stack, nodat_stack, mcck_stack; 195 struct lowcore *lc; 196 197 lc = (struct lowcore *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER); 198 nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER); 199 async_stack = stack_alloc(); 200 mcck_stack = stack_alloc(); 201 if (!lc || !nodat_stack || !async_stack || !mcck_stack) 202 goto out; 203 memcpy(lc, get_lowcore(), 512); 204 memset((char *) lc + 512, 0, sizeof(*lc) - 512); 205 lc->async_stack = async_stack + STACK_INIT_OFFSET; 206 lc->nodat_stack = nodat_stack + STACK_INIT_OFFSET; 207 lc->mcck_stack = mcck_stack + STACK_INIT_OFFSET; 208 lc->cpu_nr = cpu; 209 lc->spinlock_lockval = arch_spin_lockval(cpu); 210 lc->spinlock_index = 0; 211 lc->return_lpswe = gen_lpswe(__LC_RETURN_PSW); 212 lc->return_mcck_lpswe = gen_lpswe(__LC_RETURN_MCCK_PSW); 213 lc->preempt_count = PREEMPT_DISABLED; 214 if (nmi_alloc_mcesa(&lc->mcesad)) 215 goto out; 216 if (abs_lowcore_map(cpu, lc, true)) 217 goto out_mcesa; 218 lowcore_ptr[cpu] = lc; 219 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, __pa(lc)); 220 return 0; 221 222 out_mcesa: 223 nmi_free_mcesa(&lc->mcesad); 224 out: 225 stack_free(mcck_stack); 226 stack_free(async_stack); 227 free_pages(nodat_stack, THREAD_SIZE_ORDER); 228 free_pages((unsigned long) lc, LC_ORDER); 229 return -ENOMEM; 230 } 231 232 static void pcpu_free_lowcore(struct pcpu *pcpu, int cpu) 233 { 234 unsigned long async_stack, nodat_stack, mcck_stack; 235 struct lowcore *lc; 236 237 lc = lowcore_ptr[cpu]; 238 nodat_stack = lc->nodat_stack - STACK_INIT_OFFSET; 239 async_stack = lc->async_stack - STACK_INIT_OFFSET; 240 mcck_stack = lc->mcck_stack - STACK_INIT_OFFSET; 241 pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0); 242 lowcore_ptr[cpu] = NULL; 243 abs_lowcore_unmap(cpu); 244 nmi_free_mcesa(&lc->mcesad); 245 stack_free(async_stack); 246 stack_free(mcck_stack); 247 free_pages(nodat_stack, THREAD_SIZE_ORDER); 248 free_pages((unsigned long) lc, LC_ORDER); 249 } 250 251 static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu) 252 { 253 struct lowcore *lc, *abs_lc; 254 255 lc = lowcore_ptr[cpu]; 256 cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask); 257 cpumask_set_cpu(cpu, mm_cpumask(&init_mm)); 258 lc->cpu_nr = cpu; 259 lc->pcpu = (unsigned long)pcpu; 260 lc->restart_flags = RESTART_FLAG_CTLREGS; 261 lc->spinlock_lockval = arch_spin_lockval(cpu); 262 lc->spinlock_index = 0; 263 lc->percpu_offset = __per_cpu_offset[cpu]; 264 lc->kernel_asce = get_lowcore()->kernel_asce; 265 lc->user_asce = s390_invalid_asce; 266 lc->machine_flags = get_lowcore()->machine_flags; 267 lc->user_timer = lc->system_timer = 268 lc->steal_timer = lc->avg_steal_timer = 0; 269 abs_lc = get_abs_lowcore(); 270 memcpy(lc->cregs_save_area, abs_lc->cregs_save_area, sizeof(lc->cregs_save_area)); 271 put_abs_lowcore(abs_lc); 272 lc->cregs_save_area[1] = lc->kernel_asce; 273 lc->cregs_save_area[7] = lc->user_asce; 274 save_access_regs((unsigned int *) lc->access_regs_save_area); 275 arch_spin_lock_setup(cpu); 276 } 277 278 static void pcpu_attach_task(int cpu, struct task_struct *tsk) 279 { 280 struct lowcore *lc; 281 282 lc = lowcore_ptr[cpu]; 283 lc->kernel_stack = (unsigned long)task_stack_page(tsk) + STACK_INIT_OFFSET; 284 lc->current_task = (unsigned long)tsk; 285 lc->lpp = LPP_MAGIC; 286 lc->current_pid = tsk->pid; 287 lc->user_timer = tsk->thread.user_timer; 288 lc->guest_timer = tsk->thread.guest_timer; 289 lc->system_timer = tsk->thread.system_timer; 290 lc->hardirq_timer = tsk->thread.hardirq_timer; 291 lc->softirq_timer = tsk->thread.softirq_timer; 292 lc->steal_timer = 0; 293 } 294 295 static void pcpu_start_fn(int cpu, void (*func)(void *), void *data) 296 { 297 struct lowcore *lc; 298 299 lc = lowcore_ptr[cpu]; 300 lc->restart_stack = lc->kernel_stack; 301 lc->restart_fn = (unsigned long) func; 302 lc->restart_data = (unsigned long) data; 303 lc->restart_source = -1U; 304 pcpu_sigp_retry(per_cpu_ptr(&pcpu_devices, cpu), SIGP_RESTART, 0); 305 } 306 307 typedef void (pcpu_delegate_fn)(void *); 308 309 /* 310 * Call function via PSW restart on pcpu and stop the current cpu. 311 */ 312 static void __pcpu_delegate(pcpu_delegate_fn *func, void *data) 313 { 314 func(data); /* should not return */ 315 } 316 317 static void pcpu_delegate(struct pcpu *pcpu, int cpu, 318 pcpu_delegate_fn *func, 319 void *data, unsigned long stack) 320 { 321 struct lowcore *lc, *abs_lc; 322 unsigned int source_cpu; 323 324 lc = lowcore_ptr[cpu]; 325 source_cpu = stap(); 326 327 if (pcpu->address == source_cpu) { 328 call_on_stack(2, stack, void, __pcpu_delegate, 329 pcpu_delegate_fn *, func, void *, data); 330 } 331 /* Stop target cpu (if func returns this stops the current cpu). */ 332 pcpu_sigp_retry(pcpu, SIGP_STOP, 0); 333 pcpu_sigp_retry(pcpu, SIGP_CPU_RESET, 0); 334 /* Restart func on the target cpu and stop the current cpu. */ 335 if (lc) { 336 lc->restart_stack = stack; 337 lc->restart_fn = (unsigned long)func; 338 lc->restart_data = (unsigned long)data; 339 lc->restart_source = source_cpu; 340 } else { 341 abs_lc = get_abs_lowcore(); 342 abs_lc->restart_stack = stack; 343 abs_lc->restart_fn = (unsigned long)func; 344 abs_lc->restart_data = (unsigned long)data; 345 abs_lc->restart_source = source_cpu; 346 put_abs_lowcore(abs_lc); 347 } 348 asm volatile( 349 "0: sigp 0,%0,%2 # sigp restart to target cpu\n" 350 " brc 2,0b # busy, try again\n" 351 "1: sigp 0,%1,%3 # sigp stop to current cpu\n" 352 " brc 2,1b # busy, try again\n" 353 : : "d" (pcpu->address), "d" (source_cpu), 354 "K" (SIGP_RESTART), "K" (SIGP_STOP) 355 : "0", "1", "cc"); 356 for (;;) ; 357 } 358 359 /* 360 * Enable additional logical cpus for multi-threading. 361 */ 362 static int pcpu_set_smt(unsigned int mtid) 363 { 364 int cc; 365 366 if (smp_cpu_mtid == mtid) 367 return 0; 368 cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL); 369 if (cc == 0) { 370 smp_cpu_mtid = mtid; 371 smp_cpu_mt_shift = 0; 372 while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift)) 373 smp_cpu_mt_shift++; 374 per_cpu(pcpu_devices, 0).address = stap(); 375 } 376 return cc; 377 } 378 379 /* 380 * Call function on the ipl CPU. 381 */ 382 void smp_call_ipl_cpu(void (*func)(void *), void *data) 383 { 384 struct lowcore *lc = lowcore_ptr[0]; 385 386 if (ipl_pcpu->address == stap()) 387 lc = get_lowcore(); 388 389 pcpu_delegate(ipl_pcpu, 0, func, data, lc->nodat_stack); 390 } 391 392 int smp_find_processor_id(u16 address) 393 { 394 int cpu; 395 396 for_each_present_cpu(cpu) 397 if (per_cpu(pcpu_devices, cpu).address == address) 398 return cpu; 399 return -1; 400 } 401 402 void schedule_mcck_handler(void) 403 { 404 pcpu_ec_call(this_cpu_ptr(&pcpu_devices), ec_mcck_pending); 405 } 406 407 bool notrace arch_vcpu_is_preempted(int cpu) 408 { 409 if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu)) 410 return false; 411 if (pcpu_running(per_cpu_ptr(&pcpu_devices, cpu))) 412 return false; 413 return true; 414 } 415 EXPORT_SYMBOL(arch_vcpu_is_preempted); 416 417 void notrace smp_yield_cpu(int cpu) 418 { 419 if (!MACHINE_HAS_DIAG9C) 420 return; 421 diag_stat_inc_norecursion(DIAG_STAT_X09C); 422 asm volatile("diag %0,0,0x9c" 423 : : "d" (per_cpu(pcpu_devices, cpu).address)); 424 } 425 EXPORT_SYMBOL_GPL(smp_yield_cpu); 426 427 /* 428 * Send cpus emergency shutdown signal. This gives the cpus the 429 * opportunity to complete outstanding interrupts. 430 */ 431 void notrace smp_emergency_stop(void) 432 { 433 static arch_spinlock_t lock = __ARCH_SPIN_LOCK_UNLOCKED; 434 static cpumask_t cpumask; 435 u64 end; 436 int cpu; 437 438 arch_spin_lock(&lock); 439 cpumask_copy(&cpumask, cpu_online_mask); 440 cpumask_clear_cpu(smp_processor_id(), &cpumask); 441 442 end = get_tod_clock() + (1000000UL << 12); 443 for_each_cpu(cpu, &cpumask) { 444 struct pcpu *pcpu = per_cpu_ptr(&pcpu_devices, cpu); 445 set_bit(ec_stop_cpu, &pcpu->ec_mask); 446 while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL, 447 0, NULL) == SIGP_CC_BUSY && 448 get_tod_clock() < end) 449 cpu_relax(); 450 } 451 while (get_tod_clock() < end) { 452 for_each_cpu(cpu, &cpumask) 453 if (pcpu_stopped(per_cpu_ptr(&pcpu_devices, cpu))) 454 cpumask_clear_cpu(cpu, &cpumask); 455 if (cpumask_empty(&cpumask)) 456 break; 457 cpu_relax(); 458 } 459 arch_spin_unlock(&lock); 460 } 461 NOKPROBE_SYMBOL(smp_emergency_stop); 462 463 /* 464 * Stop all cpus but the current one. 465 */ 466 void smp_send_stop(void) 467 { 468 struct pcpu *pcpu; 469 int cpu; 470 471 /* Disable all interrupts/machine checks */ 472 __load_psw_mask(PSW_KERNEL_BITS); 473 trace_hardirqs_off(); 474 475 debug_set_critical(); 476 477 if (oops_in_progress) 478 smp_emergency_stop(); 479 480 /* stop all processors */ 481 for_each_online_cpu(cpu) { 482 if (cpu == smp_processor_id()) 483 continue; 484 pcpu = per_cpu_ptr(&pcpu_devices, cpu); 485 pcpu_sigp_retry(pcpu, SIGP_STOP, 0); 486 while (!pcpu_stopped(pcpu)) 487 cpu_relax(); 488 } 489 } 490 491 /* 492 * This is the main routine where commands issued by other 493 * cpus are handled. 494 */ 495 static void smp_handle_ext_call(void) 496 { 497 unsigned long bits; 498 499 /* handle bit signal external calls */ 500 bits = this_cpu_xchg(pcpu_devices.ec_mask, 0); 501 if (test_bit(ec_stop_cpu, &bits)) 502 smp_stop_cpu(); 503 if (test_bit(ec_schedule, &bits)) 504 scheduler_ipi(); 505 if (test_bit(ec_call_function_single, &bits)) 506 generic_smp_call_function_single_interrupt(); 507 if (test_bit(ec_mcck_pending, &bits)) 508 s390_handle_mcck(); 509 if (test_bit(ec_irq_work, &bits)) 510 irq_work_run(); 511 } 512 513 static void do_ext_call_interrupt(struct ext_code ext_code, 514 unsigned int param32, unsigned long param64) 515 { 516 inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS); 517 smp_handle_ext_call(); 518 } 519 520 void arch_send_call_function_ipi_mask(const struct cpumask *mask) 521 { 522 int cpu; 523 524 for_each_cpu(cpu, mask) 525 pcpu_ec_call(per_cpu_ptr(&pcpu_devices, cpu), ec_call_function_single); 526 } 527 528 void arch_send_call_function_single_ipi(int cpu) 529 { 530 pcpu_ec_call(per_cpu_ptr(&pcpu_devices, cpu), ec_call_function_single); 531 } 532 533 /* 534 * this function sends a 'reschedule' IPI to another CPU. 535 * it goes straight through and wastes no time serializing 536 * anything. Worst case is that we lose a reschedule ... 537 */ 538 void arch_smp_send_reschedule(int cpu) 539 { 540 pcpu_ec_call(per_cpu_ptr(&pcpu_devices, cpu), ec_schedule); 541 } 542 543 #ifdef CONFIG_IRQ_WORK 544 void arch_irq_work_raise(void) 545 { 546 pcpu_ec_call(this_cpu_ptr(&pcpu_devices), ec_irq_work); 547 } 548 #endif 549 550 #ifdef CONFIG_CRASH_DUMP 551 552 int smp_store_status(int cpu) 553 { 554 struct lowcore *lc; 555 struct pcpu *pcpu; 556 unsigned long pa; 557 558 pcpu = per_cpu_ptr(&pcpu_devices, cpu); 559 lc = lowcore_ptr[cpu]; 560 pa = __pa(&lc->floating_pt_save_area); 561 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS, 562 pa) != SIGP_CC_ORDER_CODE_ACCEPTED) 563 return -EIO; 564 if (!cpu_has_vx() && !MACHINE_HAS_GS) 565 return 0; 566 pa = lc->mcesad & MCESA_ORIGIN_MASK; 567 if (MACHINE_HAS_GS) 568 pa |= lc->mcesad & MCESA_LC_MASK; 569 if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS, 570 pa) != SIGP_CC_ORDER_CODE_ACCEPTED) 571 return -EIO; 572 return 0; 573 } 574 575 /* 576 * Collect CPU state of the previous, crashed system. 577 * There are three cases: 578 * 1) standard zfcp/nvme dump 579 * condition: OLDMEM_BASE == NULL && is_ipl_type_dump() == true 580 * The state for all CPUs except the boot CPU needs to be collected 581 * with sigp stop-and-store-status. The boot CPU state is located in 582 * the absolute lowcore of the memory stored in the HSA. The zcore code 583 * will copy the boot CPU state from the HSA. 584 * 2) stand-alone kdump for SCSI/NVMe (zfcp/nvme dump with swapped memory) 585 * condition: OLDMEM_BASE != NULL && is_ipl_type_dump() == true 586 * The state for all CPUs except the boot CPU needs to be collected 587 * with sigp stop-and-store-status. The firmware or the boot-loader 588 * stored the registers of the boot CPU in the absolute lowcore in the 589 * memory of the old system. 590 * 3) kdump or stand-alone kdump for DASD 591 * condition: OLDMEM_BASE != NULL && is_ipl_type_dump() == false 592 * The state for all CPUs except the boot CPU needs to be collected 593 * with sigp stop-and-store-status. The kexec code or the boot-loader 594 * stored the registers of the boot CPU in the memory of the old system. 595 * 596 * Note that the legacy kdump mode where the old kernel stored the CPU states 597 * does no longer exist: setup_arch() explicitly deactivates the elfcorehdr= 598 * kernel parameter. The is_kdump_kernel() implementation on s390 is independent 599 * of the elfcorehdr= parameter. 600 */ 601 static bool dump_available(void) 602 { 603 return oldmem_data.start || is_ipl_type_dump(); 604 } 605 606 void __init smp_save_dump_ipl_cpu(void) 607 { 608 struct save_area *sa; 609 void *regs; 610 611 if (!dump_available()) 612 return; 613 sa = save_area_alloc(true); 614 regs = memblock_alloc_or_panic(512, 8); 615 copy_oldmem_kernel(regs, __LC_FPREGS_SAVE_AREA, 512); 616 save_area_add_regs(sa, regs); 617 memblock_free(regs, 512); 618 if (cpu_has_vx()) 619 save_area_add_vxrs(sa, boot_cpu_vector_save_area); 620 } 621 622 void __init smp_save_dump_secondary_cpus(void) 623 { 624 int addr, boot_cpu_addr, max_cpu_addr; 625 struct save_area *sa; 626 void *page; 627 628 if (!dump_available()) 629 return; 630 /* Allocate a page as dumping area for the store status sigps */ 631 page = memblock_alloc_low(PAGE_SIZE, PAGE_SIZE); 632 if (!page) 633 panic("ERROR: Failed to allocate %lx bytes below %lx\n", 634 PAGE_SIZE, 1UL << 31); 635 636 /* Set multi-threading state to the previous system. */ 637 pcpu_set_smt(sclp.mtid_prev); 638 boot_cpu_addr = stap(); 639 max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev; 640 for (addr = 0; addr <= max_cpu_addr; addr++) { 641 if (addr == boot_cpu_addr) 642 continue; 643 if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) == 644 SIGP_CC_NOT_OPERATIONAL) 645 continue; 646 sa = save_area_alloc(false); 647 __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, __pa(page)); 648 save_area_add_regs(sa, page); 649 if (cpu_has_vx()) { 650 __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, __pa(page)); 651 save_area_add_vxrs(sa, page); 652 } 653 } 654 memblock_free(page, PAGE_SIZE); 655 diag_amode31_ops.diag308_reset(); 656 pcpu_set_smt(0); 657 } 658 #endif /* CONFIG_CRASH_DUMP */ 659 660 void smp_cpu_set_polarization(int cpu, int val) 661 { 662 per_cpu(pcpu_devices, cpu).polarization = val; 663 } 664 665 int smp_cpu_get_polarization(int cpu) 666 { 667 return per_cpu(pcpu_devices, cpu).polarization; 668 } 669 670 void smp_cpu_set_capacity(int cpu, unsigned long val) 671 { 672 per_cpu(pcpu_devices, cpu).capacity = val; 673 } 674 675 unsigned long smp_cpu_get_capacity(int cpu) 676 { 677 return per_cpu(pcpu_devices, cpu).capacity; 678 } 679 680 void smp_set_core_capacity(int cpu, unsigned long val) 681 { 682 int i; 683 684 cpu = smp_get_base_cpu(cpu); 685 for (i = cpu; (i <= cpu + smp_cpu_mtid) && (i < nr_cpu_ids); i++) 686 smp_cpu_set_capacity(i, val); 687 } 688 689 int smp_cpu_get_cpu_address(int cpu) 690 { 691 return per_cpu(pcpu_devices, cpu).address; 692 } 693 694 static void __ref smp_get_core_info(struct sclp_core_info *info, int early) 695 { 696 static int use_sigp_detection; 697 int address; 698 699 if (use_sigp_detection || sclp_get_core_info(info, early)) { 700 use_sigp_detection = 1; 701 for (address = 0; 702 address < (SCLP_MAX_CORES << smp_cpu_mt_shift); 703 address += (1U << smp_cpu_mt_shift)) { 704 if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) == 705 SIGP_CC_NOT_OPERATIONAL) 706 continue; 707 info->core[info->configured].core_id = 708 address >> smp_cpu_mt_shift; 709 info->configured++; 710 } 711 info->combined = info->configured; 712 } 713 } 714 715 static int smp_add_core(struct sclp_core_entry *core, cpumask_t *avail, 716 bool configured, bool early) 717 { 718 struct pcpu *pcpu; 719 int cpu, nr, i; 720 u16 address; 721 722 nr = 0; 723 if (sclp.has_core_type && core->type != boot_core_type) 724 return nr; 725 cpu = cpumask_first(avail); 726 address = core->core_id << smp_cpu_mt_shift; 727 for (i = 0; (i <= smp_cpu_mtid) && (cpu < nr_cpu_ids); i++) { 728 if (pcpu_find_address(cpu_present_mask, address + i)) 729 continue; 730 pcpu = per_cpu_ptr(&pcpu_devices, cpu); 731 pcpu->address = address + i; 732 if (configured) 733 pcpu->state = CPU_STATE_CONFIGURED; 734 else 735 pcpu->state = CPU_STATE_STANDBY; 736 smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN); 737 smp_cpu_set_capacity(cpu, CPU_CAPACITY_HIGH); 738 set_cpu_present(cpu, true); 739 if (!early && arch_register_cpu(cpu)) 740 set_cpu_present(cpu, false); 741 else 742 nr++; 743 cpumask_clear_cpu(cpu, avail); 744 cpu = cpumask_next(cpu, avail); 745 } 746 return nr; 747 } 748 749 static int __smp_rescan_cpus(struct sclp_core_info *info, bool early) 750 { 751 struct sclp_core_entry *core; 752 static cpumask_t avail; 753 bool configured; 754 u16 core_id; 755 int nr, i; 756 757 cpus_read_lock(); 758 mutex_lock(&smp_cpu_state_mutex); 759 nr = 0; 760 cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask); 761 /* 762 * Add IPL core first (which got logical CPU number 0) to make sure 763 * that all SMT threads get subsequent logical CPU numbers. 764 */ 765 if (early) { 766 core_id = per_cpu(pcpu_devices, 0).address >> smp_cpu_mt_shift; 767 for (i = 0; i < info->configured; i++) { 768 core = &info->core[i]; 769 if (core->core_id == core_id) { 770 nr += smp_add_core(core, &avail, true, early); 771 break; 772 } 773 } 774 } 775 for (i = 0; i < info->combined; i++) { 776 configured = i < info->configured; 777 nr += smp_add_core(&info->core[i], &avail, configured, early); 778 } 779 mutex_unlock(&smp_cpu_state_mutex); 780 cpus_read_unlock(); 781 return nr; 782 } 783 784 void __init smp_detect_cpus(void) 785 { 786 unsigned int cpu, mtid, c_cpus, s_cpus; 787 struct sclp_core_info *info; 788 u16 address; 789 790 /* Get CPU information */ 791 info = memblock_alloc_or_panic(sizeof(*info), 8); 792 smp_get_core_info(info, 1); 793 /* Find boot CPU type */ 794 if (sclp.has_core_type) { 795 address = stap(); 796 for (cpu = 0; cpu < info->combined; cpu++) 797 if (info->core[cpu].core_id == address) { 798 /* The boot cpu dictates the cpu type. */ 799 boot_core_type = info->core[cpu].type; 800 break; 801 } 802 if (cpu >= info->combined) 803 panic("Could not find boot CPU type"); 804 } 805 806 /* Set multi-threading state for the current system */ 807 mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp; 808 mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1; 809 pcpu_set_smt(mtid); 810 811 /* Print number of CPUs */ 812 c_cpus = s_cpus = 0; 813 for (cpu = 0; cpu < info->combined; cpu++) { 814 if (sclp.has_core_type && 815 info->core[cpu].type != boot_core_type) 816 continue; 817 if (cpu < info->configured) 818 c_cpus += smp_cpu_mtid + 1; 819 else 820 s_cpus += smp_cpu_mtid + 1; 821 } 822 pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus); 823 memblock_free(info, sizeof(*info)); 824 } 825 826 /* 827 * Activate a secondary processor. 828 */ 829 static void smp_start_secondary(void *cpuvoid) 830 { 831 struct lowcore *lc = get_lowcore(); 832 int cpu = raw_smp_processor_id(); 833 834 lc->last_update_clock = get_tod_clock(); 835 lc->restart_stack = (unsigned long)restart_stack; 836 lc->restart_fn = (unsigned long)do_restart; 837 lc->restart_data = 0; 838 lc->restart_source = -1U; 839 lc->restart_flags = 0; 840 restore_access_regs(lc->access_regs_save_area); 841 cpu_init(); 842 rcutree_report_cpu_starting(cpu); 843 init_cpu_timer(); 844 vtime_init(); 845 vdso_getcpu_init(); 846 pfault_init(); 847 cpumask_set_cpu(cpu, &cpu_setup_mask); 848 update_cpu_masks(); 849 notify_cpu_starting(cpu); 850 if (topology_cpu_dedicated(cpu)) 851 set_cpu_flag(CIF_DEDICATED_CPU); 852 else 853 clear_cpu_flag(CIF_DEDICATED_CPU); 854 set_cpu_online(cpu, true); 855 inc_irq_stat(CPU_RST); 856 local_irq_enable(); 857 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 858 } 859 860 /* Upping and downing of CPUs */ 861 int __cpu_up(unsigned int cpu, struct task_struct *tidle) 862 { 863 struct pcpu *pcpu = per_cpu_ptr(&pcpu_devices, cpu); 864 int rc; 865 866 if (pcpu->state != CPU_STATE_CONFIGURED) 867 return -EIO; 868 if (pcpu_sigp_retry(pcpu, SIGP_INITIAL_CPU_RESET, 0) != 869 SIGP_CC_ORDER_CODE_ACCEPTED) 870 return -EIO; 871 872 rc = pcpu_alloc_lowcore(pcpu, cpu); 873 if (rc) 874 return rc; 875 /* 876 * Make sure global control register contents do not change 877 * until new CPU has initialized control registers. 878 */ 879 system_ctlreg_lock(); 880 pcpu_prepare_secondary(pcpu, cpu); 881 pcpu_attach_task(cpu, tidle); 882 pcpu_start_fn(cpu, smp_start_secondary, NULL); 883 /* Wait until cpu puts itself in the online & active maps */ 884 while (!cpu_online(cpu)) 885 cpu_relax(); 886 system_ctlreg_unlock(); 887 return 0; 888 } 889 890 static unsigned int setup_possible_cpus __initdata; 891 892 static int __init _setup_possible_cpus(char *s) 893 { 894 get_option(&s, &setup_possible_cpus); 895 return 0; 896 } 897 early_param("possible_cpus", _setup_possible_cpus); 898 899 int __cpu_disable(void) 900 { 901 struct ctlreg cregs[16]; 902 int cpu; 903 904 /* Handle possible pending IPIs */ 905 smp_handle_ext_call(); 906 cpu = smp_processor_id(); 907 set_cpu_online(cpu, false); 908 cpumask_clear_cpu(cpu, &cpu_setup_mask); 909 update_cpu_masks(); 910 /* Disable pseudo page faults on this cpu. */ 911 pfault_fini(); 912 /* Disable interrupt sources via control register. */ 913 __local_ctl_store(0, 15, cregs); 914 cregs[0].val &= ~0x0000ee70UL; /* disable all external interrupts */ 915 cregs[6].val &= ~0xff000000UL; /* disable all I/O interrupts */ 916 cregs[14].val &= ~0x1f000000UL; /* disable most machine checks */ 917 __local_ctl_load(0, 15, cregs); 918 clear_cpu_flag(CIF_NOHZ_DELAY); 919 return 0; 920 } 921 922 void __cpu_die(unsigned int cpu) 923 { 924 struct pcpu *pcpu; 925 926 /* Wait until target cpu is down */ 927 pcpu = per_cpu_ptr(&pcpu_devices, cpu); 928 while (!pcpu_stopped(pcpu)) 929 cpu_relax(); 930 pcpu_free_lowcore(pcpu, cpu); 931 cpumask_clear_cpu(cpu, mm_cpumask(&init_mm)); 932 cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask); 933 pcpu->flags = 0; 934 } 935 936 void __noreturn cpu_die(void) 937 { 938 idle_task_exit(); 939 pcpu_sigp_retry(this_cpu_ptr(&pcpu_devices), SIGP_STOP, 0); 940 for (;;) ; 941 } 942 943 void __init smp_fill_possible_mask(void) 944 { 945 unsigned int possible, sclp_max, cpu; 946 947 sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1; 948 sclp_max = min(smp_max_threads, sclp_max); 949 sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids; 950 possible = setup_possible_cpus ?: nr_cpu_ids; 951 possible = min(possible, sclp_max); 952 for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++) 953 set_cpu_possible(cpu, true); 954 } 955 956 void __init smp_prepare_cpus(unsigned int max_cpus) 957 { 958 if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt)) 959 panic("Couldn't request external interrupt 0x1201"); 960 system_ctl_set_bit(0, 14); 961 if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt)) 962 panic("Couldn't request external interrupt 0x1202"); 963 system_ctl_set_bit(0, 13); 964 smp_rescan_cpus(true); 965 } 966 967 void __init smp_prepare_boot_cpu(void) 968 { 969 struct lowcore *lc = get_lowcore(); 970 971 WARN_ON(!cpu_present(0) || !cpu_online(0)); 972 lc->percpu_offset = __per_cpu_offset[0]; 973 ipl_pcpu = per_cpu_ptr(&pcpu_devices, 0); 974 ipl_pcpu->state = CPU_STATE_CONFIGURED; 975 lc->pcpu = (unsigned long)ipl_pcpu; 976 smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN); 977 smp_cpu_set_capacity(0, CPU_CAPACITY_HIGH); 978 } 979 980 void __init smp_setup_processor_id(void) 981 { 982 struct lowcore *lc = get_lowcore(); 983 984 lc->cpu_nr = 0; 985 per_cpu(pcpu_devices, 0).address = stap(); 986 lc->spinlock_lockval = arch_spin_lockval(0); 987 lc->spinlock_index = 0; 988 } 989 990 /* 991 * the frequency of the profiling timer can be changed 992 * by writing a multiplier value into /proc/profile. 993 * 994 * usually you want to run this on all CPUs ;) 995 */ 996 int setup_profiling_timer(unsigned int multiplier) 997 { 998 return 0; 999 } 1000 1001 static ssize_t cpu_configure_show(struct device *dev, 1002 struct device_attribute *attr, char *buf) 1003 { 1004 ssize_t count; 1005 1006 mutex_lock(&smp_cpu_state_mutex); 1007 count = sysfs_emit(buf, "%d\n", per_cpu(pcpu_devices, dev->id).state); 1008 mutex_unlock(&smp_cpu_state_mutex); 1009 return count; 1010 } 1011 1012 static ssize_t cpu_configure_store(struct device *dev, 1013 struct device_attribute *attr, 1014 const char *buf, size_t count) 1015 { 1016 struct pcpu *pcpu; 1017 int cpu, val, rc, i; 1018 char delim; 1019 1020 if (sscanf(buf, "%d %c", &val, &delim) != 1) 1021 return -EINVAL; 1022 if (val != 0 && val != 1) 1023 return -EINVAL; 1024 cpus_read_lock(); 1025 mutex_lock(&smp_cpu_state_mutex); 1026 rc = -EBUSY; 1027 /* disallow configuration changes of online cpus */ 1028 cpu = dev->id; 1029 cpu = smp_get_base_cpu(cpu); 1030 for (i = 0; i <= smp_cpu_mtid; i++) 1031 if (cpu_online(cpu + i)) 1032 goto out; 1033 pcpu = per_cpu_ptr(&pcpu_devices, cpu); 1034 rc = 0; 1035 switch (val) { 1036 case 0: 1037 if (pcpu->state != CPU_STATE_CONFIGURED) 1038 break; 1039 rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift); 1040 if (rc) 1041 break; 1042 for (i = 0; i <= smp_cpu_mtid; i++) { 1043 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) 1044 continue; 1045 per_cpu(pcpu_devices, cpu + i).state = CPU_STATE_STANDBY; 1046 smp_cpu_set_polarization(cpu + i, 1047 POLARIZATION_UNKNOWN); 1048 } 1049 topology_expect_change(); 1050 break; 1051 case 1: 1052 if (pcpu->state != CPU_STATE_STANDBY) 1053 break; 1054 rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift); 1055 if (rc) 1056 break; 1057 for (i = 0; i <= smp_cpu_mtid; i++) { 1058 if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i)) 1059 continue; 1060 per_cpu(pcpu_devices, cpu + i).state = CPU_STATE_CONFIGURED; 1061 smp_cpu_set_polarization(cpu + i, 1062 POLARIZATION_UNKNOWN); 1063 } 1064 topology_expect_change(); 1065 break; 1066 default: 1067 break; 1068 } 1069 out: 1070 mutex_unlock(&smp_cpu_state_mutex); 1071 cpus_read_unlock(); 1072 return rc ? rc : count; 1073 } 1074 static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store); 1075 1076 static ssize_t show_cpu_address(struct device *dev, 1077 struct device_attribute *attr, char *buf) 1078 { 1079 return sysfs_emit(buf, "%d\n", per_cpu(pcpu_devices, dev->id).address); 1080 } 1081 static DEVICE_ATTR(address, 0444, show_cpu_address, NULL); 1082 1083 static struct attribute *cpu_common_attrs[] = { 1084 &dev_attr_configure.attr, 1085 &dev_attr_address.attr, 1086 NULL, 1087 }; 1088 1089 static struct attribute_group cpu_common_attr_group = { 1090 .attrs = cpu_common_attrs, 1091 }; 1092 1093 static struct attribute *cpu_online_attrs[] = { 1094 &dev_attr_idle_count.attr, 1095 &dev_attr_idle_time_us.attr, 1096 NULL, 1097 }; 1098 1099 static struct attribute_group cpu_online_attr_group = { 1100 .attrs = cpu_online_attrs, 1101 }; 1102 1103 static int smp_cpu_online(unsigned int cpu) 1104 { 1105 struct cpu *c = per_cpu_ptr(&cpu_devices, cpu); 1106 1107 return sysfs_create_group(&c->dev.kobj, &cpu_online_attr_group); 1108 } 1109 1110 static int smp_cpu_pre_down(unsigned int cpu) 1111 { 1112 struct cpu *c = per_cpu_ptr(&cpu_devices, cpu); 1113 1114 sysfs_remove_group(&c->dev.kobj, &cpu_online_attr_group); 1115 return 0; 1116 } 1117 1118 bool arch_cpu_is_hotpluggable(int cpu) 1119 { 1120 return !!cpu; 1121 } 1122 1123 int arch_register_cpu(int cpu) 1124 { 1125 struct cpu *c = per_cpu_ptr(&cpu_devices, cpu); 1126 int rc; 1127 1128 c->hotpluggable = arch_cpu_is_hotpluggable(cpu); 1129 rc = register_cpu(c, cpu); 1130 if (rc) 1131 goto out; 1132 rc = sysfs_create_group(&c->dev.kobj, &cpu_common_attr_group); 1133 if (rc) 1134 goto out_cpu; 1135 rc = topology_cpu_init(c); 1136 if (rc) 1137 goto out_topology; 1138 return 0; 1139 1140 out_topology: 1141 sysfs_remove_group(&c->dev.kobj, &cpu_common_attr_group); 1142 out_cpu: 1143 unregister_cpu(c); 1144 out: 1145 return rc; 1146 } 1147 1148 int __ref smp_rescan_cpus(bool early) 1149 { 1150 struct sclp_core_info *info; 1151 int nr; 1152 1153 info = kzalloc(sizeof(*info), GFP_KERNEL); 1154 if (!info) 1155 return -ENOMEM; 1156 smp_get_core_info(info, 0); 1157 nr = __smp_rescan_cpus(info, early); 1158 kfree(info); 1159 if (nr) 1160 topology_schedule_update(); 1161 return 0; 1162 } 1163 1164 static ssize_t __ref rescan_store(struct device *dev, 1165 struct device_attribute *attr, 1166 const char *buf, 1167 size_t count) 1168 { 1169 int rc; 1170 1171 rc = lock_device_hotplug_sysfs(); 1172 if (rc) 1173 return rc; 1174 rc = smp_rescan_cpus(false); 1175 unlock_device_hotplug(); 1176 return rc ? rc : count; 1177 } 1178 static DEVICE_ATTR_WO(rescan); 1179 1180 static int __init s390_smp_init(void) 1181 { 1182 struct device *dev_root; 1183 int rc; 1184 1185 dev_root = bus_get_dev_root(&cpu_subsys); 1186 if (dev_root) { 1187 rc = device_create_file(dev_root, &dev_attr_rescan); 1188 put_device(dev_root); 1189 if (rc) 1190 return rc; 1191 } 1192 rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online", 1193 smp_cpu_online, smp_cpu_pre_down); 1194 rc = rc <= 0 ? rc : 0; 1195 return rc; 1196 } 1197 subsys_initcall(s390_smp_init); 1198