1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2024 DeepComputing (HK) Limited 4 */ 5 6/dts-v1/; 7#include "jh7110-common.dtsi" 8 9/ { 10 model = "DeepComputing FML13V01"; 11 compatible = "deepcomputing,fml13v01", "starfive,jh7110"; 12}; 13 14&pcie1 { 15 perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>; 16 phys = <&pciephy1>; 17 pinctrl-names = "default"; 18 pinctrl-0 = <&pcie1_pins>; 19 status = "okay"; 20}; 21 22&sysgpio { 23 pcie1_pins: pcie1-0 { 24 clkreq-pins { 25 pinmux = <GPIOMUX(29, GPOUT_LOW, 26 GPOEN_DISABLE, 27 GPI_NONE)>; 28 bias-pull-down; 29 drive-strength = <2>; 30 input-enable; 31 input-schmitt-disable; 32 slew-rate = <0>; 33 }; 34 35 wake-pins { 36 pinmux = <GPIOMUX(28, GPOUT_HIGH, 37 GPOEN_DISABLE, 38 GPI_NONE)>; 39 bias-pull-up; 40 drive-strength = <2>; 41 input-enable; 42 input-schmitt-disable; 43 slew-rate = <0>; 44 }; 45 }; 46 47 usb0_pins: usb0-0 { 48 vbus-pins { 49 pinmux = <GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, 50 GPOEN_ENABLE, 51 GPI_NONE)>; 52 bias-disable; 53 input-disable; 54 input-schmitt-disable; 55 slew-rate = <0>; 56 }; 57 }; 58}; 59 60&usb0 { 61 dr_mode = "host"; 62 pinctrl-names = "default"; 63 pinctrl-0 = <&usb0_pins>; 64 status = "okay"; 65}; 66 67&usb_cdns3 { 68 phys = <&usbphy0>, <&pciephy0>; 69 phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy"; 70}; 71