1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name> 4 */ 5 6#include <dt-bindings/clock/spacemit,k1-syscon.h> 7 8/dts-v1/; 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 model = "SpacemiT K1"; 13 compatible = "spacemit,k1"; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 timebase-frequency = <24000000>; 19 20 cpu-map { 21 cluster0 { 22 core0 { 23 cpu = <&cpu_0>; 24 }; 25 core1 { 26 cpu = <&cpu_1>; 27 }; 28 core2 { 29 cpu = <&cpu_2>; 30 }; 31 core3 { 32 cpu = <&cpu_3>; 33 }; 34 }; 35 36 cluster1 { 37 core0 { 38 cpu = <&cpu_4>; 39 }; 40 core1 { 41 cpu = <&cpu_5>; 42 }; 43 core2 { 44 cpu = <&cpu_6>; 45 }; 46 core3 { 47 cpu = <&cpu_7>; 48 }; 49 }; 50 }; 51 52 cpu_0: cpu@0 { 53 compatible = "spacemit,x60", "riscv"; 54 device_type = "cpu"; 55 reg = <0>; 56 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 57 riscv,isa-base = "rv64i"; 58 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 59 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 60 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 61 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 62 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 63 riscv,cbom-block-size = <64>; 64 riscv,cbop-block-size = <64>; 65 riscv,cboz-block-size = <64>; 66 i-cache-block-size = <64>; 67 i-cache-size = <32768>; 68 i-cache-sets = <128>; 69 d-cache-block-size = <64>; 70 d-cache-size = <32768>; 71 d-cache-sets = <128>; 72 next-level-cache = <&cluster0_l2_cache>; 73 mmu-type = "riscv,sv39"; 74 75 cpu0_intc: interrupt-controller { 76 compatible = "riscv,cpu-intc"; 77 interrupt-controller; 78 #interrupt-cells = <1>; 79 }; 80 }; 81 82 cpu_1: cpu@1 { 83 compatible = "spacemit,x60", "riscv"; 84 device_type = "cpu"; 85 reg = <1>; 86 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 87 riscv,isa-base = "rv64i"; 88 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 89 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 90 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 91 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 92 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 93 riscv,cbom-block-size = <64>; 94 riscv,cbop-block-size = <64>; 95 riscv,cboz-block-size = <64>; 96 i-cache-block-size = <64>; 97 i-cache-size = <32768>; 98 i-cache-sets = <128>; 99 d-cache-block-size = <64>; 100 d-cache-size = <32768>; 101 d-cache-sets = <128>; 102 next-level-cache = <&cluster0_l2_cache>; 103 mmu-type = "riscv,sv39"; 104 105 cpu1_intc: interrupt-controller { 106 compatible = "riscv,cpu-intc"; 107 interrupt-controller; 108 #interrupt-cells = <1>; 109 }; 110 }; 111 112 cpu_2: cpu@2 { 113 compatible = "spacemit,x60", "riscv"; 114 device_type = "cpu"; 115 reg = <2>; 116 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 117 riscv,isa-base = "rv64i"; 118 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 119 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 120 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 121 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 122 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 123 riscv,cbom-block-size = <64>; 124 riscv,cbop-block-size = <64>; 125 riscv,cboz-block-size = <64>; 126 i-cache-block-size = <64>; 127 i-cache-size = <32768>; 128 i-cache-sets = <128>; 129 d-cache-block-size = <64>; 130 d-cache-size = <32768>; 131 d-cache-sets = <128>; 132 next-level-cache = <&cluster0_l2_cache>; 133 mmu-type = "riscv,sv39"; 134 135 cpu2_intc: interrupt-controller { 136 compatible = "riscv,cpu-intc"; 137 interrupt-controller; 138 #interrupt-cells = <1>; 139 }; 140 }; 141 142 cpu_3: cpu@3 { 143 compatible = "spacemit,x60", "riscv"; 144 device_type = "cpu"; 145 reg = <3>; 146 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 147 riscv,isa-base = "rv64i"; 148 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 149 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 150 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 151 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 152 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 153 riscv,cbom-block-size = <64>; 154 riscv,cbop-block-size = <64>; 155 riscv,cboz-block-size = <64>; 156 i-cache-block-size = <64>; 157 i-cache-size = <32768>; 158 i-cache-sets = <128>; 159 d-cache-block-size = <64>; 160 d-cache-size = <32768>; 161 d-cache-sets = <128>; 162 next-level-cache = <&cluster0_l2_cache>; 163 mmu-type = "riscv,sv39"; 164 165 cpu3_intc: interrupt-controller { 166 compatible = "riscv,cpu-intc"; 167 interrupt-controller; 168 #interrupt-cells = <1>; 169 }; 170 }; 171 172 cpu_4: cpu@4 { 173 compatible = "spacemit,x60", "riscv"; 174 device_type = "cpu"; 175 reg = <4>; 176 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 177 riscv,isa-base = "rv64i"; 178 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 179 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 180 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 181 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 182 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 183 riscv,cbom-block-size = <64>; 184 riscv,cbop-block-size = <64>; 185 riscv,cboz-block-size = <64>; 186 i-cache-block-size = <64>; 187 i-cache-size = <32768>; 188 i-cache-sets = <128>; 189 d-cache-block-size = <64>; 190 d-cache-size = <32768>; 191 d-cache-sets = <128>; 192 next-level-cache = <&cluster1_l2_cache>; 193 mmu-type = "riscv,sv39"; 194 195 cpu4_intc: interrupt-controller { 196 compatible = "riscv,cpu-intc"; 197 interrupt-controller; 198 #interrupt-cells = <1>; 199 }; 200 }; 201 202 cpu_5: cpu@5 { 203 compatible = "spacemit,x60", "riscv"; 204 device_type = "cpu"; 205 reg = <5>; 206 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 207 riscv,isa-base = "rv64i"; 208 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 209 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 210 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 211 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 212 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 213 riscv,cbom-block-size = <64>; 214 riscv,cbop-block-size = <64>; 215 riscv,cboz-block-size = <64>; 216 i-cache-block-size = <64>; 217 i-cache-size = <32768>; 218 i-cache-sets = <128>; 219 d-cache-block-size = <64>; 220 d-cache-size = <32768>; 221 d-cache-sets = <128>; 222 next-level-cache = <&cluster1_l2_cache>; 223 mmu-type = "riscv,sv39"; 224 225 cpu5_intc: interrupt-controller { 226 compatible = "riscv,cpu-intc"; 227 interrupt-controller; 228 #interrupt-cells = <1>; 229 }; 230 }; 231 232 cpu_6: cpu@6 { 233 compatible = "spacemit,x60", "riscv"; 234 device_type = "cpu"; 235 reg = <6>; 236 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 237 riscv,isa-base = "rv64i"; 238 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 239 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 240 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 241 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 242 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 243 riscv,cbom-block-size = <64>; 244 riscv,cbop-block-size = <64>; 245 riscv,cboz-block-size = <64>; 246 i-cache-block-size = <64>; 247 i-cache-size = <32768>; 248 i-cache-sets = <128>; 249 d-cache-block-size = <64>; 250 d-cache-size = <32768>; 251 d-cache-sets = <128>; 252 next-level-cache = <&cluster1_l2_cache>; 253 mmu-type = "riscv,sv39"; 254 255 cpu6_intc: interrupt-controller { 256 compatible = "riscv,cpu-intc"; 257 interrupt-controller; 258 #interrupt-cells = <1>; 259 }; 260 }; 261 262 cpu_7: cpu@7 { 263 compatible = "spacemit,x60", "riscv"; 264 device_type = "cpu"; 265 reg = <7>; 266 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 267 riscv,isa-base = "rv64i"; 268 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 269 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 270 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 271 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 272 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 273 riscv,cbom-block-size = <64>; 274 riscv,cbop-block-size = <64>; 275 riscv,cboz-block-size = <64>; 276 i-cache-block-size = <64>; 277 i-cache-size = <32768>; 278 i-cache-sets = <128>; 279 d-cache-block-size = <64>; 280 d-cache-size = <32768>; 281 d-cache-sets = <128>; 282 next-level-cache = <&cluster1_l2_cache>; 283 mmu-type = "riscv,sv39"; 284 285 cpu7_intc: interrupt-controller { 286 compatible = "riscv,cpu-intc"; 287 interrupt-controller; 288 #interrupt-cells = <1>; 289 }; 290 }; 291 292 cluster0_l2_cache: l2-cache0 { 293 compatible = "cache"; 294 cache-block-size = <64>; 295 cache-level = <2>; 296 cache-size = <524288>; 297 cache-sets = <512>; 298 cache-unified; 299 }; 300 301 cluster1_l2_cache: l2-cache1 { 302 compatible = "cache"; 303 cache-block-size = <64>; 304 cache-level = <2>; 305 cache-size = <524288>; 306 cache-sets = <512>; 307 cache-unified; 308 }; 309 }; 310 311 clocks { 312 vctcxo_1m: clock-1m { 313 compatible = "fixed-clock"; 314 clock-frequency = <1000000>; 315 clock-output-names = "vctcxo_1m"; 316 #clock-cells = <0>; 317 }; 318 319 vctcxo_24m: clock-24m { 320 compatible = "fixed-clock"; 321 clock-frequency = <24000000>; 322 clock-output-names = "vctcxo_24m"; 323 #clock-cells = <0>; 324 }; 325 326 vctcxo_3m: clock-3m { 327 compatible = "fixed-clock"; 328 clock-frequency = <3000000>; 329 clock-output-names = "vctcxo_3m"; 330 #clock-cells = <0>; 331 }; 332 333 osc_32k: clock-32k { 334 compatible = "fixed-clock"; 335 clock-frequency = <32000>; 336 clock-output-names = "osc_32k"; 337 #clock-cells = <0>; 338 }; 339 }; 340 341 soc { 342 compatible = "simple-bus"; 343 interrupt-parent = <&plic>; 344 #address-cells = <2>; 345 #size-cells = <2>; 346 dma-noncoherent; 347 ranges; 348 349 syscon_apbc: system-controller@d4015000 { 350 compatible = "spacemit,k1-syscon-apbc"; 351 reg = <0x0 0xd4015000 0x0 0x1000>; 352 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, 353 <&vctcxo_24m>; 354 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", 355 "vctcxo_24m"; 356 #clock-cells = <1>; 357 #reset-cells = <1>; 358 }; 359 360 uart0: serial@d4017000 { 361 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 362 reg = <0x0 0xd4017000 0x0 0x100>; 363 clocks = <&syscon_apbc CLK_UART0>, 364 <&syscon_apbc CLK_UART0_BUS>; 365 clock-names = "core", "bus"; 366 interrupts = <42>; 367 reg-shift = <2>; 368 reg-io-width = <4>; 369 status = "disabled"; 370 }; 371 372 uart2: serial@d4017100 { 373 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 374 reg = <0x0 0xd4017100 0x0 0x100>; 375 clocks = <&syscon_apbc CLK_UART2>, 376 <&syscon_apbc CLK_UART2_BUS>; 377 clock-names = "core", "bus"; 378 interrupts = <44>; 379 reg-shift = <2>; 380 reg-io-width = <4>; 381 status = "disabled"; 382 }; 383 384 uart3: serial@d4017200 { 385 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 386 reg = <0x0 0xd4017200 0x0 0x100>; 387 clocks = <&syscon_apbc CLK_UART3>, 388 <&syscon_apbc CLK_UART3_BUS>; 389 clock-names = "core", "bus"; 390 interrupts = <45>; 391 reg-shift = <2>; 392 reg-io-width = <4>; 393 status = "disabled"; 394 }; 395 396 uart4: serial@d4017300 { 397 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 398 reg = <0x0 0xd4017300 0x0 0x100>; 399 clocks = <&syscon_apbc CLK_UART4>, 400 <&syscon_apbc CLK_UART4_BUS>; 401 clock-names = "core", "bus"; 402 interrupts = <46>; 403 reg-shift = <2>; 404 reg-io-width = <4>; 405 status = "disabled"; 406 }; 407 408 uart5: serial@d4017400 { 409 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 410 reg = <0x0 0xd4017400 0x0 0x100>; 411 clocks = <&syscon_apbc CLK_UART5>, 412 <&syscon_apbc CLK_UART5_BUS>; 413 clock-names = "core", "bus"; 414 interrupts = <47>; 415 reg-shift = <2>; 416 reg-io-width = <4>; 417 status = "disabled"; 418 }; 419 420 uart6: serial@d4017500 { 421 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 422 reg = <0x0 0xd4017500 0x0 0x100>; 423 clocks = <&syscon_apbc CLK_UART6>, 424 <&syscon_apbc CLK_UART6_BUS>; 425 clock-names = "core", "bus"; 426 interrupts = <48>; 427 reg-shift = <2>; 428 reg-io-width = <4>; 429 status = "disabled"; 430 }; 431 432 uart7: serial@d4017600 { 433 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 434 reg = <0x0 0xd4017600 0x0 0x100>; 435 clocks = <&syscon_apbc CLK_UART7>, 436 <&syscon_apbc CLK_UART7_BUS>; 437 clock-names = "core", "bus"; 438 interrupts = <49>; 439 reg-shift = <2>; 440 reg-io-width = <4>; 441 status = "disabled"; 442 }; 443 444 uart8: serial@d4017700 { 445 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 446 reg = <0x0 0xd4017700 0x0 0x100>; 447 clocks = <&syscon_apbc CLK_UART8>, 448 <&syscon_apbc CLK_UART8_BUS>; 449 clock-names = "core", "bus"; 450 interrupts = <50>; 451 reg-shift = <2>; 452 reg-io-width = <4>; 453 status = "disabled"; 454 }; 455 456 uart9: serial@d4017800 { 457 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 458 reg = <0x0 0xd4017800 0x0 0x100>; 459 clocks = <&syscon_apbc CLK_UART9>, 460 <&syscon_apbc CLK_UART9_BUS>; 461 clock-names = "core", "bus"; 462 interrupts = <51>; 463 reg-shift = <2>; 464 reg-io-width = <4>; 465 status = "disabled"; 466 }; 467 468 gpio: gpio@d4019000 { 469 compatible = "spacemit,k1-gpio"; 470 reg = <0x0 0xd4019000 0x0 0x100>; 471 clocks = <&syscon_apbc CLK_GPIO>, 472 <&syscon_apbc CLK_GPIO_BUS>; 473 clock-names = "core", "bus"; 474 gpio-controller; 475 #gpio-cells = <3>; 476 interrupts = <58>; 477 interrupt-parent = <&plic>; 478 interrupt-controller; 479 #interrupt-cells = <3>; 480 gpio-ranges = <&pinctrl 0 0 0 32>, 481 <&pinctrl 1 0 32 32>, 482 <&pinctrl 2 0 64 32>, 483 <&pinctrl 3 0 96 32>; 484 }; 485 486 pinctrl: pinctrl@d401e000 { 487 compatible = "spacemit,k1-pinctrl"; 488 reg = <0x0 0xd401e000 0x0 0x400>; 489 clocks = <&syscon_apbc CLK_AIB>, 490 <&syscon_apbc CLK_AIB_BUS>; 491 clock-names = "func", "bus"; 492 }; 493 494 syscon_mpmu: system-controller@d4050000 { 495 compatible = "spacemit,k1-syscon-mpmu"; 496 reg = <0x0 0xd4050000 0x0 0x209c>; 497 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, 498 <&vctcxo_24m>; 499 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", 500 "vctcxo_24m"; 501 #clock-cells = <1>; 502 #power-domain-cells = <1>; 503 #reset-cells = <1>; 504 }; 505 506 pll: clock-controller@d4090000 { 507 compatible = "spacemit,k1-pll"; 508 reg = <0x0 0xd4090000 0x0 0x1000>; 509 clocks = <&vctcxo_24m>; 510 spacemit,mpmu = <&syscon_mpmu>; 511 #clock-cells = <1>; 512 }; 513 514 syscon_apmu: system-controller@d4282800 { 515 compatible = "spacemit,k1-syscon-apmu"; 516 reg = <0x0 0xd4282800 0x0 0x400>; 517 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, 518 <&vctcxo_24m>; 519 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", 520 "vctcxo_24m"; 521 #clock-cells = <1>; 522 #power-domain-cells = <1>; 523 #reset-cells = <1>; 524 }; 525 526 plic: interrupt-controller@e0000000 { 527 compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; 528 reg = <0x0 0xe0000000 0x0 0x4000000>; 529 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 530 <&cpu1_intc 11>, <&cpu1_intc 9>, 531 <&cpu2_intc 11>, <&cpu2_intc 9>, 532 <&cpu3_intc 11>, <&cpu3_intc 9>, 533 <&cpu4_intc 11>, <&cpu4_intc 9>, 534 <&cpu5_intc 11>, <&cpu5_intc 9>, 535 <&cpu6_intc 11>, <&cpu6_intc 9>, 536 <&cpu7_intc 11>, <&cpu7_intc 9>; 537 interrupt-controller; 538 #address-cells = <0>; 539 #interrupt-cells = <1>; 540 riscv,ndev = <159>; 541 }; 542 543 clint: timer@e4000000 { 544 compatible = "spacemit,k1-clint", "sifive,clint0"; 545 reg = <0x0 0xe4000000 0x0 0x10000>; 546 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 547 <&cpu1_intc 3>, <&cpu1_intc 7>, 548 <&cpu2_intc 3>, <&cpu2_intc 7>, 549 <&cpu3_intc 3>, <&cpu3_intc 7>, 550 <&cpu4_intc 3>, <&cpu4_intc 7>, 551 <&cpu5_intc 3>, <&cpu5_intc 7>, 552 <&cpu6_intc 3>, <&cpu6_intc 7>, 553 <&cpu7_intc 3>, <&cpu7_intc 7>; 554 }; 555 556 sec_uart1: serial@f0612000 { 557 compatible = "spacemit,k1-uart", "intel,xscale-uart"; 558 reg = <0x0 0xf0612000 0x0 0x100>; 559 interrupts = <43>; 560 clock-frequency = <14857000>; 561 reg-shift = <2>; 562 reg-io-width = <4>; 563 status = "reserved"; /* for TEE usage */ 564 }; 565 }; 566}; 567