16f4eea90SVincent Chenmenu "CPU errata selection" 26f4eea90SVincent Chen 3e021ae7fSLad Prabhakarconfig ERRATA_ANDES 4e021ae7fSLad Prabhakar bool "Andes AX45MP errata" 52f73b35dSLad Prabhakar depends on RISCV_ALTERNATIVE && RISCV_SBI 6e021ae7fSLad Prabhakar help 7e021ae7fSLad Prabhakar All Andes errata Kconfig depend on this Kconfig. Disabling 8e021ae7fSLad Prabhakar this Kconfig will disable all Andes errata. Please say "Y" 9e021ae7fSLad Prabhakar here if your platform uses Andes CPU cores. 10e021ae7fSLad Prabhakar 11e021ae7fSLad Prabhakar Otherwise, please say "N" here to avoid unnecessary overhead. 12e021ae7fSLad Prabhakar 13e021ae7fSLad Prabhakarconfig ERRATA_ANDES_CMO 14e021ae7fSLad Prabhakar bool "Apply Andes cache management errata" 1554adc24cSLad Prabhakar depends on ERRATA_ANDES && ARCH_R9A07G043 16e021ae7fSLad Prabhakar select RISCV_DMA_NONCOHERENT 17e021ae7fSLad Prabhakar default y 18e021ae7fSLad Prabhakar help 19e021ae7fSLad Prabhakar This will apply the cache management errata to handle the 20e021ae7fSLad Prabhakar non-standard handling on non-coherent operations on Andes cores. 21e021ae7fSLad Prabhakar 22e021ae7fSLad Prabhakar If you don't know what to do here, say "Y". 23e021ae7fSLad Prabhakar 241a0e5dbdSVincent Chenconfig ERRATA_MIPS 251a0e5dbdSVincent Chen bool "MIPS errata" 261ee7fc3fSConor Dooley depends on RISCV_ALTERNATIVE 271a0e5dbdSVincent Chen help 281a0e5dbdSVincent Chen All MIPS errata Kconfig depend on this Kconfig. Disabling 291a0e5dbdSVincent Chen this Kconfig will disable all MIPS errata. Please say "Y" 301a0e5dbdSVincent Chen here if your platform uses MIPS CPU cores. 311a0e5dbdSVincent Chen 321a0e5dbdSVincent Chen Otherwise, please say "N" here to avoid unnecessary overhead. 331a0e5dbdSVincent Chen 34800149a7SVincent Chenconfig ERRATA_MIPS_P8700_PAUSE_OPCODE 35800149a7SVincent Chen bool "Fix the PAUSE Opcode for MIPS P8700" 360e0d4992SVincent Chen depends on ERRATA_MIPS && 64BIT 37800149a7SVincent Chen default n 38800149a7SVincent Chen help 39800149a7SVincent Chen The RISCV MIPS P8700 uses a different opcode for PAUSE. 40800149a7SVincent Chen It is a 'hint' encoding of the SLLI instruction, 41800149a7SVincent Chen with rd=0, rs1=0 and imm=5. It will behave as a NOP 42800149a7SVincent Chen instruction if no additional behavior beyond that of 43800149a7SVincent Chen SLLI is implemented. 44800149a7SVincent Chen 45bff3ff52SVincent Chen If you are not using the P8700 processor, say n. 46bff3ff52SVincent Chen 470e0d4992SVincent Chenconfig ERRATA_SIFIVE 48bff3ff52SVincent Chen bool "SiFive errata" 49bff3ff52SVincent Chen depends on RISCV_ALTERNATIVE 50bff3ff52SVincent Chen help 51bff3ff52SVincent Chen All SiFive errata Kconfig depend on this Kconfig. Disabling 52bff3ff52SVincent Chen this Kconfig will disable all SiFive errata. Please say "Y" 53bff3ff52SVincent Chen here if your platform uses SiFive CPU cores. 54bff3ff52SVincent Chen 55bff3ff52SVincent Chen Otherwise, please say "N" here to avoid unnecessary overhead. 5664fc984aSEmil Renner Berthing 5764fc984aSEmil Renner Berthingconfig ERRATA_SIFIVE_CIP_453 589a9e8d8dSEmil Renner Berthing bool "Apply SiFive errata CIP-453" 599a9e8d8dSEmil Renner Berthing depends on ERRATA_SIFIVE && 64BIT 609a9e8d8dSEmil Renner Berthing default y 6164fc984aSEmil Renner Berthing help 6264fc984aSEmil Renner Berthing This will apply the SiFive CIP-453 errata to add sign extension 6364fc984aSEmil Renner Berthing to the $badaddr when exception type is instruction page fault 6464fc984aSEmil Renner Berthing and instruction access fault. 6564fc984aSEmil Renner Berthing 6664fc984aSEmil Renner Berthing If you don't know what to do here, say "Y". 6764fc984aSEmil Renner Berthing 6864fc984aSEmil Renner Berthingconfig ERRATA_SIFIVE_CIP_1200 6964fc984aSEmil Renner Berthing bool "Apply SiFive errata CIP-1200" 7064fc984aSEmil Renner Berthing depends on ERRATA_SIFIVE && 64BIT 7164fc984aSEmil Renner Berthing default y 7264fc984aSEmil Renner Berthing help 7364fc984aSEmil Renner Berthing This will apply the SiFive CIP-1200 errata to repalce all 7464fc984aSEmil Renner Berthing "sfence.vma addr" with "sfence.vma" to ensure that the addr 75a35707c3SHeiko Stuebner has been flushed from TLB. 76a35707c3SHeiko Stuebner 771ee7fc3fSConor Dooley If you don't know what to do here, say "Y". 78a35707c3SHeiko Stuebner 79a35707c3SHeiko Stuebnerconfig ERRATA_STARFIVE_JH7100 80a35707c3SHeiko Stuebner bool "StarFive JH7100 support" 81a35707c3SHeiko Stuebner depends on ARCH_STARFIVE 82a35707c3SHeiko Stuebner depends on !DMA_DIRECT_REMAP 83a35707c3SHeiko Stuebner depends on NONPORTABLE 84a35707c3SHeiko Stuebner select DMA_GLOBAL_POOL 85a35707c3SHeiko Stuebner select RISCV_DMA_NONCOHERENT 86a35707c3SHeiko Stuebner select RISCV_NONSTANDARD_CACHE_OPS 872a2018c3SHeiko Stuebner select SIFIVE_CCACHE 88a35707c3SHeiko Stuebner default n 89a35707c3SHeiko Stuebner help 90a35707c3SHeiko Stuebner The StarFive JH7100 was a test chip for the JH7110 and has 91a35707c3SHeiko Stuebner caches that are non-coherent with respect to peripheral DMAs. 92a35707c3SHeiko Stuebner It was designed before the Zicbom extension so needs non-standard 93a35707c3SHeiko Stuebner cache operations through the SiFive cache controller. 94a35707c3SHeiko Stuebner 95a35707c3SHeiko Stuebner Say "Y" if you want to support the BeagleV Starlight and/or 96d20ec752SHeiko Stuebner StarFive VisionFive V1 boards. 97d20ec752SHeiko Stuebner 982a2018c3SHeiko Stuebnerconfig ERRATA_THEAD 99381cae16SChristoph Hellwig bool "T-HEAD errata" 100d20ec752SHeiko Stuebner depends on RISCV_ALTERNATIVE 101*a4ff64edSJisheng Zhang help 102d20ec752SHeiko Stuebner All T-HEAD errata Kconfig depend on this Kconfig. Disabling 103d20ec752SHeiko Stuebner this Kconfig will disable all T-HEAD errata. Please say "Y" 104d20ec752SHeiko Stuebner here if your platform uses T-HEAD CPU cores. 105d20ec752SHeiko Stuebner 106d20ec752SHeiko Stuebner Otherwise, please say "N" here to avoid unnecessary overhead. 107d20ec752SHeiko Stuebner 108d20ec752SHeiko Stuebnerconfig ERRATA_THEAD_MAE 10965e9fb08SHeiko Stuebner bool "Apply T-Head's memory attribute extension (XTheadMae) errata" 11065e9fb08SHeiko Stuebner depends on ERRATA_THEAD && 64BIT && MMU 11165e9fb08SHeiko Stuebner select RISCV_ALTERNATIVE_EARLY 11265e9fb08SHeiko Stuebner default y 11365e9fb08SHeiko Stuebner help 11465e9fb08SHeiko Stuebner This will apply the memory attribute extension errata to handle the 11565e9fb08SHeiko Stuebner non-standard PTE utilization on T-Head SoCs (XTheadMae). 11665e9fb08SHeiko Stuebner 11765e9fb08SHeiko Stuebner If you don't know what to do here, say "Y". 11865e9fb08SHeiko Stuebner 11965e9fb08SHeiko Stuebnerconfig ERRATA_THEAD_CMO 12065e9fb08SHeiko Stuebner bool "Apply T-Head cache management errata" 12165e9fb08SHeiko Stuebner depends on ERRATA_THEAD && MMU 12284b10f78SJuerg Haefliger select DMA_DIRECT_REMAP 123 select RISCV_DMA_NONCOHERENT 124 select RISCV_NONSTANDARD_CACHE_OPS 125 default y 126 help 127 This will apply the cache management errata to handle the 128 non-standard handling on non-coherent operations on T-Head SoCs. 129 130 If you don't know what to do here, say "Y". 131 132config ERRATA_THEAD_PMU 133 bool "Apply T-Head PMU errata" 134 depends on ERRATA_THEAD && RISCV_PMU_SBI 135 default y 136 help 137 The T-Head C9xx cores implement a PMU overflow extension very 138 similar to the core SSCOFPMF extension. 139 140 This will apply the overflow errata to handle the non-standard 141 behaviour via the regular SBI PMU driver and interface. 142 143 If you don't know what to do here, say "Y". 144 145config ERRATA_THEAD_GHOSTWRITE 146 bool "Apply T-Head Ghostwrite errata" 147 depends on ERRATA_THEAD && RISCV_ISA_XTHEADVECTOR 148 default y 149 help 150 The T-Head C9xx cores have a vulnerability in the xtheadvector 151 instruction set. When this errata is enabled, the CPUs will be probed 152 to determine if they are vulnerable and disable xtheadvector. 153 154 If you don't know what to do here, say "Y". 155 156endmenu # "CPU errata selection" 157