1/* 2 * This file contains miscellaneous low-level functions. 3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 4 * 5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) 6 * and Paul Mackerras. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 * 13 */ 14 15#include <linux/config.h> 16#include <linux/sys.h> 17#include <asm/unistd.h> 18#include <asm/errno.h> 19#include <asm/reg.h> 20#include <asm/page.h> 21#include <asm/cache.h> 22#include <asm/cputable.h> 23#include <asm/mmu.h> 24#include <asm/ppc_asm.h> 25#include <asm/thread_info.h> 26#include <asm/asm-offsets.h> 27 28 .text 29 30 .align 5 31_GLOBAL(__delay) 32 cmpwi 0,r3,0 33 mtctr r3 34 beqlr 351: bdnz 1b 36 blr 37 38/* 39 * Returns (address we're running at) - (address we were linked at) 40 * for use before the text and data are mapped to KERNELBASE. 41 */ 42_GLOBAL(reloc_offset) 43 mflr r0 44 bl 1f 451: mflr r3 46 LOADADDR(r4,1b) 47 subf r3,r4,r3 48 mtlr r0 49 blr 50 51/* 52 * add_reloc_offset(x) returns x + reloc_offset(). 53 */ 54_GLOBAL(add_reloc_offset) 55 mflr r0 56 bl 1f 571: mflr r5 58 LOADADDR(r4,1b) 59 subf r5,r4,r5 60 add r3,r3,r5 61 mtlr r0 62 blr 63 64/* 65 * sub_reloc_offset(x) returns x - reloc_offset(). 66 */ 67_GLOBAL(sub_reloc_offset) 68 mflr r0 69 bl 1f 701: mflr r5 71 lis r4,1b@ha 72 addi r4,r4,1b@l 73 subf r5,r4,r5 74 subf r3,r5,r3 75 mtlr r0 76 blr 77 78/* 79 * reloc_got2 runs through the .got2 section adding an offset 80 * to each entry. 81 */ 82_GLOBAL(reloc_got2) 83 mflr r11 84 lis r7,__got2_start@ha 85 addi r7,r7,__got2_start@l 86 lis r8,__got2_end@ha 87 addi r8,r8,__got2_end@l 88 subf r8,r7,r8 89 srwi. r8,r8,2 90 beqlr 91 mtctr r8 92 bl 1f 931: mflr r0 94 lis r4,1b@ha 95 addi r4,r4,1b@l 96 subf r0,r4,r0 97 add r7,r0,r7 982: lwz r0,0(r7) 99 add r0,r0,r3 100 stw r0,0(r7) 101 addi r7,r7,4 102 bdnz 2b 103 mtlr r11 104 blr 105 106/* 107 * identify_cpu, 108 * called with r3 = data offset and r4 = CPU number 109 * doesn't change r3 110 */ 111_GLOBAL(identify_cpu) 112 addis r8,r3,cpu_specs@ha 113 addi r8,r8,cpu_specs@l 114 mfpvr r7 1151: 116 lwz r5,CPU_SPEC_PVR_MASK(r8) 117 and r5,r5,r7 118 lwz r6,CPU_SPEC_PVR_VALUE(r8) 119 cmplw 0,r6,r5 120 beq 1f 121 addi r8,r8,CPU_SPEC_ENTRY_SIZE 122 b 1b 1231: 124 addis r6,r3,cur_cpu_spec@ha 125 addi r6,r6,cur_cpu_spec@l 126 sub r8,r8,r3 127 stw r8,0(r6) 128 blr 129 130/* 131 * do_cpu_ftr_fixups - goes through the list of CPU feature fixups 132 * and writes nop's over sections of code that don't apply for this cpu. 133 * r3 = data offset (not changed) 134 */ 135_GLOBAL(do_cpu_ftr_fixups) 136 /* Get CPU 0 features */ 137 addis r6,r3,cur_cpu_spec@ha 138 addi r6,r6,cur_cpu_spec@l 139 lwz r4,0(r6) 140 add r4,r4,r3 141 lwz r4,CPU_SPEC_FEATURES(r4) 142 143 /* Get the fixup table */ 144 addis r6,r3,__start___ftr_fixup@ha 145 addi r6,r6,__start___ftr_fixup@l 146 addis r7,r3,__stop___ftr_fixup@ha 147 addi r7,r7,__stop___ftr_fixup@l 148 149 /* Do the fixup */ 1501: cmplw 0,r6,r7 151 bgelr 152 addi r6,r6,16 153 lwz r8,-16(r6) /* mask */ 154 and r8,r8,r4 155 lwz r9,-12(r6) /* value */ 156 cmplw 0,r8,r9 157 beq 1b 158 lwz r8,-8(r6) /* section begin */ 159 lwz r9,-4(r6) /* section end */ 160 subf. r9,r8,r9 161 beq 1b 162 /* write nops over the section of code */ 163 /* todo: if large section, add a branch at the start of it */ 164 srwi r9,r9,2 165 mtctr r9 166 add r8,r8,r3 167 lis r0,0x60000000@h /* nop */ 1683: stw r0,0(r8) 169 andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l 170 beq 2f 171 dcbst 0,r8 /* suboptimal, but simpler */ 172 sync 173 icbi 0,r8 1742: addi r8,r8,4 175 bdnz 3b 176 sync /* additional sync needed on g4 */ 177 isync 178 b 1b 179 180/* 181 * call_setup_cpu - call the setup_cpu function for this cpu 182 * r3 = data offset, r24 = cpu number 183 * 184 * Setup function is called with: 185 * r3 = data offset 186 * r4 = ptr to CPU spec (relocated) 187 */ 188_GLOBAL(call_setup_cpu) 189 addis r4,r3,cur_cpu_spec@ha 190 addi r4,r4,cur_cpu_spec@l 191 lwz r4,0(r4) 192 add r4,r4,r3 193 lwz r5,CPU_SPEC_SETUP(r4) 194 cmpi 0,r5,0 195 add r5,r5,r3 196 beqlr 197 mtctr r5 198 bctr 199 200#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx) 201 202/* This gets called by via-pmu.c to switch the PLL selection 203 * on 750fx CPU. This function should really be moved to some 204 * other place (as most of the cpufreq code in via-pmu 205 */ 206_GLOBAL(low_choose_750fx_pll) 207 /* Clear MSR:EE */ 208 mfmsr r7 209 rlwinm r0,r7,0,17,15 210 mtmsr r0 211 212 /* If switching to PLL1, disable HID0:BTIC */ 213 cmplwi cr0,r3,0 214 beq 1f 215 mfspr r5,SPRN_HID0 216 rlwinm r5,r5,0,27,25 217 sync 218 mtspr SPRN_HID0,r5 219 isync 220 sync 221 2221: 223 /* Calc new HID1 value */ 224 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */ 225 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */ 226 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */ 227 or r4,r4,r5 228 mtspr SPRN_HID1,r4 229 230 /* Store new HID1 image */ 231 rlwinm r6,r1,0,0,18 232 lwz r6,TI_CPU(r6) 233 slwi r6,r6,2 234 addis r6,r6,nap_save_hid1@ha 235 stw r4,nap_save_hid1@l(r6) 236 237 /* If switching to PLL0, enable HID0:BTIC */ 238 cmplwi cr0,r3,0 239 bne 1f 240 mfspr r5,SPRN_HID0 241 ori r5,r5,HID0_BTIC 242 sync 243 mtspr SPRN_HID0,r5 244 isync 245 sync 246 2471: 248 /* Return */ 249 mtmsr r7 250 blr 251 252_GLOBAL(low_choose_7447a_dfs) 253 /* Clear MSR:EE */ 254 mfmsr r7 255 rlwinm r0,r7,0,17,15 256 mtmsr r0 257 258 /* Calc new HID1 value */ 259 mfspr r4,SPRN_HID1 260 insrwi r4,r3,1,9 /* insert parameter into bit 9 */ 261 sync 262 mtspr SPRN_HID1,r4 263 sync 264 isync 265 266 /* Return */ 267 mtmsr r7 268 blr 269 270#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */ 271 272/* 273 * complement mask on the msr then "or" some values on. 274 * _nmask_and_or_msr(nmask, value_to_or) 275 */ 276_GLOBAL(_nmask_and_or_msr) 277 mfmsr r0 /* Get current msr */ 278 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */ 279 or r0,r0,r4 /* Or on the bits in r4 (second parm) */ 280 SYNC /* Some chip revs have problems here... */ 281 mtmsr r0 /* Update machine state */ 282 isync 283 blr /* Done */ 284 285 286/* 287 * Flush MMU TLB 288 */ 289_GLOBAL(_tlbia) 290#if defined(CONFIG_40x) 291 sync /* Flush to memory before changing mapping */ 292 tlbia 293 isync /* Flush shadow TLB */ 294#elif defined(CONFIG_44x) 295 li r3,0 296 sync 297 298 /* Load high watermark */ 299 lis r4,tlb_44x_hwater@ha 300 lwz r5,tlb_44x_hwater@l(r4) 301 3021: tlbwe r3,r3,PPC44x_TLB_PAGEID 303 addi r3,r3,1 304 cmpw 0,r3,r5 305 ble 1b 306 307 isync 308#elif defined(CONFIG_FSL_BOOKE) 309 /* Invalidate all entries in TLB0 */ 310 li r3, 0x04 311 tlbivax 0,3 312 /* Invalidate all entries in TLB1 */ 313 li r3, 0x0c 314 tlbivax 0,3 315 /* Invalidate all entries in TLB2 */ 316 li r3, 0x14 317 tlbivax 0,3 318 /* Invalidate all entries in TLB3 */ 319 li r3, 0x1c 320 tlbivax 0,3 321 msync 322#ifdef CONFIG_SMP 323 tlbsync 324#endif /* CONFIG_SMP */ 325#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */ 326#if defined(CONFIG_SMP) 327 rlwinm r8,r1,0,0,18 328 lwz r8,TI_CPU(r8) 329 oris r8,r8,10 330 mfmsr r10 331 SYNC 332 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 333 rlwinm r0,r0,0,28,26 /* clear DR */ 334 mtmsr r0 335 SYNC_601 336 isync 337 lis r9,mmu_hash_lock@h 338 ori r9,r9,mmu_hash_lock@l 339 tophys(r9,r9) 34010: lwarx r7,0,r9 341 cmpwi 0,r7,0 342 bne- 10b 343 stwcx. r8,0,r9 344 bne- 10b 345 sync 346 tlbia 347 sync 348 TLBSYNC 349 li r0,0 350 stw r0,0(r9) /* clear mmu_hash_lock */ 351 mtmsr r10 352 SYNC_601 353 isync 354#else /* CONFIG_SMP */ 355 sync 356 tlbia 357 sync 358#endif /* CONFIG_SMP */ 359#endif /* ! defined(CONFIG_40x) */ 360 blr 361 362/* 363 * Flush MMU TLB for a particular address 364 */ 365_GLOBAL(_tlbie) 366#if defined(CONFIG_40x) 367 tlbsx. r3, 0, r3 368 bne 10f 369 sync 370 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear. 371 * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate 372 * the TLB entry. */ 373 tlbwe r3, r3, TLB_TAG 374 isync 37510: 376#elif defined(CONFIG_44x) 377 mfspr r4,SPRN_MMUCR 378 mfspr r5,SPRN_PID /* Get PID */ 379 rlwimi r4,r5,0,24,31 /* Set TID */ 380 mtspr SPRN_MMUCR,r4 381 382 tlbsx. r3, 0, r3 383 bne 10f 384 sync 385 /* There are only 64 TLB entries, so r3 < 64, 386 * which means bit 22, is clear. Since 22 is 387 * the V bit in the TLB_PAGEID, loading this 388 * value will invalidate the TLB entry. 389 */ 390 tlbwe r3, r3, PPC44x_TLB_PAGEID 391 isync 39210: 393#elif defined(CONFIG_FSL_BOOKE) 394 rlwinm r4, r3, 0, 0, 19 395 ori r5, r4, 0x08 /* TLBSEL = 1 */ 396 ori r6, r4, 0x10 /* TLBSEL = 2 */ 397 ori r7, r4, 0x18 /* TLBSEL = 3 */ 398 tlbivax 0, r4 399 tlbivax 0, r5 400 tlbivax 0, r6 401 tlbivax 0, r7 402 msync 403#if defined(CONFIG_SMP) 404 tlbsync 405#endif /* CONFIG_SMP */ 406#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */ 407#if defined(CONFIG_SMP) 408 rlwinm r8,r1,0,0,18 409 lwz r8,TI_CPU(r8) 410 oris r8,r8,11 411 mfmsr r10 412 SYNC 413 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ 414 rlwinm r0,r0,0,28,26 /* clear DR */ 415 mtmsr r0 416 SYNC_601 417 isync 418 lis r9,mmu_hash_lock@h 419 ori r9,r9,mmu_hash_lock@l 420 tophys(r9,r9) 42110: lwarx r7,0,r9 422 cmpwi 0,r7,0 423 bne- 10b 424 stwcx. r8,0,r9 425 bne- 10b 426 eieio 427 tlbie r3 428 sync 429 TLBSYNC 430 li r0,0 431 stw r0,0(r9) /* clear mmu_hash_lock */ 432 mtmsr r10 433 SYNC_601 434 isync 435#else /* CONFIG_SMP */ 436 tlbie r3 437 sync 438#endif /* CONFIG_SMP */ 439#endif /* ! CONFIG_40x */ 440 blr 441 442/* 443 * Flush instruction cache. 444 * This is a no-op on the 601. 445 */ 446_GLOBAL(flush_instruction_cache) 447#if defined(CONFIG_8xx) 448 isync 449 lis r5, IDC_INVALL@h 450 mtspr SPRN_IC_CST, r5 451#elif defined(CONFIG_4xx) 452#ifdef CONFIG_403GCX 453 li r3, 512 454 mtctr r3 455 lis r4, KERNELBASE@h 4561: iccci 0, r4 457 addi r4, r4, 16 458 bdnz 1b 459#else 460 lis r3, KERNELBASE@h 461 iccci 0,r3 462#endif 463#elif CONFIG_FSL_BOOKE 464BEGIN_FTR_SECTION 465 mfspr r3,SPRN_L1CSR0 466 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC 467 /* msync; isync recommended here */ 468 mtspr SPRN_L1CSR0,r3 469 isync 470 blr 471END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) 472 mfspr r3,SPRN_L1CSR1 473 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR 474 mtspr SPRN_L1CSR1,r3 475#else 476 mfspr r3,SPRN_PVR 477 rlwinm r3,r3,16,16,31 478 cmpwi 0,r3,1 479 beqlr /* for 601, do nothing */ 480 /* 603/604 processor - use invalidate-all bit in HID0 */ 481 mfspr r3,SPRN_HID0 482 ori r3,r3,HID0_ICFI 483 mtspr SPRN_HID0,r3 484#endif /* CONFIG_8xx/4xx */ 485 isync 486 blr 487 488/* 489 * Write any modified data cache blocks out to memory 490 * and invalidate the corresponding instruction cache blocks. 491 * This is a no-op on the 601. 492 * 493 * flush_icache_range(unsigned long start, unsigned long stop) 494 */ 495_GLOBAL(flush_icache_range) 496BEGIN_FTR_SECTION 497 blr /* for 601, do nothing */ 498END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) 499 li r5,L1_CACHE_LINE_SIZE-1 500 andc r3,r3,r5 501 subf r4,r3,r4 502 add r4,r4,r5 503 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE 504 beqlr 505 mtctr r4 506 mr r6,r3 5071: dcbst 0,r3 508 addi r3,r3,L1_CACHE_LINE_SIZE 509 bdnz 1b 510 sync /* wait for dcbst's to get to ram */ 511 mtctr r4 5122: icbi 0,r6 513 addi r6,r6,L1_CACHE_LINE_SIZE 514 bdnz 2b 515 sync /* additional sync needed on g4 */ 516 isync 517 blr 518/* 519 * Write any modified data cache blocks out to memory. 520 * Does not invalidate the corresponding cache lines (especially for 521 * any corresponding instruction cache). 522 * 523 * clean_dcache_range(unsigned long start, unsigned long stop) 524 */ 525_GLOBAL(clean_dcache_range) 526 li r5,L1_CACHE_LINE_SIZE-1 527 andc r3,r3,r5 528 subf r4,r3,r4 529 add r4,r4,r5 530 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE 531 beqlr 532 mtctr r4 533 5341: dcbst 0,r3 535 addi r3,r3,L1_CACHE_LINE_SIZE 536 bdnz 1b 537 sync /* wait for dcbst's to get to ram */ 538 blr 539 540/* 541 * Write any modified data cache blocks out to memory and invalidate them. 542 * Does not invalidate the corresponding instruction cache blocks. 543 * 544 * flush_dcache_range(unsigned long start, unsigned long stop) 545 */ 546_GLOBAL(flush_dcache_range) 547 li r5,L1_CACHE_LINE_SIZE-1 548 andc r3,r3,r5 549 subf r4,r3,r4 550 add r4,r4,r5 551 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE 552 beqlr 553 mtctr r4 554 5551: dcbf 0,r3 556 addi r3,r3,L1_CACHE_LINE_SIZE 557 bdnz 1b 558 sync /* wait for dcbst's to get to ram */ 559 blr 560 561/* 562 * Like above, but invalidate the D-cache. This is used by the 8xx 563 * to invalidate the cache so the PPC core doesn't get stale data 564 * from the CPM (no cache snooping here :-). 565 * 566 * invalidate_dcache_range(unsigned long start, unsigned long stop) 567 */ 568_GLOBAL(invalidate_dcache_range) 569 li r5,L1_CACHE_LINE_SIZE-1 570 andc r3,r3,r5 571 subf r4,r3,r4 572 add r4,r4,r5 573 srwi. r4,r4,LG_L1_CACHE_LINE_SIZE 574 beqlr 575 mtctr r4 576 5771: dcbi 0,r3 578 addi r3,r3,L1_CACHE_LINE_SIZE 579 bdnz 1b 580 sync /* wait for dcbi's to get to ram */ 581 blr 582 583#ifdef CONFIG_NOT_COHERENT_CACHE 584/* 585 * 40x cores have 8K or 16K dcache and 32 byte line size. 586 * 44x has a 32K dcache and 32 byte line size. 587 * 8xx has 1, 2, 4, 8K variants. 588 * For now, cover the worst case of the 44x. 589 * Must be called with external interrupts disabled. 590 */ 591#define CACHE_NWAYS 64 592#define CACHE_NLINES 16 593 594_GLOBAL(flush_dcache_all) 595 li r4, (2 * CACHE_NWAYS * CACHE_NLINES) 596 mtctr r4 597 lis r5, KERNELBASE@h 5981: lwz r3, 0(r5) /* Load one word from every line */ 599 addi r5, r5, L1_CACHE_LINE_SIZE 600 bdnz 1b 601 blr 602#endif /* CONFIG_NOT_COHERENT_CACHE */ 603 604/* 605 * Flush a particular page from the data cache to RAM. 606 * Note: this is necessary because the instruction cache does *not* 607 * snoop from the data cache. 608 * This is a no-op on the 601 which has a unified cache. 609 * 610 * void __flush_dcache_icache(void *page) 611 */ 612_GLOBAL(__flush_dcache_icache) 613BEGIN_FTR_SECTION 614 blr /* for 601, do nothing */ 615END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) 616 rlwinm r3,r3,0,0,19 /* Get page base address */ 617 li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */ 618 mtctr r4 619 mr r6,r3 6200: dcbst 0,r3 /* Write line to ram */ 621 addi r3,r3,L1_CACHE_LINE_SIZE 622 bdnz 0b 623 sync 624 mtctr r4 6251: icbi 0,r6 626 addi r6,r6,L1_CACHE_LINE_SIZE 627 bdnz 1b 628 sync 629 isync 630 blr 631 632/* 633 * Flush a particular page from the data cache to RAM, identified 634 * by its physical address. We turn off the MMU so we can just use 635 * the physical address (this may be a highmem page without a kernel 636 * mapping). 637 * 638 * void __flush_dcache_icache_phys(unsigned long physaddr) 639 */ 640_GLOBAL(__flush_dcache_icache_phys) 641BEGIN_FTR_SECTION 642 blr /* for 601, do nothing */ 643END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) 644 mfmsr r10 645 rlwinm r0,r10,0,28,26 /* clear DR */ 646 mtmsr r0 647 isync 648 rlwinm r3,r3,0,0,19 /* Get page base address */ 649 li r4,4096/L1_CACHE_LINE_SIZE /* Number of lines in a page */ 650 mtctr r4 651 mr r6,r3 6520: dcbst 0,r3 /* Write line to ram */ 653 addi r3,r3,L1_CACHE_LINE_SIZE 654 bdnz 0b 655 sync 656 mtctr r4 6571: icbi 0,r6 658 addi r6,r6,L1_CACHE_LINE_SIZE 659 bdnz 1b 660 sync 661 mtmsr r10 /* restore DR */ 662 isync 663 blr 664 665/* 666 * Clear pages using the dcbz instruction, which doesn't cause any 667 * memory traffic (except to write out any cache lines which get 668 * displaced). This only works on cacheable memory. 669 * 670 * void clear_pages(void *page, int order) ; 671 */ 672_GLOBAL(clear_pages) 673 li r0,4096/L1_CACHE_LINE_SIZE 674 slw r0,r0,r4 675 mtctr r0 676#ifdef CONFIG_8xx 677 li r4, 0 6781: stw r4, 0(r3) 679 stw r4, 4(r3) 680 stw r4, 8(r3) 681 stw r4, 12(r3) 682#else 6831: dcbz 0,r3 684#endif 685 addi r3,r3,L1_CACHE_LINE_SIZE 686 bdnz 1b 687 blr 688 689/* 690 * Copy a whole page. We use the dcbz instruction on the destination 691 * to reduce memory traffic (it eliminates the unnecessary reads of 692 * the destination into cache). This requires that the destination 693 * is cacheable. 694 */ 695#define COPY_16_BYTES \ 696 lwz r6,4(r4); \ 697 lwz r7,8(r4); \ 698 lwz r8,12(r4); \ 699 lwzu r9,16(r4); \ 700 stw r6,4(r3); \ 701 stw r7,8(r3); \ 702 stw r8,12(r3); \ 703 stwu r9,16(r3) 704 705_GLOBAL(copy_page) 706 addi r3,r3,-4 707 addi r4,r4,-4 708 709#ifdef CONFIG_8xx 710 /* don't use prefetch on 8xx */ 711 li r0,4096/L1_CACHE_LINE_SIZE 712 mtctr r0 7131: COPY_16_BYTES 714 bdnz 1b 715 blr 716 717#else /* not 8xx, we can prefetch */ 718 li r5,4 719 720#if MAX_COPY_PREFETCH > 1 721 li r0,MAX_COPY_PREFETCH 722 li r11,4 723 mtctr r0 72411: dcbt r11,r4 725 addi r11,r11,L1_CACHE_LINE_SIZE 726 bdnz 11b 727#else /* MAX_COPY_PREFETCH == 1 */ 728 dcbt r5,r4 729 li r11,L1_CACHE_LINE_SIZE+4 730#endif /* MAX_COPY_PREFETCH */ 731 li r0,4096/L1_CACHE_LINE_SIZE - MAX_COPY_PREFETCH 732 crclr 4*cr0+eq 7332: 734 mtctr r0 7351: 736 dcbt r11,r4 737 dcbz r5,r3 738 COPY_16_BYTES 739#if L1_CACHE_LINE_SIZE >= 32 740 COPY_16_BYTES 741#if L1_CACHE_LINE_SIZE >= 64 742 COPY_16_BYTES 743 COPY_16_BYTES 744#if L1_CACHE_LINE_SIZE >= 128 745 COPY_16_BYTES 746 COPY_16_BYTES 747 COPY_16_BYTES 748 COPY_16_BYTES 749#endif 750#endif 751#endif 752 bdnz 1b 753 beqlr 754 crnot 4*cr0+eq,4*cr0+eq 755 li r0,MAX_COPY_PREFETCH 756 li r11,4 757 b 2b 758#endif /* CONFIG_8xx */ 759 760/* 761 * void atomic_clear_mask(atomic_t mask, atomic_t *addr) 762 * void atomic_set_mask(atomic_t mask, atomic_t *addr); 763 */ 764_GLOBAL(atomic_clear_mask) 76510: lwarx r5,0,r4 766 andc r5,r5,r3 767 PPC405_ERR77(0,r4) 768 stwcx. r5,0,r4 769 bne- 10b 770 blr 771_GLOBAL(atomic_set_mask) 77210: lwarx r5,0,r4 773 or r5,r5,r3 774 PPC405_ERR77(0,r4) 775 stwcx. r5,0,r4 776 bne- 10b 777 blr 778 779/* 780 * I/O string operations 781 * 782 * insb(port, buf, len) 783 * outsb(port, buf, len) 784 * insw(port, buf, len) 785 * outsw(port, buf, len) 786 * insl(port, buf, len) 787 * outsl(port, buf, len) 788 * insw_ns(port, buf, len) 789 * outsw_ns(port, buf, len) 790 * insl_ns(port, buf, len) 791 * outsl_ns(port, buf, len) 792 * 793 * The *_ns versions don't do byte-swapping. 794 */ 795_GLOBAL(_insb) 796 cmpwi 0,r5,0 797 mtctr r5 798 subi r4,r4,1 799 blelr- 80000: lbz r5,0(r3) 801 eieio 802 stbu r5,1(r4) 803 bdnz 00b 804 blr 805 806_GLOBAL(_outsb) 807 cmpwi 0,r5,0 808 mtctr r5 809 subi r4,r4,1 810 blelr- 81100: lbzu r5,1(r4) 812 stb r5,0(r3) 813 eieio 814 bdnz 00b 815 blr 816 817_GLOBAL(_insw) 818 cmpwi 0,r5,0 819 mtctr r5 820 subi r4,r4,2 821 blelr- 82200: lhbrx r5,0,r3 823 eieio 824 sthu r5,2(r4) 825 bdnz 00b 826 blr 827 828_GLOBAL(_outsw) 829 cmpwi 0,r5,0 830 mtctr r5 831 subi r4,r4,2 832 blelr- 83300: lhzu r5,2(r4) 834 eieio 835 sthbrx r5,0,r3 836 bdnz 00b 837 blr 838 839_GLOBAL(_insl) 840 cmpwi 0,r5,0 841 mtctr r5 842 subi r4,r4,4 843 blelr- 84400: lwbrx r5,0,r3 845 eieio 846 stwu r5,4(r4) 847 bdnz 00b 848 blr 849 850_GLOBAL(_outsl) 851 cmpwi 0,r5,0 852 mtctr r5 853 subi r4,r4,4 854 blelr- 85500: lwzu r5,4(r4) 856 stwbrx r5,0,r3 857 eieio 858 bdnz 00b 859 blr 860 861_GLOBAL(__ide_mm_insw) 862_GLOBAL(_insw_ns) 863 cmpwi 0,r5,0 864 mtctr r5 865 subi r4,r4,2 866 blelr- 86700: lhz r5,0(r3) 868 eieio 869 sthu r5,2(r4) 870 bdnz 00b 871 blr 872 873_GLOBAL(__ide_mm_outsw) 874_GLOBAL(_outsw_ns) 875 cmpwi 0,r5,0 876 mtctr r5 877 subi r4,r4,2 878 blelr- 87900: lhzu r5,2(r4) 880 sth r5,0(r3) 881 eieio 882 bdnz 00b 883 blr 884 885_GLOBAL(__ide_mm_insl) 886_GLOBAL(_insl_ns) 887 cmpwi 0,r5,0 888 mtctr r5 889 subi r4,r4,4 890 blelr- 89100: lwz r5,0(r3) 892 eieio 893 stwu r5,4(r4) 894 bdnz 00b 895 blr 896 897_GLOBAL(__ide_mm_outsl) 898_GLOBAL(_outsl_ns) 899 cmpwi 0,r5,0 900 mtctr r5 901 subi r4,r4,4 902 blelr- 90300: lwzu r5,4(r4) 904 stw r5,0(r3) 905 eieio 906 bdnz 00b 907 blr 908 909/* 910 * Extended precision shifts. 911 * 912 * Updated to be valid for shift counts from 0 to 63 inclusive. 913 * -- Gabriel 914 * 915 * R3/R4 has 64 bit value 916 * R5 has shift count 917 * result in R3/R4 918 * 919 * ashrdi3: arithmetic right shift (sign propagation) 920 * lshrdi3: logical right shift 921 * ashldi3: left shift 922 */ 923_GLOBAL(__ashrdi3) 924 subfic r6,r5,32 925 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count 926 addi r7,r5,32 # could be xori, or addi with -32 927 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) 928 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0 929 sraw r7,r3,r7 # t2 = MSW >> (count-32) 930 or r4,r4,r6 # LSW |= t1 931 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2 932 sraw r3,r3,r5 # MSW = MSW >> count 933 or r4,r4,r7 # LSW |= t2 934 blr 935 936_GLOBAL(__ashldi3) 937 subfic r6,r5,32 938 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count 939 addi r7,r5,32 # could be xori, or addi with -32 940 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count) 941 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32) 942 or r3,r3,r6 # MSW |= t1 943 slw r4,r4,r5 # LSW = LSW << count 944 or r3,r3,r7 # MSW |= t2 945 blr 946 947_GLOBAL(__lshrdi3) 948 subfic r6,r5,32 949 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count 950 addi r7,r5,32 # could be xori, or addi with -32 951 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) 952 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32) 953 or r4,r4,r6 # LSW |= t1 954 srw r3,r3,r5 # MSW = MSW >> count 955 or r4,r4,r7 # LSW |= t2 956 blr 957 958_GLOBAL(abs) 959 srawi r4,r3,31 960 xor r3,r3,r4 961 sub r3,r3,r4 962 blr 963 964_GLOBAL(_get_SP) 965 mr r3,r1 /* Close enough */ 966 blr 967 968/* 969 * These are used in the alignment trap handler when emulating 970 * single-precision loads and stores. 971 * We restore and save the fpscr so the task gets the same result 972 * and exceptions as if the cpu had performed the load or store. 973 */ 974 975#ifdef CONFIG_PPC_FPU 976_GLOBAL(cvt_fd) 977 lfd 0,-4(r5) /* load up fpscr value */ 978 mtfsf 0xff,0 979 lfs 0,0(r3) 980 stfd 0,0(r4) 981 mffs 0 /* save new fpscr value */ 982 stfd 0,-4(r5) 983 blr 984 985_GLOBAL(cvt_df) 986 lfd 0,-4(r5) /* load up fpscr value */ 987 mtfsf 0xff,0 988 lfd 0,0(r3) 989 stfs 0,0(r4) 990 mffs 0 /* save new fpscr value */ 991 stfd 0,-4(r5) 992 blr 993#endif 994 995/* 996 * Create a kernel thread 997 * kernel_thread(fn, arg, flags) 998 */ 999_GLOBAL(kernel_thread) 1000 stwu r1,-16(r1) 1001 stw r30,8(r1) 1002 stw r31,12(r1) 1003 mr r30,r3 /* function */ 1004 mr r31,r4 /* argument */ 1005 ori r3,r5,CLONE_VM /* flags */ 1006 oris r3,r3,CLONE_UNTRACED>>16 1007 li r4,0 /* new sp (unused) */ 1008 li r0,__NR_clone 1009 sc 1010 cmpwi 0,r3,0 /* parent or child? */ 1011 bne 1f /* return if parent */ 1012 li r0,0 /* make top-level stack frame */ 1013 stwu r0,-16(r1) 1014 mtlr r30 /* fn addr in lr */ 1015 mr r3,r31 /* load arg and call fn */ 1016 PPC440EP_ERR42 1017 blrl 1018 li r0,__NR_exit /* exit if function returns */ 1019 li r3,0 1020 sc 10211: lwz r30,8(r1) 1022 lwz r31,12(r1) 1023 addi r1,r1,16 1024 blr 1025 1026_GLOBAL(execve) 1027 li r0,__NR_execve 1028 sc 1029 bnslr 1030 neg r3,r3 1031 blr 1032 1033/* 1034 * This routine is just here to keep GCC happy - sigh... 1035 */ 1036_GLOBAL(__main) 1037 blr 1038