1d94d71cbSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 27cabf491SVarun Sethi /* 37cabf491SVarun Sethi * 47cabf491SVarun Sethi * Copyright (C) 2013 Freescale Semiconductor, Inc. 57cabf491SVarun Sethi */ 67cabf491SVarun Sethi 77cabf491SVarun Sethi #ifndef __FSL_PAMU_STASH_H 87cabf491SVarun Sethi #define __FSL_PAMU_STASH_H 97cabf491SVarun Sethi 104eeb96f6SChristoph Hellwig struct iommu_domain; 114eeb96f6SChristoph Hellwig 127cabf491SVarun Sethi /* cache stash targets */ 137cabf491SVarun Sethi enum pamu_stash_target { 147cabf491SVarun Sethi PAMU_ATTR_CACHE_L1 = 1, 157cabf491SVarun Sethi PAMU_ATTR_CACHE_L2, 167cabf491SVarun Sethi PAMU_ATTR_CACHE_L3, 177cabf491SVarun Sethi }; 187cabf491SVarun Sethi 194eeb96f6SChristoph Hellwig int fsl_pamu_configure_l1_stash(struct iommu_domain *domain, u32 cpu); 207cabf491SVarun Sethi 217cabf491SVarun Sethi #endif /* __FSL_PAMU_STASH_H */ 22