1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21da177e4SLinus Torvalds /* 31da177e4SLinus Torvalds * include/asm-parisc/cache.h 41da177e4SLinus Torvalds */ 51da177e4SLinus Torvalds 61da177e4SLinus Torvalds #ifndef __ARCH_PARISC_CACHE_H 71da177e4SLinus Torvalds #define __ARCH_PARISC_CACHE_H 81da177e4SLinus Torvalds 93847dab7SHelge Deller #include <asm/alternative.h> 101da177e4SLinus Torvalds 111da177e4SLinus Torvalds /* 12a01fece2SJohn David Anglin * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors 13a01fece2SJohn David Anglin * have 32-byte cachelines. The L1 length appears to be 16 bytes but this 14a01fece2SJohn David Anglin * is not clearly documented. 151da177e4SLinus Torvalds */ 16a01fece2SJohn David Anglin #define L1_CACHE_BYTES 16 17a01fece2SJohn David Anglin #define L1_CACHE_SHIFT 4 181da177e4SLinus Torvalds 191da177e4SLinus Torvalds #ifndef __ASSEMBLER__ 201da177e4SLinus Torvalds 211da177e4SLinus Torvalds #define SMP_CACHE_BYTES L1_CACHE_BYTES 221da177e4SLinus Torvalds 237896bfa4SFUJITA Tomonori #ifdef CONFIG_PA20 247896bfa4SFUJITA Tomonori #define ARCH_DMA_MINALIGN 128 2533def849SJoe Perches #else 26804f1594SKyle McMartin #define ARCH_DMA_MINALIGN 32 27d6ce8626SRandolph Chung #endif 28d6ce8626SRandolph Chung #define ARCH_KMALLOC_MINALIGN 16 /* ldcw requires 16-byte alignment */ 29d6ce8626SRandolph Chung 30d6ce8626SRandolph Chung #define arch_slab_minalign() ((unsigned)dcache_stride) 311da177e4SLinus Torvalds #define cache_line_size() dcache_stride 321da177e4SLinus Torvalds #define dma_get_cache_alignment cache_line_size 331da177e4SLinus Torvalds 341da177e4SLinus Torvalds #define __read_mostly __section(".data..read_mostly") 351da177e4SLinus Torvalds 361da177e4SLinus Torvalds void parisc_cache_init(void); /* initializes cache-flushing */ 371da177e4SLinus Torvalds void disable_sr_hashing_asm(int); /* low level support for above */ 381da177e4SLinus Torvalds void disable_sr_hashing(void); /* turns off space register hashing */ 391da177e4SLinus Torvalds void free_sid(unsigned long); 40*e5ef93d0SHelge Deller unsigned long alloc_sid(void); 41d6ce8626SRandolph Chung 421da177e4SLinus Torvalds struct seq_file; 43360bd6c6SHelge Deller extern void show_cache_info(struct seq_file *m); 443847dab7SHelge Deller 45360bd6c6SHelge Deller extern int split_tlb; 46360bd6c6SHelge Deller extern int dcache_stride; 473847dab7SHelge Deller extern int icache_stride; 483847dab7SHelge Deller extern struct pdc_cache_info cache_info; 49360bd6c6SHelge Deller extern struct pdc_btlb_info btlb_info; 503847dab7SHelge Deller void parisc_setup_cache_timing(void); 513847dab7SHelge Deller 523847dab7SHelge Deller #define pdtlb(sr, addr) asm volatile("pdtlb 0(%%sr%0,%1)" \ 533847dab7SHelge Deller ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \ 542d94a832SHelge Deller : : "i"(sr), "r" (addr) : "memory") 553847dab7SHelge Deller #define pitlb(sr, addr) asm volatile("pitlb 0(%%sr%0,%1)" \ 563847dab7SHelge Deller ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \ 572d94a832SHelge Deller ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \ 581fc7db24SJohn David Anglin : : "i"(sr), "r" (addr) : "memory") 591da177e4SLinus Torvalds 601da177e4SLinus Torvalds #define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \ 611da177e4SLinus Torvalds ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \ 621da177e4SLinus Torvalds ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \ 631da177e4SLinus Torvalds : : "r" (addr) : "memory") 641da177e4SLinus Torvalds #define asm_io_sync() asm volatile("sync" \ 651da177e4SLinus Torvalds ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \ 661da177e4SLinus Torvalds ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :::"memory") 671da177e4SLinus Torvalds #define asm_syncdma() asm volatile("syncdma" :::"memory") 681da177e4SLinus Torvalds 69 #endif /* ! __ASSEMBLER__ */ 70 71 /* Classes of processor wrt: disabling space register hashing */ 72 73 #define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */ 74 #define SRHASH_PCXL 1 /* pcxl */ 75 #define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */ 76 77 #endif 78