xref: /linux/arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi (revision d89a415ff8d5e0aad4963f2d8ebb0f9e8110b7fa) 
1// SPDX-License-Identifier: GPL-2.0
2
3/dts-v1/;
4
5#include <dt-bindings/interrupt-controller/irq.h>
6
7/ {
8	compatible = "loongson,loongson2k1000";
9
10	#address-cells = <2>;
11	#size-cells = <2>;
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu0: cpu@0 {
18			device_type = "cpu";
19			compatible = "loongson,gs264";
20			reg = <0x0>;
21			#clock-cells = <1>;
22			clocks = <&cpu_clk>;
23		};
24	};
25
26	memory@200000 {
27		compatible = "memory";
28		device_type = "memory";
29		reg = <0x00000000 0x00200000 0x00000000 0x0ee00000>, /* 238 MB at 2 MB */
30			<0x00000000 0x20000000 0x00000000 0x1f000000>, /* 496 MB at 512 MB */
31			<0x00000001 0x10000000 0x00000001 0xb0000000>; /* 6912 MB at 4352MB */
32	};
33
34	cpu_clk: cpu_clk {
35		#clock-cells = <0>;
36		compatible = "fixed-clock";
37		clock-frequency = <800000000>;
38	};
39
40	cpuintc: interrupt-controller {
41		#address-cells = <0>;
42		#interrupt-cells = <1>;
43		interrupt-controller;
44		compatible = "mti,cpu-interrupt-controller";
45	};
46
47	package0: bus@10000000 {
48		compatible = "simple-bus";
49		#address-cells = <2>;
50		#size-cells = <2>;
51		ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */
52			0 0x40000000 0 0x40000000 0 0x40000000
53			0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
54
55		pm: reset-controller@1fe07000 {
56			compatible = "loongson,ls2k-pm";
57			reg = <0 0x1fe07000 0 0x422>;
58		};
59
60		liointc0: interrupt-controller@1fe11400 {
61			compatible = "loongson,liointc-2.0";
62			reg = <0 0x1fe11400 0 0x40>,
63				<0 0x1fe11040 0 0x8>,
64				<0 0x1fe11140 0 0x8>;
65			reg-names = "main", "isr0", "isr1";
66
67			interrupt-controller;
68			#interrupt-cells = <2>;
69
70			interrupt-parent = <&cpuintc>;
71			interrupts = <2>;
72			interrupt-names = "int0";
73
74			loongson,parent_int_map = <0xffffffff>, /* int0 */
75						<0x00000000>, /* int1 */
76						<0x00000000>, /* int2 */
77						<0x00000000>; /* int3 */
78		};
79
80		liointc1: interrupt-controller@1fe11440 {
81			compatible = "loongson,liointc-2.0";
82			reg = <0 0x1fe11440 0 0x40>,
83				<0 0x1fe11048 0 0x8>,
84				<0 0x1fe11148 0 0x8>;
85			reg-names = "main", "isr0", "isr1";
86
87			interrupt-controller;
88			#interrupt-cells = <2>;
89
90			interrupt-parent = <&cpuintc>;
91			interrupts = <3>;
92			interrupt-names = "int1";
93
94			loongson,parent_int_map = <0x00000000>, /* int0 */
95						<0xffffffff>, /* int1 */
96						<0x00000000>, /* int2 */
97						<0x00000000>; /* int3 */
98		};
99
100		rtc0: rtc@1fe07800 {
101			compatible = "loongson,ls2k1000-rtc";
102			reg = <0 0x1fe07800 0 0x78>;
103			interrupt-parent = <&liointc0>;
104			interrupts = <60 IRQ_TYPE_LEVEL_LOW>;
105		};
106
107		uart0: serial@1fe00000 {
108			compatible = "ns16550a";
109			reg = <0 0x1fe00000 0 0x8>;
110			clock-frequency = <125000000>;
111			interrupt-parent = <&liointc0>;
112			interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
113			no-loopback-test;
114		};
115
116		pci@1a000000 {
117			compatible = "loongson,ls2k-pci";
118			device_type = "pci";
119			#address-cells = <3>;
120			#size-cells = <2>;
121
122			reg = <0 0x1a000000 0 0x02000000>,
123				<0xfe 0x00000000 0 0x20000000>;
124
125			ranges = <0x01000000 0x0 0x00000000 0x0 0x18000000  0x0 0x00010000>,
126				 <0x02000000 0x0 0x40000000 0x0 0x40000000  0x0 0x40000000>;
127
128			gmac@3,0 {
129				compatible = "pci0014,7a03.0",
130						   "pci0014,7a03",
131						   "pciclass0c0320",
132						   "pciclass0c03";
133
134				reg = <0x1800 0x0 0x0 0x0 0x0>;
135				interrupts = <12 IRQ_TYPE_LEVEL_LOW>,
136					     <13 IRQ_TYPE_LEVEL_LOW>;
137				interrupt-names = "macirq", "eth_lpi";
138				interrupt-parent = <&liointc0>;
139				phy-mode = "rgmii";
140				mdio {
141					#address-cells = <1>;
142					#size-cells = <0>;
143					compatible = "snps,dwmac-mdio";
144					phy0: ethernet-phy@0 {
145						reg = <0>;
146					};
147				};
148			};
149
150			gmac@3,1 {
151				compatible = "pci0014,7a03.0",
152						   "pci0014,7a03",
153						   "pciclass0c0320",
154						   "pciclass0c03",
155						   "loongson, pci-gmac";
156
157				reg = <0x1900 0x0 0x0 0x0 0x0>;
158				interrupts = <14 IRQ_TYPE_LEVEL_LOW>,
159					     <15 IRQ_TYPE_LEVEL_LOW>;
160				interrupt-names = "macirq", "eth_lpi";
161				interrupt-parent = <&liointc0>;
162				phy-mode = "rgmii";
163				mdio {
164					#address-cells = <1>;
165					#size-cells = <0>;
166					compatible = "snps,dwmac-mdio";
167					phy1: ethernet-phy@1 {
168						reg = <0>;
169					};
170				};
171			};
172
173			ehci@4,1 {
174				compatible = "pci0014,7a14.0",
175						   "pci0014,7a14",
176						   "pciclass0c0320",
177						   "pciclass0c03";
178
179				reg = <0x2100 0x0 0x0 0x0 0x0>;
180				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
181				interrupt-parent = <&liointc1>;
182			};
183
184			ohci@4,2 {
185				compatible = "pci0014,7a24.0",
186						   "pci0014,7a24",
187						   "pciclass0c0310",
188						   "pciclass0c03";
189
190				reg = <0x2200 0x0 0x0 0x0 0x0>;
191				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
192				interrupt-parent = <&liointc1>;
193			};
194
195			sata@8,0 {
196				compatible = "pci0014,7a08.0",
197						   "pci0014,7a08",
198						   "pciclass010601",
199						   "pciclass0106";
200
201				reg = <0x4000 0x0 0x0 0x0 0x0>;
202				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
203				interrupt-parent = <&liointc0>;
204			};
205
206			pcie@9,0 {
207				compatible = "pci0014,7a19.0",
208						   "pci0014,7a19",
209						   "pciclass060400",
210						   "pciclass0604";
211
212				reg = <0x4800 0x0 0x0 0x0 0x0>;
213				#address-cells = <3>;
214				#size-cells = <2>;
215				device_type = "pci";
216				#interrupt-cells = <1>;
217				interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
218				interrupt-parent = <&liointc1>;
219				interrupt-map-mask = <0 0 0 0>;
220				interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>;
221				ranges;
222				external-facing;
223			};
224
225			pcie@a,0 {
226				compatible = "pci0014,7a09.0",
227						   "pci0014,7a09",
228						   "pciclass060400",
229						   "pciclass0604";
230
231				reg = <0x5000 0x0 0x0 0x0 0x0>;
232				#address-cells = <3>;
233				#size-cells = <2>;
234				device_type = "pci";
235				#interrupt-cells = <1>;
236				interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
237				interrupt-parent = <&liointc1>;
238				interrupt-map-mask = <0 0 0 0>;
239				interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>;
240				ranges;
241				external-facing;
242			};
243
244			pcie@b,0 {
245				compatible = "pci0014,7a09.0",
246						   "pci0014,7a09",
247						   "pciclass060400",
248						   "pciclass0604";
249
250				reg = <0x5800 0x0 0x0 0x0 0x0>;
251				#address-cells = <3>;
252				#size-cells = <2>;
253				device_type = "pci";
254				#interrupt-cells = <1>;
255				interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
256				interrupt-parent = <&liointc1>;
257				interrupt-map-mask = <0 0 0 0>;
258				interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>;
259				ranges;
260				external-facing;
261			};
262
263			pcie@c,0 {
264				compatible = "pci0014,7a09.0",
265						   "pci0014,7a09",
266						   "pciclass060400",
267						   "pciclass0604";
268
269				reg = <0x6000 0x0 0x0 0x0 0x0>;
270				#address-cells = <3>;
271				#size-cells = <2>;
272				device_type = "pci";
273				#interrupt-cells = <1>;
274				interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
275				interrupt-parent = <&liointc1>;
276				interrupt-map-mask = <0 0 0 0>;
277				interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>;
278				ranges;
279				external-facing;
280			};
281
282			pcie@d,0 {
283				compatible = "pci0014,7a19.0",
284						   "pci0014,7a19",
285						   "pciclass060400",
286						   "pciclass0604";
287
288				reg = <0x6800 0x0 0x0 0x0 0x0>;
289				#address-cells = <3>;
290				#size-cells = <2>;
291				device_type = "pci";
292				#interrupt-cells = <1>;
293				interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
294				interrupt-parent = <&liointc1>;
295				interrupt-map-mask = <0 0 0 0>;
296				interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>;
297				ranges;
298				external-facing;
299			};
300
301			pcie@e,0 {
302				compatible = "pci0014,7a09.0",
303						   "pci0014,7a09",
304						   "pciclass060400",
305						   "pciclass0604";
306
307				reg = <0x7000 0x0 0x0 0x0 0x0>;
308				#address-cells = <3>;
309				#size-cells = <2>;
310				device_type = "pci";
311				#interrupt-cells = <1>;
312				interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
313				interrupt-parent = <&liointc1>;
314				interrupt-map-mask = <0 0 0 0>;
315				interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>;
316				ranges;
317				external-facing;
318			};
319
320		};
321	};
322};
323
324