1// SPDX-License-Identifier: GPL-2.0 2 3/dts-v1/; 4 5#include <dt-bindings/interrupt-controller/irq.h> 6 7/ { 8 compatible = "loongson,loongson2k1000"; 9 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu0: cpu@0 { 18 device_type = "cpu"; 19 compatible = "loongson,gs264"; 20 reg = <0x0>; 21 #clock-cells = <1>; 22 clocks = <&cpu_clk>; 23 }; 24 }; 25 26 cpu_clk: cpu_clk { 27 #clock-cells = <0>; 28 compatible = "fixed-clock"; 29 clock-frequency = <800000000>; 30 }; 31 32 cpuintc: interrupt-controller { 33 #address-cells = <0>; 34 #interrupt-cells = <1>; 35 interrupt-controller; 36 compatible = "mti,cpu-interrupt-controller"; 37 }; 38 39 package0: bus@10000000 { 40 compatible = "simple-bus"; 41 #address-cells = <2>; 42 #size-cells = <2>; 43 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */ 44 0 0x40000000 0 0x40000000 0 0x40000000 45 0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>; 46 47 pm: reset-controller@1fe07000 { 48 compatible = "loongson,ls2k-pm"; 49 reg = <0 0x1fe07000 0 0x422>; 50 }; 51 52 liointc0: interrupt-controller@1fe11400 { 53 compatible = "loongson,liointc-2.0"; 54 reg = <0 0x1fe11400 0 0x40>, 55 <0 0x1fe11040 0 0x8>, 56 <0 0x1fe11140 0 0x8>; 57 reg-names = "main", "isr0", "isr1"; 58 59 interrupt-controller; 60 #interrupt-cells = <2>; 61 62 interrupt-parent = <&cpuintc>; 63 interrupts = <2>; 64 interrupt-names = "int0"; 65 66 loongson,parent_int_map = <0xffffffff>, /* int0 */ 67 <0x00000000>, /* int1 */ 68 <0x00000000>, /* int2 */ 69 <0x00000000>; /* int3 */ 70 }; 71 72 liointc1: interrupt-controller@1fe11440 { 73 compatible = "loongson,liointc-2.0"; 74 reg = <0 0x1fe11440 0 0x40>, 75 <0 0x1fe11048 0 0x8>, 76 <0 0x1fe11148 0 0x8>; 77 reg-names = "main", "isr0", "isr1"; 78 79 interrupt-controller; 80 #interrupt-cells = <2>; 81 82 interrupt-parent = <&cpuintc>; 83 interrupts = <3>; 84 interrupt-names = "int1"; 85 86 loongson,parent_int_map = <0x00000000>, /* int0 */ 87 <0xffffffff>, /* int1 */ 88 <0x00000000>, /* int2 */ 89 <0x00000000>; /* int3 */ 90 }; 91 92 rtc0: rtc@1fe07800 { 93 compatible = "loongson,ls2k1000-rtc"; 94 reg = <0 0x1fe07800 0 0x78>; 95 interrupt-parent = <&liointc0>; 96 interrupts = <60 IRQ_TYPE_LEVEL_LOW>; 97 }; 98 99 uart0: serial@1fe00000 { 100 compatible = "ns16550a"; 101 reg = <0 0x1fe00000 0 0x8>; 102 clock-frequency = <125000000>; 103 interrupt-parent = <&liointc0>; 104 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 105 no-loopback-test; 106 }; 107 108 pci@1a000000 { 109 compatible = "loongson,ls2k-pci"; 110 device_type = "pci"; 111 #address-cells = <3>; 112 #size-cells = <2>; 113 114 reg = <0 0x1a000000 0 0x02000000>, 115 <0xfe 0x00000000 0 0x20000000>; 116 117 ranges = <0x01000000 0x0 0x00000000 0x0 0x18000000 0x0 0x00010000>, 118 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; 119 120 gmac@3,0 { 121 compatible = "pci0014,7a03.0", 122 "pci0014,7a03", 123 "pciclass0c0320", 124 "pciclass0c03"; 125 126 reg = <0x1800 0x0 0x0 0x0 0x0>; 127 interrupts = <12 IRQ_TYPE_LEVEL_LOW>, 128 <13 IRQ_TYPE_LEVEL_LOW>; 129 interrupt-names = "macirq", "eth_lpi"; 130 interrupt-parent = <&liointc0>; 131 phy-mode = "rgmii"; 132 mdio { 133 #address-cells = <1>; 134 #size-cells = <0>; 135 compatible = "snps,dwmac-mdio"; 136 phy0: ethernet-phy@0 { 137 reg = <0>; 138 }; 139 }; 140 }; 141 142 gmac@3,1 { 143 compatible = "pci0014,7a03.0", 144 "pci0014,7a03", 145 "pciclass0c0320", 146 "pciclass0c03", 147 "loongson, pci-gmac"; 148 149 reg = <0x1900 0x0 0x0 0x0 0x0>; 150 interrupts = <14 IRQ_TYPE_LEVEL_LOW>, 151 <15 IRQ_TYPE_LEVEL_LOW>; 152 interrupt-names = "macirq", "eth_lpi"; 153 interrupt-parent = <&liointc0>; 154 phy-mode = "rgmii"; 155 mdio { 156 #address-cells = <1>; 157 #size-cells = <0>; 158 compatible = "snps,dwmac-mdio"; 159 phy1: ethernet-phy@1 { 160 reg = <0>; 161 }; 162 }; 163 }; 164 165 ehci@4,1 { 166 compatible = "pci0014,7a14.0", 167 "pci0014,7a14", 168 "pciclass0c0320", 169 "pciclass0c03"; 170 171 reg = <0x2100 0x0 0x0 0x0 0x0>; 172 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 173 interrupt-parent = <&liointc1>; 174 }; 175 176 ohci@4,2 { 177 compatible = "pci0014,7a24.0", 178 "pci0014,7a24", 179 "pciclass0c0310", 180 "pciclass0c03"; 181 182 reg = <0x2200 0x0 0x0 0x0 0x0>; 183 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 184 interrupt-parent = <&liointc1>; 185 }; 186 187 sata@8,0 { 188 compatible = "pci0014,7a08.0", 189 "pci0014,7a08", 190 "pciclass010601", 191 "pciclass0106"; 192 193 reg = <0x4000 0x0 0x0 0x0 0x0>; 194 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 195 interrupt-parent = <&liointc0>; 196 }; 197 198 pcie@9,0 { 199 compatible = "pci0014,7a19.0", 200 "pci0014,7a19", 201 "pciclass060400", 202 "pciclass0604"; 203 204 reg = <0x4800 0x0 0x0 0x0 0x0>; 205 #address-cells = <3>; 206 #size-cells = <2>; 207 device_type = "pci"; 208 #interrupt-cells = <1>; 209 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 210 interrupt-parent = <&liointc1>; 211 interrupt-map-mask = <0 0 0 0>; 212 interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>; 213 ranges; 214 external-facing; 215 }; 216 217 pcie@a,0 { 218 compatible = "pci0014,7a09.0", 219 "pci0014,7a09", 220 "pciclass060400", 221 "pciclass0604"; 222 223 reg = <0x5000 0x0 0x0 0x0 0x0>; 224 #address-cells = <3>; 225 #size-cells = <2>; 226 device_type = "pci"; 227 #interrupt-cells = <1>; 228 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 229 interrupt-parent = <&liointc1>; 230 interrupt-map-mask = <0 0 0 0>; 231 interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>; 232 ranges; 233 external-facing; 234 }; 235 236 pcie@b,0 { 237 compatible = "pci0014,7a09.0", 238 "pci0014,7a09", 239 "pciclass060400", 240 "pciclass0604"; 241 242 reg = <0x5800 0x0 0x0 0x0 0x0>; 243 #address-cells = <3>; 244 #size-cells = <2>; 245 device_type = "pci"; 246 #interrupt-cells = <1>; 247 interrupts = <2 IRQ_TYPE_LEVEL_LOW>; 248 interrupt-parent = <&liointc1>; 249 interrupt-map-mask = <0 0 0 0>; 250 interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>; 251 ranges; 252 external-facing; 253 }; 254 255 pcie@c,0 { 256 compatible = "pci0014,7a09.0", 257 "pci0014,7a09", 258 "pciclass060400", 259 "pciclass0604"; 260 261 reg = <0x6000 0x0 0x0 0x0 0x0>; 262 #address-cells = <3>; 263 #size-cells = <2>; 264 device_type = "pci"; 265 #interrupt-cells = <1>; 266 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 267 interrupt-parent = <&liointc1>; 268 interrupt-map-mask = <0 0 0 0>; 269 interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>; 270 ranges; 271 external-facing; 272 }; 273 274 pcie@d,0 { 275 compatible = "pci0014,7a19.0", 276 "pci0014,7a19", 277 "pciclass060400", 278 "pciclass0604"; 279 280 reg = <0x6800 0x0 0x0 0x0 0x0>; 281 #address-cells = <3>; 282 #size-cells = <2>; 283 device_type = "pci"; 284 #interrupt-cells = <1>; 285 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 286 interrupt-parent = <&liointc1>; 287 interrupt-map-mask = <0 0 0 0>; 288 interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>; 289 ranges; 290 external-facing; 291 }; 292 293 pcie@e,0 { 294 compatible = "pci0014,7a09.0", 295 "pci0014,7a09", 296 "pciclass060400", 297 "pciclass0604"; 298 299 reg = <0x7000 0x0 0x0 0x0 0x0>; 300 #address-cells = <3>; 301 #size-cells = <2>; 302 device_type = "pci"; 303 #interrupt-cells = <1>; 304 interrupts = <5 IRQ_TYPE_LEVEL_LOW>; 305 interrupt-parent = <&liointc1>; 306 interrupt-map-mask = <0 0 0 0>; 307 interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>; 308 ranges; 309 external-facing; 310 }; 311 312 }; 313 }; 314}; 315 316